Prosecution Insights
Last updated: August 17, 2026
Application No. 18/981,315

OPTIMIZING SMMU CONTEXT SAVE AND RESTORE

Non-Final OA §103
Filed
Dec 13, 2024
Examiner
PANDEY, KESHAB R
Art Unit
2176
Tech Center
2100 — Computer Architecture & Software
Assignee
Qualcomm Incorporated
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
9m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
325 granted / 371 resolved
+32.6% vs TC avg
Moderate +8% lift
Without
With
+8.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
13 currently pending
Career history
381
Total Applications
across all art units

Statute-Specific Performance

§101
7.5%
-32.5% vs TC avg
§103
52.3%
+12.3% vs TC avg
§102
16.4%
-23.6% vs TC avg
§112
15.5%
-24.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 371 resolved cases

Office Action

§103
Detailed Action Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-3, 10-11, 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Offen [20150178091], in view of save [WO 2023177408 A1]. As to claim 1, Offen [20150178091] teaches 1. A method of saving a system memory management unit (SMMU) context for a system, comprising: initializing a stored content of a plurality of configuration registers for the component [0018: “context save latency is reduced by restoring only those context registers with saved state that differs from the reset value of registers. A system agent monitors access to the design blocks and sets a dirty bit to indicate which design block has registers that have changed since the last context save. During a context save operation, the system agent bypasses design blocks that have not had context changes since the latest context save operation, and only saves context registers for design blocks that have changed context. ”- reset initializes]; identifying a subset of the plurality of configuration registers whose stored content has changed during a monitoring period that begins following the initializing and ends at a start of a transition of the system to a non-retention state in which the stored content for the plurality of configuration registers is lost [0018: “A system agent monitors access to the design blocks and sets a dirty bit to indicate which design block has registers that have changed since the last context save. During a context save operation, the system agent bypasses design blocks that have not had context changes since the latest context save operation, and only saves context registers for design blocks that have changed context. In one embodiment, the system agent marks a bit-field for each context register that is changed to a value that differs from the reset value of the register.” And 0017: “Additionally, context save and restore latency can be particularly high for design blocks that lose context information during deep sleep states. ”]; and writing a content of the subset of the plurality of configuration registers to an image in a system memory after an end of the monitoring period [0018: “During a context save operation, the system agent bypasses design blocks that have not had context changes since the latest context save operation, and only saves context registers for design blocks that have changed context.” And 0041: “ In one exemplary embodiment, the memory access units 564 include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 572 in the memory unit 570”- data is saved for restoration is written in the non-volatile memory and data written in address form is equivalent to image address] But, does not explicitly teach writing in the SMMU in the memory. However, Save [WO 2023177408 A1] teaches writing in the SMMU image in the memory [0022: “The computing device 100 includes a save-restore engine (SRE) 102. The SRE 102 is configured to save, in an isolated local memory 106, configuration data, e.g., status data and configuration data, for an AC component or other registers, e.g., the AC component 112, located in a power domain 150 affected by a power collapse event.” And 0006: “The SRE is configured to use an isolated local memory that has an always-on or standby power rail during power collapse events. The isolation of the local memory protects the configuration data from access by untrusted components on the SoC. In addition, the isolation of the local memory makes it safe from compromised application software. ” and 0084: “a computing device can include a generic module or client device that has a respective generic AC component, e.g., an SMMU. Because it can be difficult or impossible to adapt the AC component to support the save and restore operations for the SRE, the computing device 100 can include a widget, e.g., a generic save-restore widget 500, to help support the save and restore operations for the SRE.”] It would have been obvious to person of ordinary skill in the art before the effective filing date of the claimed invention to combine teaching of offen and save because both are directed to saving data. Furthermore, Save improves upon Offen by being able to write the data in SMMU memory component such that data can be restored later on efficiently. As to claim 2, Save teaches comprising encrypting the SMMU image prior to writing the SMMU image to the system memory [0031: “As another example, the isolated local memory 106 can include a DRAM that can be used to save and restore the configuration data of the AC component, and the system can protect the configuration data stored in the DRAM against potential tampering using cryptographic methods, such as authentication through encryption/decryption, anti-replay protection, and so on.”]. As to claim 3, Save teaches writing the SMMU image to the system memory comprises writing the SMMU image to a data authentication and encryption portion of the system memory [0031: “As another example, the isolated local memory 106 can include a DRAM that can be used to save and restore the configuration data of the AC component, and the system can protect the configuration data stored in the DRAM against potential tampering using cryptographic methods, such as authentication through encryption/decryption, anti-replay protection, and so on. ”]. . As to claim 10-11, Combination of offen and Save teach this claim according to the reasoning set forth in claim 1-2 supra. As to claim 17, Combination of offen and Save teach this claim according to the reasoning set forth in claim 1supra. Furthermore, Offen teach an driver configured to set a bit [ 0018: “In one embodiment, the system agent marks a bit-field for each context register that is changed to a value that differs from the reset value of the register.”.” ”- it would be obvious to integrate system agent to SMMU such that bit for each of the register can be marked for efficient operation] As to claim 18, Combination of offen and Save teach this claim according to the reasoning set forth in claim 2 supra. Allowable Subject Matter Claim 4-9 and 12-16, 19-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KESHAB R PANDEY whose telephone number is (571)270-0176. The examiner can normally be reached Monday-Friday 9:00-5:00(ET). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at (571) 270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KESHAB R PANDEY/Primary Examiner, Art Unit 2176
Read full office action

Prosecution Timeline

Dec 13, 2024
Application Filed
Jun 24, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12705068
ADJUSTING COMMANDS FOR APPLICATION EXECUTION
2y 6m to grant Granted Aug 11, 2026
Patent 12705069
BEST-KNOWN CONFIGURATION (BKC) OF NODES IN A FIRMWARE FRAMEWORK
2y 4m to grant Granted Aug 11, 2026
Patent 12693870
Edge Device Configuration System and Method
2y 6m to grant Granted Jul 28, 2026
Patent 12687912
TRANSMITTING/RECEIVING DEVICE FOR SELECTIVELY WAKING UP A SUBSCRIBER STATION OF A SERIAL BUS SYSTEM AND METHOD FOR SELECTIVELY WAKING UP A SUBSCRIBER STATION IN A SERIAL BUS SYSTEM
1y 10m to grant Granted Jul 21, 2026
Patent 12675130
CHIP, CHIP SYSTEM, AND TIMESTAMP SYNCHRONIZATION METHOD
2y 2m to grant Granted Jul 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
96%
With Interview (+8.3%)
2y 5m (~9m remaining)
Median Time to Grant
Low
PTA Risk
Based on 371 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month