DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed May 20, 2026 have been fully considered but they are not persuasive.
Applicant’s first argument is that the first and second portions taught by Fazzi are connected to different voltage domains.
This is not persuasive because as discussed in the rejection below the claims require that the delay unit comprises a first portion and one more second portions coupled to a common supply voltage. Fazzi discloses that the second portions 12 are coupled between VCCrx and GNDrx, thus all of the one or more second portions are coupled to a common supply voltage. The claim does not require that both the first and second portions are coupled to the same common supply voltage.
Applicant’s second argument is that Fazzi does not disclose a delay line unit configured for an AND gate logic operation.
One skilled in the art would understand that AND logic gate operation, which is a logical high output when all of the inputs are logically high and a logical low output when any one input is logically low. Fazzi discloses, in Column 7: lines 40-50, that when the RX node is high the pull up current is higher tending to bring a high voltage to the RX node and when the RX node is low the pull down current is lower tending to bring a low voltage to the RX node. Therefore the receiver circuit operations as an AND gate since it has a logically high output when the input is high and a logically low output when the input is low.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 12-14, and 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fazzi et al. (US 7,821,293).
In regard to Claim 1:
Fazzi discloses, in Figure 3, a circuit comprising:
one or more delay line units (10), wherein each of the delay line units comprises: a first portion (11) and one or more (13, 14) second portions (12) coupled to a common supply voltage (the all of the portions of 12 are connected between Vccrx and GNDrx) wherein:
the first portion (11) comprises a NAND gate (Column 5: lines 34-39); and
each of the one or more second portions (12) comprises a PMOS device (P3) and first (N2), second (N3), and third (N1) NMOS devices, and wherein:
each of the one or more delay line units (10) is configured for an AND gate logic operation (Column 6: lines 15-24).
In regard to Claim 2:
Fazzi discloses, in Figure 3, the circuit of claim 1, wherein for a respective delay line unit: the first NMOS device (N2) is coupled between an output (Z*) of the respective delay line unit (10) and a reset input (recovery enable).
In regard to Claim 3:
Fazzi discloses, in Figure 3, the circuit of claim 1, wherein for a respective delay line unit (10): a gate input of the PMOS device (P3) is coupled to a gate input of the second (N3) NMOS device (the gates of P3 and N3 are coupled together).
In regard to Claim 4:
Fazzi discloses, in Figure 3, the circuit of claim 1, wherein for a respective delay line unit (10): the second (N3) and the third (N1) NMOS devices are coupled in series (N1 and N3 are in series).
In regard to Claim 12:
Fazzi discloses, in Figure 3, a method comprising:
receiving first (A) and second (Tx reset) input signals at a first portion (11) of a delay line unit (10) having the first portion (11) and one or more (13, 14) second portions (12) coupled to a common supply voltage (the all of the portions of 12 are connected between Vccrx and GNDrx); and
activating a first NMOS device (N8) to provide conduction to an output of the delay line unit (10), wherein:
at a second portion (13) among the one or more second portions of the delay line unit (12), the first NMOS device (N8) is coupled between a reset input (N8 is between TX reset at N9 and P9) and the output (Z*); and
the first NMOS device (N8) is activated upon receiving the first input signal (A).
In regard to Claim 13:
Fazzi discloses, in Figure 3, the method of claim 12, wherein the first portion (11) comprises a NAND gate (Column 5: lines 34-39), and further comprising: in response to a transition of an output of the NAND gate (11, Column 5: lines 34-39), providing conduction to the output (Z*) through a PMOS device (P3) of the second portion (12, where the output of 11 is coupled to the gate of P3 for conduction to the output Z*).
In regard to Claim 14:
Fazzi discloses, in Figure 3, the method of claim 13, wherein: a gate of the PMOS device (P3) is coupled to a gate of a second NMOS device (N3) of the second portion, and the second NMOS device (N3) is coupled to a third NMOS device (N2) in series.
In regard to Claim 18:
Fazzi discloses, in Figure 3, a non-transitory computer-readable medium storing computer-readable code for fabrication of a circuit, comprising:
one or more delay line units (10), wherein each of the delay line units comprises: a first portion (11) and one or more (13, 14) second portions (12) coupled to a common supply voltage (the all of the portions of 12 are connected between Vccrx and GNDrx), wherein:
the first portion (11) comprises a NAND gate (Column 5: lines 34-39); and
each of the one or more second portions (12) comprises a PMOS device (P3) and first (N2), second (N3), and third (N1) NMOS devices, and wherein:
each of the one or more delay line units (10) is configured for an AND gate logic operation (Column 6: lines 15-24).
In regard to Claim 19:
Fazzi discloses, in Figure 3, the non-transitory computer-readable medium of claim 18, wherein for a respective delay line unit (10): the first NMOS device (N2) is coupled between an output (Z*) of the respective delay line unit (10) and a reset input (recovery enable).
In regard to Claim 20:
Fazzi discloses, in Figure 3, the non-transitory computer-readable medium of claim 18, wherein for a respective delay line unit (10): a gate input of the PMOS device (P3) is coupled to a gate input of the second (N3) NMOS device (the gates of P3 and N3 are coupled together); and the second (N3) and the third (N1) NMOS devices are coupled in series (N1 and N3 are in series).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fazzi et al. (US 7,821,293), in view of Harris et al. (US 20090085629).
In regard to Claim 17:
Fazzi discloses, in Figure 3, the circuit as claimed in claim 1 (see the rejection of Claim 1 above), wherein the circuit is coupled to the clock generator circuit (see clock generator taught by Nandi below) and the pulse generator circuit (see pulse generator taught by Nandi below), and wherein the system is configured to predict a voltage droop of a processing unit (Column 6: lines 37-53), but does not disclose a clock generator circuit and a pulse generator circuit.
Harris discloses a clock generator circuit (Figure 5B: 524) and a pulse generator circuit (Figure 13A: 1300).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the clock generator and pulse generator taught by Harris with the delay circuit taught by Fazzi, in order to save energy when distributing a clock signal, which may be measured by its efficiency with respect to power, latency and robustness (Harris Paragraph 0004).
Allowable Subject Matter
Claims 5-11 and 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to John W Poos whose telephone number is (571)270-5077. The examiner can normally be reached M-Th 8-5.
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/JOHN W POOS/Primary Examiner, Art Unit 2896
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