Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
This office acknowledges receipt of the following item(s) from the Applicant:Information Disclosure Statement (IDS) was considered.
Papers submitted under 35 U.S.C. 119(a)-(d) have been placed of record in thefile.
Claims 1-13 are present for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 5, and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 20090201742 A1).
Regarding claim 1: Lee discloses a floating gate non-volatile memory cell (FIG. 7a), which comprises from a first input terminal a first transistor (terminal of M106, FIG. 1; terminal of transistor 735, FIG. 7a) with a large floating gate (FG 738, FIG. 7a, size can be made large for needed operation, par. 117), and from a second input terminal a second transistor (terminal of M102, FIG. 1; terminal of transistor 225, FIG. 7a) with a smaller floating gate (FG 228, FIG. 7a; for operation, physical size of one paired transistor can be larger/smaller than the other to achieve a desired size ratio, thus one floating gate can have a smaller floating gate, par. 117) than the first transistor, the first transistor being connected in series via its floating gate to the floating gate of the second transistor (floating gate connection at: 110, FIG. 1; FG of 785, FIG. 7a), said electronic circuit being arranged so as to read and load the floating-gate memory structure (read and programming for structure, par. 116), characterised in that the first transistor is converted into the form of a MOS-type transistor to serve directly as a transistor (MOS transistor 735 formed, FIG. 7a, par. 115-116 and 145) for reading the floating-gate memory structure.
Regarding claim 2: Lee discloses a floating gate non-volatile memory cell (FIG. 7a), characterised in that the electronic circuit is integrated with the floating-gate memory structure in a P-type silicon substrate (205, FIG. 7a), and in that the first transistor for implementing a first capacitor (storage capacitor of MOS 735, par. 117) of the memory structure is converted into a PMOS-type transistor (P-type MOS 735, par. 115) with a source connected to the substrate connected to the first input terminal of the memory structure (FIG. 7a), and a drain enabling reading of the state-of-charge of the memory structure in connection with a read unit (drain 736 connected to bitline BL, FIG. 7a).
Regarding claim 5: Lee discloses a floating gate non-volatile memory cell (FIG. 7a), characterised in that the surface ratio between the two PMOS transistors implementing integrated first and second capacitors Cc and Ct of the electronic circuit is greater than 10 times (PMOS 225 and 735, par. 84 and 115; 225 as capacitor, par. 84; storage capacitor of 735, par. 117; size ratio between 225 and 735 made to be greater than 10 times, par. 18 and 139).
Regarding claim 7: Lee discloses a floating gate non-volatile memory cell (FIG. 7a), characterised in that a read unit (sense amplifier of 615, FIG. 6c) is connected to the drain of the first PMOS transistor (drain of PMOS transistor 735 to bitline BL, par. 115, FIG. 7a) so as to determine the state-of-charge of the floating-gate memory structure (reading operation on the floating gate memory, par. 104).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20090201742 A1) in view of Derierling et al. (US 5111069 A).
Regarding claim 6: Lee does not disclose an electronic circuit, characterized in that the first PMOS transistor is made with a width w equal to 2.24 µm and a length l equal to 1.75 µm, which gives a surface area at the floating gate in the range of 3.92 µm², and in that the second PMOS transistor is made over a width w equal to 0.65 µm and over a length l equal to 0.5 µm, which gives a surface area at the floating gate in the range of 0.325 µm², which is more than 12 times smaller than the surface area of the first PMOS transistor.
Derierling does disclose a layout for transistors characterised in that the first PMOS transistor is made with a width w equal to 2.24 µm (width minimum of 1.5 microns, col. 2 ll. 12-14) and a length l equal to 1.75 µm (minimum length is 1.2 microns, col. 2 ll. 11-12), which gives a surface area at the floating gate in the range of 3.92 µm² (area is inherent to the given width and length of the transistor), and in that the second PMOS transistor is made over a width w equal to 0.65 µm and over a length l equal to 0.5 µm, which gives a surface area at the floating gate in the range of 0.325 µm², which is more than 12 times smaller than the surface area of the first PMOS transistor. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have a range of widths and lengths for the transistors of the circuit and the size ratio between the transistors given, since it has been held that where the general conditions of a claim are disclosed in the prior art the optimum or workable ranges involves only routine skill in the art.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the transistors of Lee with the configuration of Derierling to allow the circuit to have transistors be the same dimensions as the claimed invention.
Allowable Subject Matter
Claims 3-4 and 8-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject
matter:
Claims include allowable subject matter since the prior art made of record and considered pertinent to the applicants’ disclosure, taken individually or in combination, does not teach or suggest the claimed invention having: the first transistor configured as a read transistor allows interfacing this transistor in the read mode by means of protection transistors where the parasitic capacitive charges of these protection transistors do not influence the coupling of the first input terminal or of the second input terminal on the floating gate, and in that the size of the read transistor allows significantly reducing the read offset as in claim 3; in order to avoid the use of an original read transistor having an associated parasitic capacitance, so as to increase the coupling factor of a programming voltage and thus to reduce the value of the programming voltage necessary to obtain a given floating-gate voltage as in claim 4; perform charging through the second PMOS transistor with a small capacitance by tunnel effect, in that the first PMOS transistor is connected via a source and a substrate to the programming terminal , while a drain of the first PMOS transistor is connected to a source and a substrate of the second PMOS transistor, a gate of which is biased by a battery voltage, and in that the first PMOS transistor serves as a switch for connecting the programming terminal to the second input terminal, if the voltage on the gate of the first PMOS transistor is at least at a voltage equivalent to or lower than the battery voltage lower than a programming voltage as in claim 9; a gate of which is biased by a battery voltage, and in that the first PMOS transistor can be controlled on a gate to be rendered conductive or preferably non-conductive so as not to have a connection with the programming voltage terminal if a drain of the second PMOS transistor is connected to the first input terminal of the first PMOS transistor with a high coupling capacitance as in claim 10; in that the first NMOS transistor of each pair is a DEMOS transistor biased on a gate by a battery voltage, while the second transistor of each pair is an NMOS type transistor respectively controlled on a gate by a control signal as in claim 11; a third PMOS transistor is provided with a large second floating gate, and in that from the first input terminal, a fourth PMOS transistor is provided with a smaller second floating gate than the third PMOS transistor as in claim 12; the read unit comprises a first DEMOS transistor connected by a drain to the drain of the first PMOS read transistor , and a second DEMOS transistor connected by a drain to a drain of a second PMOS read transistor of the third capacitor, and in that the read unit is configured to output at least one signal (pol-bit-out) of the state-of-charge of the floating gates as in claim 8 and13.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY THINH TANG whose telephone number is (571)272-6845. The examiner can normally be reached Monday-Friday 7:30-5:00 ET.
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/ANTHONY THINH TANG/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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