DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 6/30/2026 with respect to the 102 and 103 rejections have been fully considered but they are not persuasive.
Applicant argues that Shutkin teaches performing a flooding decoding process for columns of a first set and layered decoding for the second set, and that columns of the first set (which was cited in the Office Action as an additional teaching of independently processed non-punctured first variable nodes) are punctured as discussed in paragraphs 25 and 27.
The Examiner asserts that the core teaching cited in the Office Action still teaches the claimed subject matter. For example, Shutkin teaches in paragraph 160 independently performing variable node processing actions A, B, and C on non punctured columns. While the Examiner acknowledges that Shutkin may teach additional embodiments not applicable to the claims at hand, that does not change the fact that Shutkin still teaches the claimed language as shown in the updated rejection below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 15 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Shutkin et al (US Pat. Pub. 2020/0162107; hereinafter referred to as Shutkin).
As per claim 15: Shutkin teaches a decoding method, the decoding method comprising:
receiving a low density parity check (LDPC) code (paragraphs 59-60); and
decoding the LDPC code (paragraph 60; Fig. 2, 14) based on a scheduling table (Figs. 11-12), the scheduling table indicating a processing order of a plurality of rows included in a parity check matrix and a plurality of columns included in each of the plurality of rows of the parity check matrix (Figs. 11-12), the decoding of the LDPC code including,
independently performing variable node processing on one or more first variable nodes (paragraph 19 and 160, actions A, B, and C; see also paragraph 128), the one or more first variable nodes being variable nodes that do not correspond to a puncturing area or a diagonal matrix area of the parity check matrix (paragraph 78; Fig. 6, columns except columns 1 and 2), and
performing variable node processing on one or more second variable nodes (paragraph 23 and 160, actions D, E, F, G, H, and I; see also paragraph 128), the one or more second variable nodes being variable nodes corresponding to the puncturing area or the diagonal matrix area of the parity check matrix (paragraph 78; Fig. 6, columns 1 and 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shutkin in view of Gunnam (US Pat. Pub. 2010/0042896).
As per claims 1 and 20: Shutkin teaches a decoding apparatus, the decoding apparatus comprising:
a receiver configured to receive a low density parity check (LDPC) code (Fig. 2, 14; paragraphs 59-60);
a scheduling table indicating a desired processing order of a plurality of rows included in a parity check matrix and a plurality of columns included in each of the rows of the parity check matrix (Figs. 11-12); and
processing circuitry configured to,
decode a low density parity check (LDPC) (paragraph 60; Fig. 2, 14) based on the scheduling table (Figs. 11-12), the decoding including,
independently performing variable node processing on one or more first variable nodes (paragraph 19 and 160, actions A, B, and C; see also paragraph 128), the one or more first variable nodes being variable nodes that do not correspond to a puncturing area or a diagonal matrix area of the parity check matrix (paragraph 78; Fig. 6, columns except columns 1 and 2), and
performing variable node processing on one or more second variable nodes (paragraph 23 and 160, actions D, E, F, G, H, and I; see also paragraph 128), the one or more second variable nodes being variable nodes that correspond to the puncturing area or the diagonal matrix area of the parity check matrix (paragraph 78; Fig. 6, columns 1 and 2).
Not explicitly disclosed is a memory configured to store the scheduling table. However, Gunnam in an analogous art teaches a memory (Fig. 5, 504) configured to store a scheduling table indicating a desired processing order of an LDPC decoder (paragraph 72). Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use the schedule memory of Gunnam for storing a scheduling table. This modification would have been obvious for one of ordinary skill in the art at the time of filing because storing the scheduling table of Shutkin would have been necessary, and Gunnam teaches a known way for storing the table.
Claim(s) 2 is rejected under 35 U.S.C. 103 as being unpatentable over Shutkin in view of Gunnam in view of Hsu et al (US Pat. 11,316,532; hereinafter referred to as Hsu).
As per claim 2: Shutkin et al teach the decoding apparatus of claim 1. Not explicitly disclosed is wherein the processing circuitry is further configured to decode the LDPC code by: performing processing on a column included in a second scheduled row of the parity check matrix before processing on all columns included in a first scheduled row of the parity check matrix has been completed. However, Hsu in an analogous art teaches processing circuitry (Fig. 1, 124-125) configured to decode the LDPC code based on the scheduling table (Fig. 7), the decoding including performing processing on at least one column included in a second scheduled row of the parity check matrix (Fig. 7, t=2, Column 2) before processing of all columns included in a first scheduled row of the parity check matrix has been completed (Fig. 7, t=3, Column 1).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use the pipelined decoding architecture of Hsu in the decoder of Shutkin. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have achieved low decoding latency (col. 6, lines 22-26).
Claim(s) 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Shutkin in view of Gunnam in view of Hsu in view of Gunnam et al (US Pat. Pub. 2008/0276156; hereinafter referred to as Gunnam ‘156).
As per claim 6: Shutkin et al teach decoding apparatus of claim 2 above. Not explicitly disclosed is wherein the processing circuitry is configured to decode the LDPC code by: performing check node processing and variable node processing, the check node processing comprising a plurality of check node processing operations, and the variable node processing comprising a plurality of variable node processing operations. However, Gunnam ‘156 in an analogous art teaches processing circuitry configured to decode the LDPC code by performing check node processing and variable node processing (Fig. 4A; CNU and VNU), the check node processing comprising a plurality of check node processing operations, and the variable node processing comprising a plurality of variable node processing operations (paragraph 67).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use the check node and variable node processors of Gunnam ‘156 in the system of Shutkin et al. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Shutkin would have required performing check node and variable node update operations (paragraph 69).
As per claim 7: Gunnam ‘156 further teaches the decoding apparatus of claim 6, wherein the processing circuitry is further configured to: control the plurality of check node processing operations to be sequentially performed based on the desired processing order (paragraph 78); and control the plurality of variable node processing operations to be sequentially performed based on the desired processing order (Fig. 17; paragraph 99).
Claim(s) 16 is rejected under 35 U.S.C. 103 as being unpatentable over Shutkin in view of Hsu.
As per claim 16: Shutkin teaches the decoding method of claim 15. Not explicitly disclosed is wherein the decoding of the LDPC code further includes: performing processing on a column included in a second scheduled row of the parity check matrix before processing on all columns included in a first scheduled row of the parity check matrix has been completed. However, Hsu in an analogous art teaches processing circuitry (Fig. 1, 124-125) configured to decode the LDPC code based on the scheduling table (Fig. 7), the decoding including performing processing on at least one column included in a second scheduled row of the parity check matrix (Fig. 7, t=2, Column 2) before processing of all columns included in a first scheduled row of the parity check matrix has been completed (Fig. 7, t=3, Column 1).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use the pipelined decoding architecture of Hsu in the decoder of Shutkin. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have achieved low decoding latency (col. 6, lines 22-26).
Allowable Subject Matter
Claims 3-5, 8-14, and 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if the double patenting rejection is overcome.
The following is a statement of reasons for the indication of allowable subject matter: None of the prior art of record teach each limitation of dependent claims 3, 8, or 17; particularly in combination with each and every limitation of the parent claim.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVE N NGUYEN whose telephone number is (571)272-7214. The examiner can normally be reached M-F 9-5.
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/STEVE N NGUYEN/Primary Examiner, Art Unit 2111
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