Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is in response to application filed on 12/16/2024. Claims 1-20 are pending for examination.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/16/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 8-12 are objected to because of the following informalities:
In claim 8, line 3, “a the second memory cell array” should be changed to -- the second memory cell array --.
Claims 9-12 are objected since they are depended on objected claim 8.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 8-9 and 13-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Biswas et al., US 2021/0125657 A1.
Regarding claim 1, Biswas teaches a semiconductor memory device (it is taught as a system in Fig.1) comprising:
a substrate (Fig.1, a memory system 10);
a plurality of banks on the substrate (section 0029 and claim 1), the plurality of banks including a first memory cell array of a first size (claim 1; it is taught as the first memory array comprises a first plurality of banks have a first bank size) and a second memory cell array of a second size, the second size being smaller than the first size (claim 1; it is taught as the second memory array comprises a second plurality of banks having a second bank size that is less than the first bank size);
a peripheral circuit between at least two of the plurality of banks (section 0045; The TSVs 32 may be connected together when the DRAMs 16A-16D are stacked through pins between the memories); and
a processor adjacent to the second memory cell array (Fig.12 and section 0040; The cache DRAM 18 includes a memory array 22 and physical layer interface circuit (PHY circuit 24). The PHY circuit 24 is coupled through pins of the cache DRAM 18 to the connection layer 14, and through the connection layer 14 to pins of the SOC 12 and then to a corresponding PHY circuit 26 in the SOC 12. The PHY 26 is coupled to a memory controller 28 in the SOC 12, which further includes various other circuits 30 (e.g. processors, peripherals, etc.).).
Regarding claims 2 and 16, Biswas teaches a first bank among the plurality of banks includes the first memory cell array and the second memory cell array (claim 1; it is taught as a memory including the first type of DRAM and the second type of DRAM), and a distance between the second memory cell array and the processor is shorter than a distance between the first memory cell array and the processor (section 0037; a connection layer 14 may be included in the package, including relatively short interconnect to the cache DRAM(s) 18 (e.g. see FIG. 12).
Regarding claim 3, Biswas teaches the peripheral circuit includes a first peripheral circuit and a second peripheral circuit (claim 1; it is taught as first integrated circuit and second integrated circuit), and the first peripheral circuit and the second peripheral circuit are spaced apart from each other with the plurality of banks interposed therebetween (Fig.12 and claim 5; it is taught as the stack of the plurality of the first integrated circuits is coupled to the second integrated circuit, which means they are apart).
Regarding claim 4, Biswas teaches the processor is included in a plurality of processors, the first bank is included in a plurality of first banks, and each of the plurality of processors is connected to one of the plurality of first banks (Fig.12; section 0040 and section 0043; processors such as circuits 30 is connected to plurality of Main DRAMs).
Regarding claim 5, Biswas teaches the processor is included in a plurality of processors, the first bank is included in a plurality of first banks, and each of the plurality of processor is connected to at least two of the plurality of first banks (Fig.12; section 0040 and section 0043; processors such as circuits 30 is connected to plurality of Main DRAMs).
Regarding claim 8, Biswas teaches the first memory cell array is included in a second bank, of the plurality of banks, and the second memory cell array is included in a third bank of the plurality of banks (Fig.12), and a distance between the processor and the third bank is shorter than a distance between the processor and the second bank (section 0037; a connection layer 14 may be included in the package, including relatively short interconnect to the cache DRAM(s) 18 (e.g. see FIG. 12)).
Regarding claim 9, Biswas teaches the second bank is on a first side of the peripheral circuit and the third bank is on a second side of the peripheral circuit opposite to the first side, and the processor is between the peripheral circuit and the third bank (Fig.12; section 0040; the cache DRAM 18 includes a memory array 22 and physical layer interface circuit (PHY circuit 24). The PHY circuit 24 is coupled through pins of the cache DRAM 18 to the connection layer 14, and through the connection layer 14 to pins of the SOC 12 and then to a corresponding PHY circuit 26 in the SOC 12. The PHY 26 is coupled to a memory controller 28 in the SOC 12, which further includes various other circuits 30 (e.g. processors, peripherals, etc.). The other circuits 30 may be coupled through other pins of the SOC 12 to the opposite side of the connection layer 14 for coupling to other components in a system).
Regarding claim 13, Biswas teaches a fourth bank among the plurality of banks includes the first memory cell array and the second memory cell array (Fig.12), and the processor is adjacent to the second memory cell array within the fourth bank (section 0037; a connection layer 14 may be included in the package, including relatively short interconnect to the cache DRAM(s) 18 (e.g. see FIG. 12).
Regarding claim 14, Biswas teaches further comprising a plurality of processor connected to the fourth bank, wherein the fourth bank includes first rows corresponding to the first memory cell array and second rows corresponding to the second memory cell array (Fig.12) and each of the plurality of processors is adjacent to the second rows within the fourth bank (section 0037; a connection layer 14 may be included in the package, including relatively short interconnect to the cache DRAM(s) 18 (e.g. see FIG. 12).
Regarding claim 15, Biswas teaches a semiconductor memory device (it is taught as a system in Fig.1) comprising:
a substrate (Fig.1, a memory system 10);
a plurality of banks on the substrate (section 0029 and claim 1); a peripheral circuit between the plurality of banks (section 0045; The TSVs 32 may be connected together when the DRAMs 16A-16D are stacked through pins between the memories); and a processor adjacent to the peripheral circuit (Fig.12), wherein the plurality of banks include a first memory cell array of a first size (claim 1; it is taught as the first memory array comprises a first plurality of banks have a first bank size) and a second memory cell array of a second size, the second size smaller than the first size (claim 1; it is taught as the second memory array comprises a second plurality of banks having a second bank size that is less than the first bank size), and wherein a distance between the second memory cell array and the processor is shorter than that a distance between the first memory cell array and the processor (section 0037; a connection layer 14 may be included in the package, including relatively short interconnect to the cache DRAM(s) 18 (e.g. see FIG. 12).
Regarding claim 17, Biswas teaches the plurality of banks include a first bank including the first memory cell array and a second bank including the second memory cell array (claim 1), and the processor is closer to the second bank than the first bank (section 0037; a connection layer 14 may be included in the package, including relatively short interconnect to the cache DRAM(s) 18 (e.g. see FIG. 12).
Regarding claim 18, Biswas teaches the plurality of banks include a third bank including a plurality of the second memory cell array, the plurality of second memory arrays in an array including a plurality of rows (it is taught as one or more memory arrays, array includes rows and columns).
Regarding claim 19, Biswas teaches further comprising: a plurality of the processors inside the third bank (Fig.12), each of the plurality of processors is adjacent to each of the plurality of rows within the third bank (section 0037; a connection layer 14 may be included in the package, including relatively short interconnect to the cache DRAM(s) 18 (e.g. see FIG. 12).
Regarding claim 20, Biswas teaches a memory system comprising: a semiconductor memory device (it is taught as a system in Fig.1) including a plurality of banks (section 0029 and claim 1) and a processor (section 0030), the plurality of banks including a first memory cell array of a first size (claim 1; it is taught as the first memory array comprises a first plurality of banks have a first bank size) and a second memory cell array of a second size, the second size smaller than the first size (claim 1; it is taught as the second memory array comprises a second plurality of banks having a second bank size that is less than the first bank size), and the processor adjacent to the second memory cell array (section 0037; a connection layer 14 may be included in the package, including relatively short interconnect to the cache DRAM(s) 18 (e.g. see FIG. 12); and a memory controller (Fig.12; memory controller 28) configured to control an operation of the semiconductor memory device (section 0044; the memory controller 28 may be configured to write data read from the main DRAMs 16A-16D to the cache DRAM 18 ).
Allowable Subject Matter
Claims 6-7 and 10-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
The limitations not found in the prior art of record include the at least two first banks are divided by the peripheral circuit such that one of the at least two first banks is on a first side of the peripheral circuit and another of the at least two first banks is on a second side of the peripheral circuit opposite to the first side, and each of the processors connected to the at least two first banks is disposed between one of the at least two first banks and the peripheral circuit in combination with the other claimed limitations as described in the claim 6.
The limitations not found in the prior art of record include the peripheral circuit includes a first peripheral circuit and a second peripheral circuit, the at least two first banks are divided by the processor such that one of the at least two first banks is on a first side of the processor and another of the at least two first banks is on a second side of the processor opposite to the first side, the first peripheral circuit is between the processor and the first bank on the first side of the processor , and the second peripheral circuit is between the processor and the first bank on the second side of the processor in combination with the other claimed limitations as described in the claim 7.
The limitations not found in the prior art of record include the plurality of banks include a plurality of second banks and a plurality of third banks, and the plurality of second banks are divided and disposed on a first and second side of the peripheral circuit, and the plurality of third banks are divided and disposed on the first and second side of the peripheral circuit in combination with the other claimed limitations as described in the claim 10 (claims 11-12 are depended on claim 10).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ji et al., US 2022/0093159 A1 teaches a DRAM memory includes: a substrate; a plurality of memory banks arranged in rows and columns on the substrate, each memory bank is divided into three memory blocks in the column direction. Each memory block has a number of memory cells arranged in rows and columns. Dividing each memory bank into three memory blocks in the column direction shortens the length of the memory bank in the row direction, as each memory bank has a certain capacity, so a large drive is no longer required.
When responding to the office action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111 (c).
When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist examiner to locate the appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUA JASMINE SONG whose telephone number is (571)272-4213. The examiner can normally be reached on 9:00am to 5:30pm.
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/HUA J SONG/Primary Examiner, Art Unit 2133