DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-7 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter.
Based upon consideration of all of the relevant factors, claims 1-7 are determined to be directed to an abstract idea. The rationale for this determination is explained below: One of the factors weighing against eligibility is that there is no recitation of a machine or transformation.
In this particular case, the method steps of claim 1 of: “ 1. A method comprising: obtaining, by a processing device, a plurality of data state metrics with respect to a block, wherein each data state metric corresponds to a respective voltage offset bin of a plurality of voltage offset bins, and wherein each data state metric is determined based on a voltage offset associated with the respective voltage offset bin; and storing a voltage offset bin having a lowest voltage offset whose corresponding data state metric satisfies a predefined quality criterion for performing memory access operations with respect to a block family including the block.” are directed to an abstract idea. NOTE: there is no device/apparatus/machine recited in the claims (e.g.-claim 1) and/or there is no practical transformation of a machine that is tied to the claims due to the execution of the recited method steps, hence, the recited method steps are interpreted as abstract ideas which could be performed/narrated mentally. Accordingly, for the reasons provided above, claims 1-7 are directed to an abstract idea, hence, not patent eligible under 35 USC 101.
Claims 1-7 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more. Independent claims 1 is directed to an abstract idea of collecting data, and analyzing the data to provide certain results. For instance, in Electric Power Group, the concept of collecting information, analyzing the collected information, and displaying certain results of the collection and analysis were found to be abstract.
In analyzing claim 1 of the instant application, the limitations “A method comprising: obtaining, by a processing device, a plurality of data state metrics with respect to a block, wherein each data state metric corresponds to a respective voltage offset bin of a plurality of voltage offset bins, and wherein each data state metric is determined based on a voltage offset associated with the respective voltage offset bin; and storing a voltage offset bin having a lowest voltage offset whose corresponding data state metric satisfies a predefined quality criterion for performing memory access operations with respect to a block family including the block.” are directed to an abstract idea. The abstract idea of the instant application is substantially similar to the court identified abstract idea found in Electric Power Group. It is similar because it accesses data, determines/identifies certain data (analysis), and accesses the determined/identified certain data. Other court identified abstract idea are related to the abstract idea identified in the instant application, such as collecting and comparing known information (Classen), obtaining and comparing intangible data (CyberSource) and organizing information through mathematical correlations (Digitech).
Therefore, the claimed invention as a whole does not amount to significantly more than the abstract idea. Dependent claims recite no additional limitation that would amount to significantly more than the abstract idea defined in its respective independent claim. Accordingly, for the reasons provided above, claims 1-7 are directed to an abstract idea, hence, not patent eligible under 35 USC 101.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-11 and 13-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-8, 11-16 and 18-20 of U.S. Patent No. 12,210,759. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims are substantially similar with minor differences and not distinguishing the overall appearance of one over the other. Note: the claims of the instant application are anticipated by the claims of the parent, as outlined in the table below.
Current application-18/982,255
US Patent – 12,210,759
1. A method comprising: obtaining, by a processing device, … a respective voltage offset bin of a plurality of voltage offset bins, …
3. The method of claim 1, …wherein… , performing, with respect to the block,
a memory access operation utilizing
the voltage offset associated with the
respective voltage offset bin to obtain
a corresponding data state metric.
…and wherein each data state metric is determined based on a voltage offset associated with the respective voltage offset bin; and … a voltage offset bin having a lowest voltage offset whose corresponding data state metric satisfies a predefined quality criterion for performing memory access operations with respect to a block family including the block.
1. A method comprising: identifying, by a processing device, a block family; for each voltage offset bin of a plurality of voltage offset bins, performing, with respect to a block, a memory access operation utilizing a voltage offset associated with a respective voltage offset bin to obtain a corresponding data state metric; … based on the corresponding data state metric associated with the plurality of voltage offset bins, a voltage offset bin with a lowest voltage offset in which the corresponding data state metric satisfies a predefined quality criterion; and … for performing subsequent memory access operation with respect to the block family.
2. The method of claim 1, wherein satisfying the predefined quality criterion comprises determining if a value of the data state metric does not exceed a predefined threshold.
6. The method of claim 1, wherein satisfying the predefined quality criterion comprises determining if a value of the data state metric does not exceed a predefined threshold.
4. The method of claim 3, wherein the memory access operation is a read operation.
4. The method of claim 1, wherein the memory access operation is a read operation.
5. The method of claim 1, further comprising: responsive to determining that a memory access operation utilizing the voltage offset associated with the respective voltage offset bin failed to obtain the corresponding data state metric, storing a voltage offset bin that produced an optimal value of the data state metric for performing subsequent memory access operation with respect to a block family including the block.
2. The method of claim 1, further comprising: responsive to determining that the memory access operation utilizing the voltage offset associated with a respective voltage offset bin failed to obtain the corresponding data state metric,….
3. The method of claim 2, further comprising: storing voltage offset bin that produced an optimal value of the data state metric for performing subsequent memory access operation with respect to the block family.
6. The method of claim 5, wherein the optimal value if represented by one of: a minimum value of the data state metric or a maximum value of the data state metric.
7. The method of claim 2, wherein the optimal value if represented by one of: a minimum value of the data state metric or a maximum value of the data state metric.
7. The method of claim 1, wherein the data state metric is a bit error rate.
5. The method of claim 1, wherein the data state metric is a bit error rate.
8. A system comprising: a memory device; and a processing device coupled to the memory device, the processing device to perform operations comprising: obtaining, by a processing device,…
10. The system of claim 8, wherein…
for each voltage offset bin of the
plurality of voltage offset bins,
performing, with respect to the
block, a memory access operation
utilizing the voltage offset
associated with the respective
voltage offset bin to obtain a
corresponding data state metric.
a plurality of data state metrics with respect to a block, wherein each data state metric corresponds to a respective voltage offset bin of a plurality of voltage offset bins, and… storing a voltage offset bin having a lowest voltage offset whose corresponding data state metric satisfies a predefined quality criterion for performing memory access operations with respect to a block family…
8. A system comprising: a memory device; and a processing device coupled to the memory device, the processing device to perform operations comprising: identifying, by a processing device,…
for each voltage offset bin of a plurality of voltage offset bins, performing, with respect to a block, a memory access operation utilizing a voltage offset associated with a respective voltage offset bin to obtain a corresponding data state metric; selecting, based on the corresponding data state metric associated with the plurality of voltage offset bins, a voltage offset bin with a lowest voltage offset in which the corresponding data state metric satisfies a predefined quality criterion; and … for performing subsequent memory access operation with respect to the block family.
9. The system of claim 8, wherein satisfying the predefined quality criterion comprises determining if a value of the data state metric does not exceed a predefined threshold.
13. The system of claim 8, wherein satisfying the predefined quality criterion comprises determining if a value of the data state metric does not exceed a predefined threshold.
11. The system of claim 10, wherein the memory access operation is a read operation.
11. The system of claim 8, wherein the memory access operation is a read operation.
13. The system of claim 12, wherein the optimal value if represented by one of: a minimum value of the data state metric or a maximum value of the data state metric.
14. The system of claim 9, wherein the optimal value if represented by one of: a minimum value of the data state metric or a maximum value of the data state metric.
14. The system of claim 8, wherein the data state metric is a bit error rate.
12. The system of claim 8, wherein the data state metric is a bit error rate.
15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: obtaining, by a processing device,…a respective voltage offset bin of a plurality of voltage offset bins,
17. The non-transitory computer-
readable storage medium of claim
15,… performing, with respect to the
block, a memory access operation
utilizing the voltage offset associated
with the respective voltage offset bin
to obtain a corresponding data state
metric.
and wherein…storing a voltage offset bin having a lowest voltage offset whose corresponding data state metric satisfies a predefined quality criterion for performing memory access operations with respect to a block family including the block.
15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: identifying, by a processing device, a block family; for each voltage offset bin of a plurality of voltage offset bins, performing, with respect to a block, a memory access operation utilizing a voltage offset associated with a respective voltage offset bin to obtain a corresponding data state metric; selecting, based on the corresponding data state metric associated with the plurality of voltage offset bins, a voltage offset bin with a lowest voltage offset in which the corresponding data state metric satisfies a predefined quality criterion; and storing voltage offset bin with the lowest voltage offset for performing subsequent memory access operation with respect to the block family.
16. The non-transitory computer-readable storage medium of claim 15, wherein satisfying the predefined quality criterion comprises determining if a value of the data state metric does not exceed a predefined threshold.
19. The non-transitory computer-readable storage medium of claim 15, wherein satisfying the predefined quality criterion comprises determining if a value of the data state metric does not exceed a predefined threshold.
18. The non-transitory computer-readable storage medium of claim 17, wherein the memory access operation is a read operation.
18. The non-transitory computer-readable storage medium of claim 15, wherein the memory access operation is a read operation.
19. The non-transitory computer-readable storage medium of claim 15, wherein causing the processing device to perform operations further comprising: responsive to determining that a memory access operation utilizing the voltage offset associated with the respective voltage offset bin failed to obtain the corresponding data state metric, storing a voltage offset bin that produced an optimal value of the data state metric for…
16. The non-transitory computer-readable storage medium of claim 15, wherein the processing device is caused to perform operations further comprising: responsive to determining that the memory access operation utilizing the voltage offset associated with a respective voltage offset bin failed to obtain the corresponding data state metric, selecting, … a voltage offset bin that produced an optimal value of the data state metric.
20. The non-transitory computer-readable storage medium of claim 19, wherein the optimal value if represented by one of: a minimum value of the data state metric or a maximum value of the data state metric.
20. The non-transitory computer-readable storage medium of claim 16, wherein the optimal value if represented by one of: a minimum value of the data state metric or a maximum value of the data state metric.
Allowable Subject Matter
Claims 8-20 are objected to because of the presence of the obviousness type double patenting rejection (see above) but would be allowable if the rejection is overcome.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Please see the attached PTO-892. Reyter et al. (US 10,453,537), Ruby et al. (US 8,510,636), Malshe et al. (US 10,347,344), Karakulak et al. (US 9,576,671), Danjean et al. (US 10,276,233) and Bellorado et al. (US 9,236,147) do teach and a programming method of multiple memory cells of a memory device by determining a threshold voltage offset to minimize bit error rate of the programming operation.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS MAMO whose telephone number is (571)270-1726. The examiner can normally be reached Mon-Thu, 7 AM - 5 PM.
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/Elias Mamo/Primary Examiner, Art Unit 2184