Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: POWER REGULATOR FOR DIGITAL CIRCUITRY WITH GATE DELAY BASED FEEDBACK.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 - 3, 8 - 10 and 15 - 18 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Holzmann (US Pub. No. 2017/0163152 A1); (hereinafter Holzmann).
Regarding claim 1, Holzmann [e.g., Figs. 2, 5 and 7] discloses an apparatus for controlling power delivery to one or more digital circuits [e.g., -- FIG. 2 is a simplified block diagram illustrating a system including a delay locked regulator providing a regulated voltage supply to a digital circuit --, Delay Locked Regulator 201], the one or more digital circuits having a functional clock unit to provide a clock signal to the one or more digital circuits [e.g., CLOCK signal provided to flip-flops 210 and 220 as well as Combinational Logic 230, p. 0041 recites “…the circuit uses a clock source that is fed through a chain of gates (inverters shown) that are supplied by the output of the power regulator.”], the apparatus comprising: a first feedback generation unit [e.g., -- refer to Fig. 5 a simplified block diagram illustrating a delay locked regulator --, signal processing circuit 532] to generate a first feedback signal [e.g., signal generated by signal processing unit 532 and supplied to voltage control circuit 536] based on a comparison between a current number of gate delays corresponding to a current clock signal and a target number of gate delays [e.g., digital difference circuit 533 generates error signal (ERROR) based on comparison between binary value (520, current number of gate delays (DIN)) and Target Delay (533, DTARGET) p. 0054 -0055 recites “As shown in FIG. 5, voltage regulation circuit 530 is coupled to delay tracking circuit 510 to receive the binary number representing a gate delay. Voltage regulation circuit 530 also includes a signal processing circuit 532 for providing a control signal DCTRL indicative of a difference between the first binary number 520 with a second binary number Target Delay that represents a target delay. As shown in FIG. 5, signal processing circuit includes a digital difference circuit 533 for providing an error signal ERROR indicative of a difference between the first binary number with the second binary number that represents the target delay….. Digital difference circuit 533 is configured for providing an error signal ERROR indicative of a difference between the first binary number the delay tracking circuit with the second binary number that represents the target delay, shown as Target Delay.”]; and a power regulator unit to adjust the power delivery to the one or more digital circuits based on the first feedback signal [e.g., voltage control circuit 536 adjust supply regulated voltage Vreg based on signal generated by Digital Difference circuit 533].
Regarding claim 2, Holzmann [e.g., Figs. 2, 5 and 7] discloses wherein the first feedback signal represents a difference between the current number of gate delays and the target number of gate delays [e.g., digital difference circuit 533 generates error signal (ERROR) based on comparison between binary value (520, current number of gate delays (DIN)) and Target Delay (533, DTARGET) p. 0054 -0055 recites “As shown in FIG. 5, voltage regulation circuit 530 is coupled to delay tracking circuit 510 to receive the binary number representing a gate delay. Voltage regulation circuit 530 also includes a signal processing circuit 532 for providing a control signal DCTRL indicative of a difference between the first binary number 520 with a second binary number Target Delay that represents a target delay. As shown in FIG. 5, signal processing circuit includes a digital difference circuit 533 for providing an error signal ERROR indicative of a difference between the first binary number with the second binary number that represents the target delay….. Digital difference circuit 533 is configured for providing an error signal ERROR indicative of a difference between the first binary number the delay tracking circuit with the second binary number that represents the target delay, shown as Target Delay.”], and the power regulator unit is configured to adjust the power delivery to the one or more digital circuits to minimize the difference [e.g., controls Vreg based on the difference between DIN and DTARGET to allow DIN to match DTARGET, p.0066 recites “…, the delay of the delay chain can be varied by its voltage supply, which is the output voltage of the voltage regulation circuit. The voltage regulation circuit is configured for adjusting the output voltage, such that the delay of the tapped delay chain matches the target delay. For example, if for a given target delay DTARGET=n, when the loop is settled, the target delay tap point (thermometer code) of the delay chain can be represented by the binary number n.“].
Regarding claim 3, Holzmann [e.g., Figs. 2, 5 and 7] discloses wherein the power regulator unit adjusts the power delivery to the one or more digital circuits [e.g., voltage control circuit 536 adjust supply regulated voltage Vreg] to minimize the difference [e.g., Digital Difference circuit 533 minimizes difference between first binary number (DIN) and second binary number (DTARGET)] by increasing the power delivery to the one or more digital circuits when the current number of gate delays is lower than the target number of gate delays, and decreasing the power delivery to the one or more digital circuits when the current number of gate delays is higher than the target number of gate delays [e.g., controls Vreg based on the difference between DIN and DTARGET to allow DIN to match DTARGET, p.0066 recites “…, the delay of the delay chain can be varied by its voltage supply, which is the output voltage of the voltage regulation circuit. The voltage regulation circuit is configured for adjusting the output voltage, such that the delay of the tapped delay chain matches the target delay. For example, if for a given target delay DTARGET=n, when the loop is settled, the target delay tap point (thermometer code) of the delay chain can be represented by the binary number n.“].
Regarding claim 8, Holzmann [e.g., Figs. 2, 5 and 7] discloses a computer-implemented method [e.g., power regulation for digital circuitry, p. 0003 recites “Embodiments of the present invention are directed to a method and apparatus that can adjust the supply voltage in order to maintain a fixed delay through a circuit with combinational logic and flip-flops despite variations in device parameters caused by process variation and operating conditions, etc.”] of controlling power delivery to one or more digital circuits [e.g., -- FIG. 2 is a simplified block diagram illustrating a system including a delay locked regulator providing a regulated voltage supply to a digital circuit --, Delay Locked Regulator 201], the one or more digital circuits having a functional clock unit to provide a clock signal to the one or more digital circuits [e.g., CLOCK signal provided to flip-flops 210 and 220 as well as Combinational Logic 230, p. 0041 recites “…the circuit uses a clock source that is fed through a chain of gates (inverters shown) that are supplied by the output of the power regulator.”], the method comprising: generating a first feedback signal [e.g., signal generated by signal processing unit 532 and supplied to voltage control circuit 536] based on a comparison between a current number of gate delays corresponding to a current clock signal and a target number of gate [e.g., digital difference circuit 533 generates error signal (ERROR) based on comparison between binary value (520, current number of gate delays (DIN)) and Target Delay (533, DTARGET) p. 0054 -0055 recites “As shown in FIG. 5, voltage regulation circuit 530 is coupled to delay tracking circuit 510 to receive the binary number representing a gate delay. Voltage regulation circuit 530 also includes a signal processing circuit 532 for providing a control signal DCTRL indicative of a difference between the first binary number 520 with a second binary number Target Delay that represents a target delay. As shown in FIG. 5, signal processing circuit includes a digital difference circuit 533 for providing an error signal ERROR indicative of a difference between the first binary number with the second binary number that represents the target delay….. Digital difference circuit 533 is configured for providing an error signal ERROR indicative of a difference between the first binary number the delay tracking circuit with the second binary number that represents the target delay, shown as Target Delay.”]; and adjusting the power delivery to the one or more digital circuits based on the first feedback signal [e.g., voltage control circuit 536 adjust supply regulated voltage Vreg based on signal generated by Digital Difference circuit 533].
Regarding claim 9, Holzmann [e.g., Figs. 2, 5 and 7] discloses wherein the first feedback signal represents a difference between the current number of gate delays and the target number of gate delays [e.g., digital difference circuit 533 generates error signal (ERROR) based on comparison between binary value (520, current number of gate delays (DIN)) and Target Delay (533, DTARGET) p. 0054 -0055 recites “As shown in FIG. 5, voltage regulation circuit 530 is coupled to delay tracking circuit 510 to receive the binary number representing a gate delay. Voltage regulation circuit 530 also includes a signal processing circuit 532 for providing a control signal DCTRL indicative of a difference between the first binary number 520 with a second binary number Target Delay that represents a target delay. As shown in FIG. 5, signal processing circuit includes a digital difference circuit 533 for providing an error signal ERROR indicative of a difference between the first binary number with the second binary number that represents the target delay….. Digital difference circuit 533 is configured for providing an error signal ERROR indicative of a difference between the first binary number the delay tracking circuit with the second binary number that represents the target delay, shown as Target Delay.”], and the power delivery to the one or more digital circuits is adjusted to minimize the difference [e.g., controls Vreg based on the difference between DIN and DTARGET to allow DIN to match DTARGET, p.0066 recites “…, the delay of the delay chain can be varied by its voltage supply, which is the output voltage of the voltage regulation circuit. The voltage regulation circuit is configured for adjusting the output voltage, such that the delay of the tapped delay chain matches the target delay. For example, if for a given target delay DTARGET=n, when the loop is settled, the target delay tap point (thermometer code) of the delay chain can be represented by the binary number n.“].
Regarding claim 10, Holzmann [e.g., Figs. 2, 5 and 7] discloses wherein the power delivery [e.g., voltage control circuit 536] to the digital circuits is adjusted [e.g., voltage control circuit 536 adjust supply regulated voltage Vreg] to minimize the difference [e.g., Digital Difference circuit 533 minimizes difference between first binary number (DIN) and second binary number (DTARGET)] by increasing the power delivery to the one or more digital circuits when the current number of gate delays is lower than the target number of gate delays, and decreasing the power delivery to the one or more digital circuits when the current number of gate delays is higher than the target number of gate delays [e.g., controls Vreg based on the difference between DIN and DTARGET to allow DIN to match DTARGET, p.0066 recites “…, the delay of the delay chain can be varied by its voltage supply, which is the output voltage of the voltage regulation circuit. The voltage regulation circuit is configured for adjusting the output voltage, such that the delay of the tapped delay chain matches the target delay. For example, if for a given target delay DTARGET=n, when the loop is settled, the target delay tap point (thermometer code) of the delay chain can be represented by the binary number n.“].
Regarding claim 15, Holzmann [e.g., Figs. 2, 5 and 7] discloses a system [e.g., -- FIG. 2 is a simplified block diagram illustrating a system including a delay locked regulator providing a regulated voltage supply to a digital circuit --] comprising: a system on chip [e.g., Delay Tracking Circuit 510, Digital Processing Circuit 532 and voltage control circuit 536] comprising one or more digital circuits and a functional clock unit to provide a clock signal to the one or more digital circuits [e.g., CLOCK signal provided to flip-flops 210 and 220 as well as Combinational Logic 230, p. 0041 recites “…the circuit uses a clock source that is fed through a chain of gates (inverters shown) that are supplied by the output of the power regulator.”]; a power stage comprising a power supply circuit to process power delivery to the system on chip [e.g., -- refer to Fig. 5 a simplified block diagram illustrating a delay locked regulator --, signal processing circuit 532]; a first feedback generation unit [e.g., Signal Processing circuit 532] to generate a first feedback signal based on a comparison between a current number of gate delays corresponding to a current clock signal and a target number of gate delays [e.g., digital difference circuit 533 generates error signal (ERROR) based on comparison between binary value (520, current number of gate delays (DIN)) and Target Delay (533, DTARGET) p. 0054 -0055 recites “As shown in FIG. 5, voltage regulation circuit 530 is coupled to delay tracking circuit 510 to receive the binary number representing a gate delay. Voltage regulation circuit 530 also includes a signal processing circuit 532 for providing a control signal DCTRL indicative of a difference between the first binary number 520 with a second binary number Target Delay that represents a target delay. As shown in FIG. 5, signal processing circuit includes a digital difference circuit 533 for providing an error signal ERROR indicative of a difference between the first binary number with the second binary number that represents the target delay….. Digital difference circuit 533 is configured for providing an error signal ERROR indicative of a difference between the first binary number the delay tracking circuit with the second binary number that represents the target delay, shown as Target Delay.”]; and a power regulator unit to adjust the power delivery to the one or more digital circuits based on the first feedback signal [e.g., voltage control circuit 536 adjust supply regulated voltage Vreg based on signal generated by Digital Difference circuit 533].
Regarding claim 16, Holzmann [e.g., Figs. 2, 5 and 7] discloses wherein the system on chip [e.g., Delay Tracking Circuit 510, Digital Processing Circuit 532 and voltage control circuit 536] comprises the first feedback generation unit [e.g., Delay Tracking Circuit 510, Digital Processing Circuit 532] and the power regulator unit [e.g., voltage control circuit 536].
Regarding claim 17, Holzmann [e.g., Figs. 2, 5 and 7] discloses wherein the system on chip [e.g., Delay Tracking Circuit 510, Digital Processing Circuit 532 and voltage control circuit 536] comprises the first feedback generation unit [e.g., signal processing unit 532], and the power stage comprises the power regulator unit [e.g., voltage control circuit 536].
Regarding claim 18, Holzmann [e.g., Figs. 2, 5 and 7] discloses wherein the first feedback generation unit [e.g., Delay Tracking Circuit 510, Digital Processing Circuit 532] is a time-to-digital converter [e.g., -- refer to Fig. 4 for Delay Tracking circuit example, p.0061 recites “In the delay tracking circuits described above are configured as a delay time to digital number, or time-to-digital, conversion circuit.”].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4 - 6, 11 - 13 and 19 - 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Holzmann (US Pub. No. 2017/0163152 A1) in view of Ihs et al (US Pub. No. 2016/0049871 A1); (hereinafter Holzmann and Ihs et al).
Regarding claim 4, Holzmann discloses the claimed invention except for a second feedback generation unit to generate a second feedback signal based on a comparison between a supply voltage of the one or more digital circuits and a reference voltage.
Ihs et al [e.g., Figs. 1 - 4] teaches a second feedback generation unit [e.g., comparator 429b] to generate a second feedback signal based on a comparison between a supply voltage of the one or more digital circuits and a reference voltage [e.g., generates second feedback signal based on comparison between Vout and Vref generated by Reference Generator 427].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Holzmann with a second feedback generation unit to generate a second feedback signal based on a comparison between a supply voltage of the one or more digital circuits and a reference voltage as suggested by Ihs et al for voltage regulation using multiple adjustable voltage reference levels based on process and/or temperature variations and conditions.
Regarding claim 5, Holzmann discloses the claimed invention except for upon startup of the digital circuits, the power regulator unit is configured to adjust the power delivery to the one or more digital circuits based on the second feedback signal.
Ihs et al [e.g., Figs. 1 - 4] teaches upon startup of the digital circuits [e.g., -- refer to Fig. 2 for a flow diagram of a process for power regulation --, START], the power regulator unit is configured to adjust the power delivery to the one or more digital circuits based on the second feedback signal [e.g., controls voltage regulator based on feedback signals generated by comparators 429a and 429b].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Holzmann with upon startup of the digital circuits, the power regulator unit is configured to adjust the power delivery to the one or more digital circuits based on the second feedback signal as suggested by Ihs et al for voltage regulation using multiple adjustable voltage reference levels based on process and/or temperature variations and conditions.
Regarding claim 6, Holzmann discloses the claimed invention except to adjust the power delivery to the one or more digital circuits based on the second feedback signal by increasing the power delivery to the one or more digital circuits until the current supply voltage of the one or more digital circuits reaches a predetermined fraction of the reference voltage.
Ihs et al [e.g., Figs. 1 - 4] teaches to adjust the power delivery to the one or more digital circuits based on the second feedback signal [e.g., adjust voltage regulator based on signal generated by comparison circuits 429a and 429b] by increasing the power delivery to the one or more digital circuits until the current supply voltage of the one or more digital circuits reaches a predetermined fraction of the reference voltage [e.g., -- FIG. 3 is a further flow diagram of a process in accordance with aspects of the invention--, increases switching until output voltage reaches Vref or a scaled version of Vref p. 0019 recites “Operation of the voltage regulator depend on comparisons of Vout with one or more reference voltages, which for convenience shall simply be termed Vref, unless the context indicates otherwise. In the system of FIG. 1, the comparators for making the comparisons are provided in a comparator block 117. Outputs of the comparator block are provided to the voltage regulators (without such connections shown in FIG. 1 for clarity of the figure). In some embodiments the comparators include a plurality of comparators, each of which compares Vout to Vref or a scaled version of Vref. In some embodiments the voltage comparators are common to control of all phases of a power domain.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Holzmann with wherein the power regulator unit is configured to adjust the power delivery to the one or more digital circuits based on the second feedback signal by increasing the power delivery to the one or more digital circuits until the current supply voltage of the one or more digital circuits reaches a predetermined fraction of the reference voltage as suggested by Ihs et al for voltage regulation using multiple adjustable voltage reference levels based on process and/or temperature variations and conditions.
Regarding claim 11, Holzmann discloses the claimed invention except for generating a second feedback signal based on a comparison between a current supply voltage of the one or more digital circuits and a reference voltage.
Ihs et al [e.g., Figs. 1 - 4] teaches generating a second feedback signal based on a comparison between a current supply voltage of the one or more digital circuits and a reference voltage [e.g., comparator 429b generates second feedback signal based on comparison between Vout and Vref generated by Reference Generator 427].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Holzmann with generating a second feedback signal based on a comparison between a current supply voltage of the one or more digital circuits and a reference voltage as suggested by Ihs et al for voltage regulation using multiple adjustable voltage reference levels based on process and/or temperature variations and conditions.
Regarding claim 12, Holzmann discloses the claimed invention except for upon startup of the one or more digital circuits, adjusting the power delivery to the one or more digital circuits based on the second feedback signal.
Ihs et al [e.g., Figs. 1 - 4] teaches upon startup of the one or more digital circuits [e.g., -- refer to Fig. 2 for a flow diagram of a process for power regulation --, START], adjusting the power delivery to the one or more digital circuits based on the second feedback signal [e.g., controls voltage regulator based on feedback signals generated by comparators 429a and 429b].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Holzmann with upon startup of the one or more digital circuits, adjusting the power delivery to the one or more digital circuits based on the second feedback signal as suggested by Ihs et al for voltage regulation using multiple adjustable voltage reference levels based on process and/or temperature variations and conditions.
Regarding claim 13, Holzmann discloses the claimed invention except for wherein the power delivery to the one or more digital circuits is adjusted based on the second feedback signal by increasing the power delivery to the digital circuits until the current supply voltage of the one or more digital circuits reaches a predetermined fraction of the reference voltage.
Ihs et al [e.g., Figs. 1 - 4] teaches wherein the power delivery to the one or more digital circuits is adjusted based on the second feedback signal [e.g., adjust voltage regulator based on signal generated by comparison circuits 429a and 429b] by increasing the power delivery to the digital circuits until the current supply voltage of the one or more digital circuits reaches a predetermined fraction of the reference voltage [e.g., -- FIG. 3 is a further flow diagram of a process in accordance with aspects of the invention--, increases switching until output voltage reaches Vref or a scaled version of Vref p. 0019 recites “Operation of the voltage regulator depend on comparisons of Vout with one or more reference voltages, which for convenience shall simply be termed Vref, unless the context indicates otherwise. In the system of FIG. 1, the comparators for making the comparisons are provided in a comparator block 117. Outputs of the comparator block are provided to the voltage regulators (without such connections shown in FIG. 1 for clarity of the figure). In some embodiments the comparators include a plurality of comparators, each of which compares Vout to Vref or a scaled version of Vref. In some embodiments the voltage comparators are common to control of all phases of a power domain.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Holzmann with wherein the power delivery to the one or more digital circuits is adjusted based on the second feedback signal by increasing the power delivery to the digital circuits until the current supply voltage of the one or more digital circuits reaches a predetermined fraction of the reference voltage as suggested by Ihs et al for voltage regulation using multiple adjustable voltage reference levels based on process and/or temperature variations and conditions.
Regarding claim 19, Holzmann discloses the claimed invention except for a second feedback generation unit to generate a second feedback signal based on a comparison between a current supply voltage of the digital circuits and a reference voltage.
Ihs et al [e.g., Figs. 1 - 4] teaches a second feedback generation unit [e.g., comparator 429b] to generate a second feedback signal based on a comparison between a current supply voltage of the digital circuits and a reference voltage [e.g., generates signal based on comparison between Vout and Vref generated by reference generator 427].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Holzmann with a second feedback generation unit to generate a second feedback signal based on a comparison between a current supply voltage of the digital circuits and a reference voltage as suggested by Ihs et al for voltage regulation using multiple adjustable voltage reference levels based on process and/or temperature variations and conditions.
Regarding claim 20, Holzmann discloses the claimed invention except for the second feedback generation unit is a digital comparator, an analogue-to-digital converter, one or more pairs of ring oscillators, or a combination thereof.
Ihs et al [e.g., Figs. 1 - 4] teaches the second feedback generation unit is a digital comparator, an analogue-to-digital converter, one or more pairs of ring oscillators, or a combination thereof [e.g., p. 0036 recites “The controller also receives results of comparisons of the output voltage with reference voltages. The comparisons are performed by comparators 429a-b, in the example system of FIG. 4. The controller utilizes the results of the comparisons in determining states of the high side, low side, and bypass switches.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Holzmann with the second feedback generation unit is a digital comparator, an analogue-to-digital converter, one or more pairs of ring oscillators, or a combination thereof as suggested by Ihs et al for voltage regulation using multiple adjustable voltage reference levels based on process and/or temperature variations and conditions.
Claim(s) 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Holzmann (US Pub. No. 2017/0163152 A1) in view of Ihs et al (US Pub. No. 2016/0049871 A1) and Bennett (US Patent No. 8,390,367 B1); (hereinafter Holzmann, Ihs et al and Bennett).
Regarding claim 7, Holzmann discloses the claimed invention except for upon the current supply voltage reaching the predetermined fraction of the reference voltage, the power regulator unit is configured to switch from the second feedback signal to the first feedback signal.
Bennett [e.g., Figs. 2 - 4] teaches upon the current supply voltage reaching the predetermined fraction of the reference voltage [e.g., -- refer to Fig. 4 --, tether voltage established by ratio of the lengths oscillator circuits (46) and reference oscillator (42) col. 2 lines 58 - 67 recites and col. 3 lines 1 - 5“…, the reference oscillator 42 and the startup oscillator 46 are configured so that the supply voltage 28 is less than the reference voltage 48 during the startup interval, thereby tethering the supply voltage 28 to the reference voltage 48 by a tether voltage. Any suitable technique may be employed to implement the tether voltage, wherein in an embodiment shown in FIG. 4, a length of the startup oscillator 46 is shorter than a length of the reference oscillator 42 which ensures the supply voltage 28 is less than the reference voltage 48 by a tether voltage determined by a ratio of the lengths. That is, because the length of the startup oscillator 46 is shorter than the reference oscillator 42, it requires a lower supply voltage to match the oscillation frequency 50 output by the startup oscillator 42 to the reference frequency 44 output by the reference oscillator 42.”], the power regulator unit is configured to switch from the second feedback signal to the first feedback signal [e.g., switches between signal 54 and signal 40, col. 2 lines 33 - 44 recites “…, during a startup interval of the computing device the second error signal 54 generated by comparing the output of the startup oscillator 46 to the output of the reference oscillator 42 is used to adjust the supply voltage 28 which allows the frequency synthesizer 30 to stabilize while ensuring a minimum gate speed for the digital circuitry 26. Accordingly, a multiplexer 58 selects the second error signal 54 during the startup interval, and selects the first error signal 40 at the end of the startup interval. Any suitable technique may be employed to generate the reference voltage 48 applied to the reference oscillator 42, such as with a low power analog voltage regulator.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Holzmann with upon the current supply voltage reaching the predetermined fraction of the reference voltage, the power regulator unit is configured to switch from the second feedback signal to the first feedback signal as suggested by Bennett for regulating power consumption of digital circuitry to help increase the life of battery power.
Regarding claim 14, Holzmann discloses the claimed invention except for upon the current supply voltage reaching the predetermined fraction of the reference voltage, switching from the second feedback signal to the first feedback signal.”
Bennett [e.g., Figs. 2 - 4] teaches upon the current supply voltage reaching the predetermined fraction of the reference voltage [e.g., -- refer to Fig. 4 --, tether voltage established by ratio of the lengths oscillator circuits (46) and reference oscillator (42) col. 2 lines 58 - 67 recites and col. 3 lines 1 - 5“…, the reference oscillator 42 and the startup oscillator 46 are configured so that the supply voltage 28 is less than the reference voltage 48 during the startup interval, thereby tethering the supply voltage 28 to the reference voltage 48 by a tether voltage. Any suitable technique may be employed to implement the tether voltage, wherein in an embodiment shown in FIG. 4, a length of the startup oscillator 46 is shorter than a length of the reference oscillator 42 which ensures the supply voltage 28 is less than the reference voltage 48 by a tether voltage determined by a ratio of the lengths. That is, because the length of the startup oscillator 46 is shorter than the reference oscillator 42, it requires a lower supply voltage to match the oscillation frequency 50 output by the startup oscillator 42 to the reference frequency 44 output by the reference oscillator 42.”], switching from the second feedback signal to the first feedback signal [e.g., switches between signal 54 and signal 40, col. 2 lines 33 - 44 recites “…, during a startup interval of the computing device the second error signal 54 generated by comparing the output of the startup oscillator 46 to the output of the reference oscillator 42 is used to adjust the supply voltage 28 which allows the frequency synthesizer 30 to stabilize while ensuring a minimum gate speed for the digital circuitry 26. Accordingly, a multiplexer 58 selects the second error signal 54 during the startup interval, and selects the first error signal 40 at the end of the startup interval. Any suitable technique may be employed to generate the reference voltage 48 applied to the reference oscillator 42, such as with a low power analog voltage regulator.”]..
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Holzmann with upon the current supply voltage reaching the predetermined fraction of the reference voltage, switching from the second feedback signal to the first feedback signal as suggested by Bennett for regulating power consumption of digital circuitry to help increase the life of battery power.
Examiner’s Note
10. Examiner has cited particular columns, paragraphs and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figure may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art disclosed by the Examiner.
11. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention
Conclusion
12. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US Pub. No. 2023/0396163 A1 (Wei et al) discloses a feedback control circuit adaptively adjusts a peak inductor current value according to a pulse interval and an associated feedback control method.
US Patent No. 10,027,221 Ba (Cao) discloses a buck switching regulator with a second feedback signal.
US Pub. No. 2026/0106545 A1 (Tu et al) discloses a switching power circuit configured to generate a first output voltage on a first power rail and a second output voltage on a second power rail by controlling on and off of a controllable switch.
13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ULARISLAO CORDOVA whose telephone number is (571)272-4690. The examiner can normally be reached Monday-Friday 7:30 - 5:00 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/ULARISLAO CORDOVA/Examiner, Art Unit 2838
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