DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a response to the amendment filed 7/31/2026. Claims 1-20 are pending and are under examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 8, 14, 16-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Felix et al. (US 2021/0191488).
Regarding claims 1 and 17, Felix et al.’s figure 2 shows a circuitry (20) for controlling a clock throttle circuit (21 which throttle between a first clock signal or a second clock signal which has portions of clock pulses of the first clock signal removed, thus, construes to be a clock throttle circuit), the circuitry comprising: a first component (20) to: receive a target index corresponding to a target level of throttle for a clock output signal at the clock throttle circuit (droop detector provides an indication, i.e., target index, to the stop and ramp logic requires portion of clock pulses needs to be removed); determine a current index implemented at the clock throttle circuit (stop and ramp logic determines how many clock pulses, i.e., current index, need to be removed), where the current index corresponds to a current level of throttle of the clock output signal (numbers of removed clock pulses); provide, responsive to the determination, an index signal (updated value of N; paragraphs 0047-0048) to cause the clock throttle circuit to throttle the clock output signal in accordance with the index signal as called for in claims 1 and 17.
Regarding claim 2, where the target level of throttle is less than the current level of throttle (portion of clock pulse removed because less than the original clock pulses; figure 4).
Regarding claim 3, where index signal is to cause the clock throttle circuit to decrease the current level of throttle to the target level over one or more levels (the updated value of N cause the frequency of the second clock decreases further; see paragraph 0047-0048).
Regarding claim 4, where the target level of throttle is greater than the current level of throttle (the frequency of the first clock is greater than the frequency of the second clock).
Regarding claim 5, where index signal is to cause the clock throttle circuit to increase the current level of throttle to the target level (changing updated value N causes an increase in frequency of the second clock; paragraphs 0045-0046).
Regarding claim 8, where the first component (13; figure 5) comprises a first state machine (55).
Regarding claim 14, the first component (13; figure 5) comprises a second state machine (56).
Regarding claim 16, where the clock output signal is provided to a subsystem (2; figure 2).
Regarding claim 18, the circuitry of claim 1, implemented in at least one packaged chip (figure 1); at least one system component; and a board, wherein the at least one packaged chip and the at least one system component are assembled on the board (figure 1).
Regarding claim 19, A chip-containing product comprises the system of claim 18 assembled on a further board with at least one other product component (host 8; figure 1).
Regarding claim 20, A non-transitory computer-readable medium is capable of storing computer-readable code for fabrication of the circuitry of claim 1
Response to Arguments
Applicant's arguments filed 7/31/2026 have been fully considered but they are not persuasive. Applicant argues that Felix et al.’s droop detection output is not a target index. Applicant further stated that the "target index" of claim 1 represents a specific target throttle level or target pattern identifier. However, such limitation is not presented in claim 1. Furthermore, under a broadest interpretation, Examiner construes “a target index corresponding to a target level of throttle for a clock output signal at the clock throttle circuit” as a signal/indication corresponding to levels of an output clock signal being removed. In this instant, Felix et al.’s output signal from the droop detection signifies the stop and ramp logic (20) to remove a portion of clock pulses (see figure 4). Thus, the limitation of “a target index corresponding to a target level of throttle for a clock output signal at the clock throttle circuit” is met.
Applicant also argues that Felix et al.’s output signal from the droop detector is “A transient, physical measurement of voltage droop magnitude is a dynamic physical error value, not a target index corresponding to a target level of throttle." In fact, Felix is completely silent regarding any "target index.” Also found not persuasive. As noted above, under a broadest interpretation, Examiner construes “a target index corresponding to a target level of throttle for a clock output signal at the clock throttle circuit” as a signal/indication corresponding to levels of an output clock signal being removed. In this instant, Felix et al.’s output signal from the droop detection signifies the stop and ramp logic (20) to remove a portion of clock pulses (see figure 4). Thus, the limitation of “a target index corresponding to a target level of throttle for a clock output signal at the clock throttle circuit” is met.
Applicant argues that claim 1 further requires to "determine a current index implemented at the clock throttle circuit, where the current index corresponds to a current level of throttle of the clock output signal.", for example, using internal control signals (e.g., a closed-loop feedback mechanism) to know what the throttle circuit is actively doing (see e.g., feedback from the clock throttler circuit 11 to the index state machine 2A in the application was filed, paragraph [0035]). However, such closed loop feedback mechanism is not found in claim 1.
Applicant argues that Felix et al. fails to disclose to "provide, responsive to the determination, an index signal to cause the clock throttle circuit to throttle the clock output signal in accordance with the index signal." as required by claim 1 found not persuasive. The index signal corresponds to the updated value of N as disclosed in paragraphs 0047 and 0048. The updated value N causes the clock throttle circuit to remove clock pulses/to throttle the output clock signal (figure 4). The rejection is deemed proper, thus, claims 1-5, 8, 14, 16-20 remain rejected.
Allowable Subject Matter
Claims 6-7 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 9-13, 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Felix et al. reference fails to teach or fairly suggest where the index signal corresponds to a pattern of bits to be applied at the clock throttler circuitry, where: a bit having a first value is, when applied, to pass a pulse of a clock input signal as the clock output signal; a bit having a second value is, when applied, to gate a pulse of a clock input signal as the clock output signal as called for in claim 6; a second component, where the second component comprises one or more index target generator circuits, each index target generator circuit to generate an intermediate target index for a respective event as called for in claim 9.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. USP 6,304,978 discloses a power management circuit (160) monitors current use by a processor (105) via a current sensor. The power management circuit can then throttle the processor by gating a stop clock signal (115) during operation. This slows operation of the processor and prevents signals from being retired from, or new signals entering, the processor pipeline (106).
USP 5,586,332 discloses a clock throttling mechanism that turns off certain processor components to minimize power consumption. The processor detects the issuance of certain bus cycles or the execution of certain instructions which typically cause the processor to be idle for a period of time. Control circuitry detects the existence of the instruction and/or bus cycle and shuts down the clock driving certain processor components during that idle period. The control circuitry then detects the occurrence or upcoming occurrence of an event to which the processor responds and becomes active. At detection of this event, the clock signal input to these components is then restarted such that the processor can continue normal execution.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TUAN T LAM/ Primary Examiner, Art Unit 2836 9/14/2026
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