DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings were received on 7/28/26. These drawings are accepted.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but is moot in light on the amended features.
As for the argument that multiplexer is physically configured to select between different active oscillation clocks and frequency divider and does not select a first pattern. Please note the claim requires selecting a first pattern by a selection circuitry. The claim does not require the patterns are inputs of the multiplexers.
Note the invention of Pal is directed to dynamic frequency scaling to dynamically change the clock frequency of a processor based on use cases while mitigate power distribution network (PDN) droop/overshoot mitigation [background, abstract and par. 28]. Pal teaches in that a m multiplexer 120 electively provide to the processor under the under the control of controller 115 based on a plurality of inputs and selected frequencies. As notes, the entire premise of system of Pal is to mitigate droop/overshoot mitigation by ramping up a frequency of a clock signal to a processor when the processor is switching clock frequencies and/or the processor is transitioning from an idle mode to an active mode. As shown in Fig. 1A and discussed by Paul [at least par. 30-34 and 54-54], the clock circuit 140 comprises a multiplexer 120 configured to receive a plurality of input clock signals and input from voltage divider to selectively output one of the input clock signals to the processor 110 under the control of controller 115. The frequency of the clock signal can be adjusted by adjusting the divisor N of the frequency divider which dictates the amount of ramping up or down for the frequency meets the set desired frequency which correlates to the ramp down sequence stored in the table of memory of controller 115 [ par. 74]. Thus as seen, the multiplexer along with the controller serve to select the appropriate pattern used by the ramp circuit or swallower.
The ramp circuit or swallow circuit simply uses the input from the sequentially walk through the bits to produce the output frequency under the under the control of controller 115. However, the selection of the pattern/amount of ramping is done by the setting of the frequency divisor [par. 73].
Claim Interpretation
Claims 1 and 18 recites the limitation “each pattern of the plurality of patterns comprises a plurality of bits defining clock-pulse- pass commands and clock-pulse-gate commands” (emphasis added).
The specification does not provide for the such language. There is only a single recitation of “command” found in the specification [par. 94] where it states “ a user can interrupt a sequence and cause the clock throttler circuitry to select a new pattern before the current completes by issuing a command signal (e.g. a flush throttler signal).”
The citations in the specification [par. 74] that appears to be relevant to the claim language states:
Each bit of the respective patterns in the table of FIG. 4 has a value of 1 or 0, where when a bit having a value 1 is provided to an ICG and applied thereat, the ICG will pass a pulse of a clock signal (e.g. the clock input signal (clkin) depicted in FIG. 2a) and when a bit having a value 0 is provided to an ICG and applied thereat, the ICG will gate a pulse of a clock signal (e.g. the clock input signal (clkin) depicted in FIG. 2a), thereby throttling an effective frequency of the clock output signal”.
Thus the rejection will treat that the value 0 and 1 are being applied to either pass or delete a pulse based on the teaching of the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-18 are rejected under 35 U.S.C. 102 (a)(2) as being anticipated by Pal, 20170038789 A1
Regarding claim 1. Pal teaches a clock throttler circuitry for generating a clock signa [Fig. l-15, par. 6-8] the circuitry comprising:
first selection circuitry to select a first pattern of a plurality of patterns in storage, where each pattern of the plurality of patterns comprises a plurality of bits defining clock-pulse-pass commands and clock-pulse-gate commands [Fig. 1-7, and 11, par. 30-34, the clock controller 115 may switch input clock signals and dynamically change the clock frequency of processor 110 based on the needs of the processor 110; Mux selects a clock signal with outputs the selected clock signal and a selectable clock frequency under the control of the clock controller 115. Par. 67 and 74, controller 115 may include a table in memory comprises a ramp down sequence for each input clock signals; PIDs identify pulse swallow patterns to be used by the clock swallower 610 to ramp down the frequency of the output clock signal; the clock swallower 610. Each pulse swallow pattern is defined by a sequence of eight bits, in which a bit value of zero corresponds to a pulse swallow (i.e. pulse gate command) and a bit value of one corresponds to a pulse pass (pulse pass command)]
second selection circuitry to sequentially select bits of the first pattern and to provide the selected bits to clock gate circuitry [clock swallower 610/ramp circuit 410] in a successive manner [Fig.5-11, par. 66, 70; the clock swallower 610 may use different ramp up sequences depending on the frequency of the input clock signal providing (sourcing) the output clock signal. The controller 115 may instruct the clock swallower 610 to swallow pulses of the selected clock signal Clk_sel according to a particular pulse swallow pattern by inputting the corresponding PID to the clock swallower 610]
where the clock gate circuitry [clock swallower 610/ramp circuit 410] is to receive a clock input signal [Clk Sel] and to pass or gate pulses of the clock input signal responsive to applying the selected bits to generate a clock output signal [CLk out] par. 67, 96-102, clock gate circuit 1115 gates the input clock according to the pulse swallow clock pattern via frequency ramp circuit to provide clock signal to processor 110. Each pulse swallow pattern is defined by a sequence of eight bits, in which a bit value of zero corresponds to a pulse swallow and a bit value of one corresponds to a pulse pass.]
Claim 2. Pal teaches the circuitry of claim 1, further comprising a state machine circuitry to generate a sequence of bit selection signals, each bit selection signal comprising a configured to identify an individual bit of the first pattern [Fig. 7-11, par. 53-54, 67 and 70, the controller 115 (may be a state machine, par. 140) may instruct the clock swallower 610 to swallow pulses according to a particular pulse swallow pattern by inputting the corresponding PID to the clock swallower 610; each pulse swallow pattern is identified by a unique pattern ID, PID].
Claim 3. Pal teaches the circuitry of claim 2, where the state machine circuitry is to generate a bit selection signal of the sequence every one or more clock cycles [Fig. 8, par. 67, each pulse swallow pattern is defined by a sequence of eight bits each correspond to a clock cycle]
Claim 4. Pal teaches the circuitry of claim 3, where the second selection circuitry is to select a bit corresponding to each bit selection signal [ Fig. 9- 10 and par. 54 and 70, clock swallower 610 to swallow pulses of the selected clock signal based on the pulse swallow pattern identified by the PID].
Claim 5. Pal teaches the circuitry of claim 1, further comprising first storage to store the selected first pattern [ par. 134, FIG. 15 shows an example of a system 1500 in which the clock circuit 1550 comprises a PLL 1540 with selectable clock frequencies]
Claim 6. Pal teaches the circuitry of claim 5, further comprising second storage to obtain the selected first pattern responsive to an enable signal from the state machine circuitry [par. 74, the controller 115 may include a table in memory, in which the table comprises a ramp down sequence for each input clock signal]
Claim 7. Pal teaches the circuitry of claim 6, where the state machine circuitry is to assert the enable signal and generate a final bit selection signal of the sequence in the same clock cycle. [par. 133; when the output clock signal is enabled with the new input clock signal, the clock controller 115 may ramp up the output clock signal to the swallow pattern corresponding to the end PID].
Claim 8. Pal teaches the circuitry of claim 1, where each pattern of the plurality of patterns comprises “n” bits, each bit having a first value or a second value [ Fig. 8, par. 67, each pulse swallow pattern is defined by a sequence of eight bits of either 1 or zero]
Claim 9. The circuitry of claim 8, where the clock gate circuitry is to pass a pulse of the clock input signal (clkin) responsive to applying a bit having the first value and to gate a pulse of the clock input signal responsive to applying a bit having the second value [par. 67-68 a bit value of zero corresponds to a pulse swallow and a bit value of one corresponds to a pulse pass; par. 54 and 70, clock swallower 610 to swallow pulses of the selected clock signal based on the pulse swallow pattern identified by the PID].
Claim 10. The circuitry of claim 8, where each pattern of the plurality of patterns has a different number of bits having the first value [Fig. 8, par. 66-70 swallow patterns of 1 and 0 are unique for each pattern PID] .
Claim 11. The circuitry of clam 8, where applying the plurality of bits of the first selected pattern at the clock gate circuitry is to control an effective frequency of the clock output signal [Fig. 8, par. 66-70 swallow pattern are different based on the desired changed values applied to the gating circuit to change the frequency of the output clock] .
Claim 12. The circuitry of claim 1, where each pattern of the plurality of patterns has an associated pattern identifier [Fig. 8-9, clock a-d and PID].
Claim 13. Pal teaches the circuitry of claim 12, where the first selection circuitry is to select the first pattern responsive to an identifier signal comprising a pattern identifier for the first pattern [Fig. 8-9, PID and associated clock a-d for ramping function].
Claim 14. Pal teaches the circuitry of claim 1, where the selected bits of the first pattern are successively applied at the clock gate circuitry to generate the clock output signal [Fig. 11, par. par. 67, 96-102, each pulse swallow pattern is defined by a sequence of eight bits, in which a bit value of zero corresponds to a pulse swallow and a bit value of one corresponds to a pulse pass]
Claim 15. Pal teaches the circuitry of claim 1, where the first selection circuitry is to select a second pattern responsive to an identifier for the second pattern [ par. 7, frequency switching selects a second clock signal] and perform the same operations on the newly selected signal as discussed in claim 1 [see also par. 82-85]
Claim 16. The control circuitry of claim 1, comprising bypass circuitry to, when enabled, bypass the first and second selection circuitry [ Par. 104 and 10, the power manager 1110 may place the processor 110 in the idle mode to conserve power when the processing is finished, triggers the clock controller 115 to instruct the multiplexer 120 to disable the selected clock signal and unselecting all of the input clock signals i.e. bypass the selection circuit].
Claim 17. The control circuitry of claim 1, further comprising synchronisation circuitry to synchronise one or more external signals to a clock input domain [par. 38-43, the control logic 215 may output a select signal for a selected one of the inputs clock signals and output unselect signals]]
Claim 18. Pal teaches the apparatus for performing all the steps corresponding to the operation described in claim 1 and therefore rejected accordingly.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 19 and 20 ais/are rejected under 35 U.S.C. 103 as being unpatentable over Pal.
Claim 19-20, Pal teaches a system comprising: the circuitry of claim 1 and can be implemented with various combination [par. 29, 140-141, the clock controller may be implemented with a general-purpose processor among others including discrete hardware components, or any combination thereof] but does not specify that implemented in at least one packaged chip; at least one system component; and a board, wherein the at least one packaged chip and the at least one system component are assembled on the board. However, give the state of the art and the teaching of Pal regarding the implementation of integrated circuits and components [ par. 29 and 140-141], it would have been obvious to one having ordinary skill in the art before the effective filing date to implement the system of Pal as integrated circuits to take advantage of the compact size, high reliability, low cost, energy efficiency, and enhanced performance which is essential in modern electronics.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KIM HUYNH/Primary Patent Examiner, Art Unit 2176
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