Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
3. Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
4. The information disclosure statement (IDS) submitted on 12/16/2024 and 11/20/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
5. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: DC-to-DC power converter with progressive soft-start control.
Claim Objections
6. Claim 16 are objected to because of the following informalities:
Claim 16 lines 1 - 2 recites “…, a turn-on duration of a third switch and a turn-on duration of a fourth switch in a second bridge circuit of the synchronous rectification circuit”.
However, it appears that it should recite “…, a turn-on duration of a third switch and a turn-on duration of a fourth switch in the second bridge circuit of the synchronous rectification circuit”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
8. Claim(s) 1- 3, 6 - 8, 11 - 13, 15 - 16 and 18 - 20 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Karlsson et al (WO 2017/168220 A1); (hereinafter Karlsson et al).
Regarding claim 1, Karlsson et al [e.g., Figs. 5 - 6 and 11 - 16] discloses a direct current to direct current conversion (DCDC) circuit [e.g., -- refer to Fig. 11 --, Power converter], comprising: a transformer circuit [e.g., Q1 - Q4 and transformer TR], a synchronous rectification circuit [e.g., Q5 - Q8], and a control circuit [e.g., Controller 1110]; wherein the control circuit is configured to: control a turn-on duration of a first switch [e.g., -- refer to Fig. 14 for timing diagram --, controls turn on duration of Q1 (1410)] and a turn-on duration of a second switch [e.g., controls turn on duration of Q3] in a first bridge circuit of the transformer circuit [e.g., Q1 and Q3 part of a first bridge of the transformer circuit] to increase progressively every switching cycle until an output voltage of the transformer circuit is greater than a first target voltage [e.g.,. -- refer to Figs. 5 and 6 --, increases cycle progressively until output voltage of transformer charges boot-strap capacitor CB2 during start-up period, p.0042 recites “The first energy transfer and transformer balancing pulse (a short control pulse) is improved by discharging parasitic capacitances of the first and second low-side switching devices Q3, Q4 of the power train, and charging the first and second bias voltage boot-strap capacitors CBI, CB2 for the first and second high-side switching devices Q l, Q2, respectively.”]; wherein a first initial turn-on duration of the first switch corresponding to a first switching cycle [e.g., turn on duration of Q1 (1410) during first switching cycle] is different from a second initial turn-on duration of the second switch corresponding to the first switching cycle [e.g., different turn-on than Q3 during first switching cycle]; and control a turn-on duration of a third switch [e.g., turn-on duration of Q5] and a turn-on duration of a fourth switch [e.g., turn on duration of Q7] in a second bridge circuit of the synchronous rectification circuit [e.g., Q5 and Q7 forming second bridge of rectifier] to increase progressively every switching cycle until an output voltage of the synchronous rectification circuit is greater than a second target voltage [e.g.,. -- refer to Figs. 12 and 13 --, increases cycle progressively until output voltage of transformer charges boot-strap capacitor CBS on node Vd during start-up period, p.0062 recites “Additionally, a short control pulse 1420 is applied to briefly turn on (and then turn off) and discharge the parasitic capacitance of the fourth low-side switching device Q8 of the synchronous rectifier. The short control pulse 1420 is also applied to the third high-side switching device Q5. The short control pulse 1420 is sufficiently short in duration to prevent (via circuit inductance) a damaging current from flowing within the power converter. A bias voltage boot-strap capacitor CBS is also charged for the fourth high-side switching device Q6 (see, e.g., FIGURE 13). Again, the duration of the short control pulses 1410, 1420 may be varied depending on the application.”] wherein a third initial turn-on duration of the third switch corresponding to the first switching cycle [e.g., turn-on duration of Q5 correspond to first witching cycle] is different from a fourth initial turn-on duration of the fourth switch corresponding to the first switching cycle [e.g., different from turn-on duration of Q7 corresponding to first switching cycle].
Regarding claim 2, Karlsson et al [e.g., Figs. 5 - 6 and 11 - 16] discloses [e.g., full bridge Q1 - Q4], and the first switch comprises two switches located at a first bridge arm of the first bridge circuit [e.g., Q1 and Q3]; the second switch comprises two switches located at a second bridge arm of the first bridge circuit [e.g., Q2 and Q4]; and the first switch is connected to a voltage input terminal of the DCDC circuit [e.g., Q1 connected to VIN]; and the first initial turn-on duration of the first switch is less than the second initial turn-on duration of the second switch [e.g., -- refer to Fig. 14 for timing diagram --, turn-on duration of Q1 (1410) is less than turn-on duration of Q3 (D/2)]; or wherein the first bridge circuit is a full-bridge circuit [e.g., full bridge Q1 - Q4].
Regarding claim 3, Karlsson et al [e.g., Figs. 5 - 6 and 11 - 16] discloses wherein the control circuit [e.g., controller 1110] is configured to: control a pulse width of a driving signal of the first switch [e.g., signal G1 generated by Controller 1110] and a pulse width of a driving signal of the second switch [e.g., signal G2 generated by Controller 1110] to increase progressively every switching cycle [e.g., -- refer to Fig. 14 for timing diagram --, increases all switching cycle progressively]; and wherein a first initial pulse width of the driving signal of the first switch corresponding to the first switching cycle is different from a second initial pulse width of the driving signal of the second switch corresponding to the first switching cycle [e.g., initial PWM (1410) for Q1 different than second initial pulse width of driving signal Q2 during the first cycle].
Regarding claim 6, Karlsson et al [e.g., Figs. 5 - 6 and 11 - 16] discloses wherein the control circuit [e.g., controller 1110] is configured to: control the pulse width of the driving signal of the first switch [e.g., control pulse width of driving signal G1 for Q1] and the pulse width of the driving signal of the second switch [e.g., pulse width of driving signal G1 for Q2] to increase progressively along a direction every switching cycle [e.g., -- refer to Fig. 14 for timing diagram --, increases progressive the duty cycle of driving signals along as a function of time];
Regarding claim 7, Karlsson et al [e.g., Figs. 5 - 6 and 11 - 16] discloses wherein the second bridge circuit is a full-bridge circuit [e.g., Q5 - Q8], and the third switch comprises two switches located at a third bridge arm of the second bridge circuit [e.g., Q5 and Q7 forming third bridge]; the fourth switch comprises two switches located at a fourth bridge arm of the second bridge circuit [e.g., Q6 and Q8]; and the third switch is connected to a voltage output terminal of the DCDC circuit [e.g., bridge containing Q5 and Q7 connected to VOUT]; and a third initial turn-on duration of the third switch is less than a fourth initial turn-on duration of the fourth switch [e.g., -- refer to Fig. 14 for timing diagram --, initial turn on duration of Q5 is less than initial turn-on duration of Q7].
Regarding claim 8, Karlsson et al [e.g., Figs. 5 - 6 and 11 - 16] discloses wherein the control circuit [e.g., controller 1110] is configured to: control a pulse width of a driving signal of the third switch [e.g., controls Q5 via G5] and a pulse width of a driving signal of the fourth switch [e.g., controls Q7 via G7] to increase progressively every switching cycle [e.g., -- refer to Fig. 14 for timing diagram --, increases progressive the duty cycle of driving signals along as a function of time]; and wherein a third initial pulse width of the driving signal of the third switch corresponding to the first switching cycle [e.g., driving signal of Q5 (1420) during first switching cycle] is different from a fourth initial pulse width of the driving signal of the fourth switch corresponding to the first switching cycle [e.g., different from driving signal of Q7 during the first switching cycle].
Regarding claim 11, Karlsson et al [e.g., Figs. 5 - 6 and 11 - 16] discloses wherein the control circuit is configured to: control the pulse width of the driving signal of the third switch [e.g., controller 1110 controls Q5 via G5] and the pulse width of the driving signal of the fourth switch [e.g., controls Q7 via G7] to increase progressively along a direction every switching cycle [e.g., -- refer to Fig. 14 for timing diagram --, increase progressively in the time direction];
Regarding claim 12, Karlsson et al [e.g., Figs. 5 - 6 and 11 - 16] discloses a circuit start-up method [e.g., start-up method of power converter], applied to a direct current to direct current conversion (DCDC) circuit [e.g., -- refer to Fig. 11 --, Power converter], the DCDC circuit comprising a transformer circuit [e.g., transformer TR], a synchronous rectification circuit [e.g., Q5 - Q8], and a control circuit [e.g., controller 1110], the method comprising: controlling, by the control circuit, a turn-on duration of a first switch [e.g., -- refer to Fig. 14 for timing diagram --, controls turn on duration of Q1 (1410)] and a turn-on duration of a second switch in a first bridge circuit of the transformer circuit [e.g., controls turn on duration of Q3] to increase progressively every switching cycle until an output voltage of the transformer circuit is greater than a first target voltage [e.g., -- refer to Figs. 5 and 6 --, increases cycle progressively until output voltage of transformer charges boot-strap capacitor CB2 during start-up period, p.0042 recites “The first energy transfer and transformer balancing pulse (a short control pulse) is improved by discharging parasitic capacitances of the first and second low-side switching devices Q3, Q4 of the power train, and charging the first and second bias voltage boot-strap capacitors CBI, CB2 for the first and second high-side switching devices Q l, Q2, respectively.”]; wherein a first initial turn-on duration of the first switch [e.g., turn on duration of Q1 (1410)] corresponding to a first switching cycle [e.g., first switching cycle] is different from a second initial turn-on duration of the second switch [e.g., different turn-on than Q3] corresponding to the first switching cycle [e.g., during first switching cycle]; and controlling, by the control circuit, a turn-on duration of a third switch [e.g., turn-on duration of Q5] and a turn-on duration of a fourth switch in a second bridge circuit of the synchronous rectification circuit [e.g., turn on duration of Q7] to increase progressively every switching cycle until an output voltage of the synchronous rectification circuit is greater than a second target voltage [e.g.,. -- refer to Figs. 12 and 13 --, increases cycle progressively until output voltage of transformer charges boot-strap capacitor CBS on node Vd during start-up period, p.0062 recites “Additionally, a short control pulse 1420 is applied to briefly turn on (and then turn off) and discharge the parasitic capacitance of the fourth low-side switching device Q8 of the synchronous rectifier. The short control pulse 1420 is also applied to the third high-side switching device Q5. The short control pulse 1420 is sufficiently short in duration to prevent (via circuit inductance) a damaging current from flowing within the power converter. A bias voltage boot-strap capacitor CBS is also charged for the fourth high-side switching device Q6 (see, e.g., FIGURE 13). Again, the duration of the short control pulses 1410, 1420 may be varied depending on the application.”], wherein a third initial turn-on duration of the third switch corresponding to the first switching cycle [e.g., turn-on duration of Q5 correspond to first witching cycle] is different from a fourth initial turn-on duration of the fourth switch corresponding to the first switching cycle [e.g., different from turn-on duration of Q7 corresponding to first switching cycle].
Regarding claim 13, Karlsson et al [e.g., Figs. 5 - 6 and 11 - 16] discloses wherein the controlling, by the control circuit [e.g., controller 1110], a turn-on duration of a first switch and a turn-on duration of a second switch in a first bridge circuit of the transformer circuit to increase progressively every switching cycle [e.g., -- refer to Fig. 14 for timing diagram --, increases turn-on progressively of Q1 and Q3], comprises: controlling, by the control circuit, a pulse width of a driving signal of the first switch [e.g., controls G1 for Q1] and a pulse width of a driving signal of the second switch to increase progressively every switching cycle [e.g., controls G3 for Q3 to increase progressively]; wherein a first initial pulse width of the driving signal of the first switch corresponding to the first switching cycle [e.g., first initial pulse 1410 during first switching cycle] is different from a second initial pulse width of the driving signal of the second switch corresponding to the first switching cycle [e.g., different from a second initial pulse width of switch Q3 during first switching cycle].
Regarding claim 15, Karlsson et al [e.g., Figs. 5 - 6 and 11 - 16] discloses wherein the controlling, by the control circuit, a pulse width of a driving signal of the first switch and a pulse width of a driving signal of the second switch to increase progressively every switching cycle [e.g., -- refer to Fig. 14 for timing diagram --, controlling by controller 1110 signals G1 and G3 to increase progressively], comprises: controlling, by the control circuit, the pulse width of the driving signal of the first switch and the pulse width of the driving signal of the second switch to increase progressively along a direction every switching cycle [e.g., controls signals G1 and G3 to increase as time increases];
Regarding claim 16, Karlsson et al [e.g., Figs. 5 - 6 and 11 - 16] discloses wherein the controlling, by the control circuit [e.g., controller 1110], a turn-on duration of a third switch [e.g., turn-on duration of Q5] and a turn-on duration of a fourth switch in a second bridge circuit of the synchronous rectification circuit [e.g., turn-on duration of Q7 forming a second bridge of the rectification circuit] to increase progressively every switching cycle [e.g., -- refer to Fig. 14 for timing diagram --, increases signals G5 and G7 to increase progressively], comprises: controlling, by the control circuit, a pulse width of a driving signal of the third switch [e.g., controls width of signa G5] and a pulse width of a driving signal of the fourth switch to increase progressively every switching cycle [e.g., controls width of signal G7 to increase progressively]; wherein a third initial pulse width of the driving signal of the third switch corresponding to the first switching cycle is different from a fourth initial pulse width of the driving signal of the fourth switch corresponding to the first switching cycle [e.g., initial pulse of Q5 is different from initial pulse of Q7 during the first switching cycle].
Regarding claim 18, Karlsson et al [e.g., Figs. 5 - 6 and 11 - 16] discloses wherein the controlling, by the control circuit, a pulse width of a driving signal of the third switch and a pulse width of a driving signal of the fourth switch to increase progressively every switching cycle [e.g., -- refer to Fig. 14 for timing diagram --, controlling by controller 1110 signals Q5 and Q7 to increase progressively], comprises: controlling, by the control circuit, the pulse width of the driving signal of the third switch [e.g., controls width of Q5] and the pulse width of the driving signal of the fourth switch to increase progressively along a direction every switching cycle [e.g., controls width of Q5 progressively as time increases];
Regarding claim 19, Karlsson et al [e.g., Figs. 5 - 6 and 11 - 16] discloses an electronic device [e.g., -- refer to Fig. 11 --, Power converter], comprising a direct current to direct current conversion (DCDC) circuit; wherein the DCDC circuit comprises: a transformer circuit [e.g., Q1 - Q4 with transformer Tr], a synchronous rectification circuit [e.g., Q5 - Q8], and a control circuit [e.g., controller 1110]; wherein the control circuit is configured to: control a turn-on duration of a first switch and a turn-on duration of a second switch in a first bridge circuit of the transformer circuit [e.g., -- refer to Fig. 14 for timing diagram --, control turn-on duration of Q1 and Q3] to increase progressively every switching cycle until an output voltage of the transformer circuit is greater than a first target voltage [e.g.,. -- refer to Figs. 5 and 6 --, increases cycle progressively until output voltage of transformer charges boot-strap capacitor CB2 during start-up period, p.0042 recites “The first energy transfer and transformer balancing pulse (a short control pulse) is improved by discharging parasitic capacitances of the first and second low-side switching devices Q3, Q4 of the power train, and charging the first and second bias voltage boot-strap capacitors CBI, CB2 for the first and second high-side switching devices Q l, Q2, respectively.”]; wherein a first initial turn-on duration of the first switch corresponding to a first switching cycle [e.g., turn on duration of Q1 (1410) during first switching cycle] is different from a second initial turn-on duration of the second switch corresponding to the first switching cycle [e.g., different turn-on than Q3 during same first switching cycle]; and control a turn-on duration of a third switch [e.g., turn-on duration of Q5] and a turn-on duration of a fourth switch [e.g., turn on duration of Q7] in a second bridge circuit of the synchronous rectification circuit [e.g., Q5 and Q7 forming second bridge of rectifier] to increase progressively every switching cycle until an output voltage of the synchronous rectification circuit is greater than a second target voltage [e.g.,. -- refer to Figs. 12 and 13 --, increases cycle progressively until output voltage of transformer charges boot-strap capacitor CBS on node Vd during start-up period, p.0062 recites “Additionally, a short control pulse 1420 is applied to briefly turn on (and then turn off) and discharge the parasitic capacitance of the fourth low-side switching device Q8 of the synchronous rectifier. The short control pulse 1420 is also applied to the third high-side switching device Q5. The short control pulse 1420 is sufficiently short in duration to prevent (via circuit inductance) a damaging current from flowing within the power converter. A bias voltage boot-strap capacitor CBS is also charged for the fourth high-side switching device Q6 (see, e.g., FIGURE 13). Again, the duration of the short control pulses 1410, 1420 may be varied depending on the application.”], wherein a third initial turn-on duration of the third switch corresponding to the first switching cycle [e.g., turn-on duration of Q5 correspond to first witching cycle] is different from a fourth initial turn-on duration of the fourth switch corresponding to the first switching cycle [e.g., different from turn-on duration of Q7 corresponding to first switching cycle].
Regarding claim 20, Karlsson et al [e.g., Figs. 5 - 6 and 11 - 16] discloses [e.g., full bridge Q1 - Q4], and the first switch comprises two switches located at a first bridge arm of the first bridge circuit [e.g., Q1 and Q3]; the second switch comprises two switches located at a second bridge arm of the first bridge circuit [e.g., Q2 and Q4]; and the first switch is connected to a voltage input terminal of the DCDC circuit [e.g., Q1 connected to VIN]; and the first initial turn-on duration of the first switch is less than the second initial turn-on duration of the second switch [e.g., -- refer to Fig. 14 for timing diagram --, turn-on duration of Q1 (1410) is less than turn-on duration of Q3 (D/2)].
Claim Rejections - 35 USC § 103
9. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
11. Claim(s) 4 - 5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Karlsson et al in view of Katayama (US Pub. No. 2004/0124817 A1); (hereinafter Karlsson et al and Katayama).
Regarding claim 4, Karlsson et al discloses the claimed invention except for wherein the control circuit is configured to: control the pulse width of the driving signal of the first switch and the pulse width of the driving signal of the second switch to increase by a first preset pulse width every n switching cycles, wherein n is a positive integer.
Katayama [e.g., Figs. 2 - 5] teaches wherein the control circuit [e.g., PWM Control Circuit 11] is configured to: control the pulse width of the driving signal of the first switch and the pulse width of the driving signal of the second switch [e.g., controls OUT1 and OUT2] to increase by a first preset pulse width every n switching cycles, wherein n is a positive integer [e.g., -- refer to Fig. 4 --, p. 0028 recites “FIG. 4 shows a timing chart of the step signal fed to the PWM control circuit. As shown in FIG. 4, n cycles of switching cycles T are assembled to a block. A pulse width of the pulse signal SR in the i-th block is denoted as TSRi. The TSRi equals mT, where m is an integer between any of zero to n. When a power source is switched from the series regulator 20 to the DC-DC converter 10 at the time t1, the step signal SR is in an `L` state in the 0-th block. In the blocks afterwards, pulse widths of the step signals gradually increase so that TSRi+1 > TSRi. The PWM control circuit 11 receives the step signal having pulse widths that increase after every predetermined stepping period by a specified increment step. In response to this step signal SR, the PWM control circuit 11 outputs the switching signal OUT2 to gradually increase the number of turn-ON of the transistor Q2. The drivers Z1 and Z2 drive the transistors Q1 and Q2 in accordance with the switching signals OUT1 and OUT2.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Karlsson et al with wherein the control circuit is configured to: control the pulse width of the driving signal of the first switch and the pulse width of the driving signal of the second switch to increase by a first preset pulse width every n switching cycles, wherein n is a positive integer as suggested by Katayama to gradually increase the number of turn-ons of the switching elements to mitigate or suppress backward current flows as a result of the charging/discharging of capacitors.
Regarding claim 5, Karlsson et al discloses the claimed invention except for wherein the first preset pulse width is a fixed value, or the first preset pulse width increases progressively along with the number of switching cycle increasing.
Katayama [e.g., Figs. 2 - 5] teaches wherein the first preset pulse width increases progressively along with the number of switching cycle increasing [e.g., -- refer to Fig. 4 --, TSRI which causes Q2 to turn on gradually increases as switching cycle increases].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Karlsson et al with wherein the first preset pulse width increases progressively along with the number of switching cycle increasing as suggested by Katayama to gradually increase the number of turn-ons of the switching elements to mitigate or suppress backward current flows as a result of the charging/discharging of capacitors.
Regarding claim 14, Karlsson et al [e.g., Figs. 5 - 6 and 11 - 16] discloses wherein the controlling, by the control circuit [e.g., controlling by controller 1110], a pulse width of a driving signal of the first switch and a pulse width of a driving signal of the second switch to increase progressively every switching cycle [e.g., -- refer to Fig. 14 for timing diagram --, controls G1 and G3 to increase progressively].
Karlsson et al does not discloses controlling, by the control circuit, the pulse width of the driving signal of the first switch and the pulse width of the driving signal of the second switch to increase by a first preset pulse width every n switching cycles, wherein n is a positive integer.
Katayama [e.g., Figs. 2 - 5] teaches controlling, by the control circuit [e.g., PWM Control Circuit 11], the pulse width of the driving signal of the first switch and the pulse width of the driving signal of the second switch [e.g., controls OUT1 and OUT2] to increase by a first preset pulse width every n switching cycles, wherein n is a positive integer [e.g., -- refer to Fig. 4 --, p. 0028 recites “FIG. 4 shows a timing chart of the step signal fed to the PWM control circuit. As shown in FIG. 4, n cycles of switching cycles T are assembled to a block. A pulse width of the pulse signal SR in the i-th block is denoted as TSRi. The TSRi equals mT, where m is an integer between any of zero to n. When a power source is switched from the series regulator 20 to the DC-DC converter 10 at the time t1, the step signal SR is in an `L` state in the 0-th block. In the blocks afterwards, pulse widths of the step signals gradually increase so that TSRi+1 > TSRi. The PWM control circuit 11 receives the step signal having pulse widths that increase after every predetermined stepping period by a specified increment step. In response to this step signal SR, the PWM control circuit 11 outputs the switching signal OUT2 to gradually increase the number of turn-ON of the transistor Q2. The drivers Z1 and Z2 drive the transistors Q1 and Q2 in accordance with the switching signals OUT1 and OUT2.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Karlsson et al with controlling, by the control circuit, the pulse width of the driving signal of the first switch and the pulse width of the driving signal of the second switch to increase by a first preset pulse width every n switching cycles, wherein n is a positive integer as suggested by Katayama to gradually increase the number of turn-ons of the switching elements to mitigate or suppress backward current flows as a result of the charging/discharging of capacitors.
12. Claim(s) 9 - 10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Karlsson et al (WO 2017/168220 A1) in view of Cao et al (US Pub. No. 2018/0248488 A1); (hereinafter Karlsson et al and Cao et al).
Regarding claim 9, Karlsson et al discloses wherein the control circuit [e.g., controller 1110] is configured to: control the pulse width of the driving signal of the third switch and the pulse width of the driving signal of the fourth switch to increase [e.g., -- refer to Fig. 14 for timing diagram --, controls width of driving signals G and G7 to increase during start-up
Karlsson et al does not discloses to increase by a second preset pulse width every m switching cycles, wherein m is a positive integer.
Cao et al [e.g., Figs. 3 - 8] teaches to increase by a second preset pulse width every m switching cycles [e.g., -- refer to Fig. 8 --, Tdly(n), 890], wherein m is a positive integer [e.g., n is a positive integer larger than , p. 0100 recites “According to one embodiment, a pulse width of the timing signal 335 is determined by: Tsron(n)=T0+Tdly(n) where Tsron(n) represents an actual pulse width of the timing signal 335 during the nth switching cycle. Additionally, T0 represents a predetermined initial pulse width of the timing signal 335. Moreover, Tdly(n) represents an increase in actual pulse width of the timing signal 335 during the nth switching cycle in comparison with the predetermined initial pulse width of the timing signal 335. Also, n is a positive integer. For example, the nth switching cycle is the switching cycle TA. In another example, the nth switching cycle is the switching cycle TB. In yet another example, the nth switching cycle is the switching cycle TC.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Karlsson et al with a second preset pulse width every m switching cycles, wherein m is a positive integer as suggested by Cao et al to increase the pulse width of the driving signals to proportionally increase and the switching cycles increases.
Regarding claim 10, Karlsson et al discloses the claimed invention except for wherein the second preset pulse width is a fixed value, or the second preset pulse width increases progressively along with the number of switching cycle increasing.
Cao et al [e.g., Figs. 3 - 8] teaches wherein the second preset pulse width [e.g., Tdly(n)] increases progressively along with the number of switching cycle increasing [e.g., increases as switching cycle increases, p. 0101 recites “…where Tdly(1) represents an increase in actual pulse width of the timing signal 335 during the 1st switching cycle in comparison with the predetermined initial pulse width of the timing signal 335. For example, the 1st switching cycle is the switching cycle TA.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Karlsson et al with wherein the second preset pulse width is a fixed value as suggested by Cao et al to increase the pulse width of the driving signals to proportionally increase and the switching cycles increases.
Regarding claim 17, Karlsson et al [e.g., Figs. 5 - 6 and 11 - 16] discloses wherein the controlling, by the control circuit, a pulse width of a driving signal of the third switch and a pulse width of a driving signal of the fourth switch to increase progressively every switching cycle [e.g., controlling by controller 1110 signals G5 and G7], comprises: controlling, by the control circuit, the pulse width of the driving signal of the third switch and the pulse width of the driving signal of the fourth switch to increase [e.g., -- refer to Fig. 14 for timing diagram --, driving signals increasing during start-up].
Karlsson et al does not discloses to increase by a second preset pulse width every m switching cycles, wherein m is a positive integer.
Cao et al [e.g., Figs. 3 - 8] teaches to increase by a second preset pulse width every m switching cycles [e.g., -- refer to Fig. 8 --, Tdly(n), 890], wherein m is a positive integer [e.g., n is a positive integer larger than , p. 0100 recites “According to one embodiment, a pulse width of the timing signal 335 is determined by: Tsron(n)=T0+Tdly(n) where Tsron(n) represents an actual pulse width of the timing signal 335 during the nth switching cycle. Additionally, T0 represents a predetermined initial pulse width of the timing signal 335. Moreover, Tdly(n) represents an increase in actual pulse width of the timing signal 335 during the nth switching cycle in comparison with the predetermined initial pulse width of the timing signal 335. Also, n is a positive integer. For example, the nth switching cycle is the switching cycle TA. In another example, the nth switching cycle is the switching cycle TB. In yet another example, the nth switching cycle is the switching cycle TC.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Karlsson et al with a second preset pulse width every m switching cycles, wherein m is a positive integer as suggested by Cao et al to increase the pulse width of the driving signals to proportionally increase and the switching cycles increases.
Examiner’s Note
13. Examiner has cited particular columns, paragraphs and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figure may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art disclosed by the Examiner.
14. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention
Conclusion
15. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US Pub. No. 2015/0365005 A1 (Panov et al) discloses methods for controlling dual-active-bridge (DAB) bidirectional converters.
US Pub. No. 2022/0077767 A1 (WANG et al) discloses a startup control method and system for a DC/DC converter.
US Pub. No. 2013/0141945 A1 (Karlsson et al) discloses a start-up of an isolated switched mode power supply having a full-bridge primary side topology.
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/ULARISLAO CORDOVA/ Examiner, Art Unit 2838
/FRED E FINCH III/ Primary Examiner, Art Unit 2838
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