DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
For claim 2, it is unclear whether “a first clock filter” and “a first clock enable circuit” are one of the plurality of clock filters and plurality of clock enable circuits of claim 1, respectively.
For the purposes of examination, examiner will interpret these limitations as “a first clock filter of the plurality of clock filters” and “a first clock enable circuit of the plurality of clock enable circuits.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 4, 5, 7, and 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Meguro et al (US 2004/0012435) in view of official notice.
For claim 1, Meguro teaches a system (Figure 4), comprising:
a plurality of clock generation circuits (circuits not shown which generate clk_1 to clk_x) for respectively outputting a plurality of individual clock signals (clk_1 to clk_x);
a plurality of clock enable circuits (10, as understood by Figures 4-5), correspondingly electrically connected to the plurality of clock generation circuits (as understood by examination of Figures 4-5), for respectively outputting a plurality of individual output signals (ckout_1 to ckout_x) and a plurality of enable signals (cken_1 to cken_x);
a feedback logic circuit (30), electrically connected to the plurality of clock enable circuits, for performing an inverse OR (NOR) operation on the plurality of enable signals to generate a feedback signal (chen, as understood by examination of Figure 4);
a plurality of clock control circuits (40), electrically connected to the feedback logic circuit (each 40 is connected to clkout, which is based upon each clkout_, each of which is based upon the feedback signal chen) and correspondingly electrically connected to the plurality of clock generation circuits (each 40 is connected to clkout, which is based upon each clkout_, each clkout_ is based upon clk_), for respectively generating and outputting a plurality of control signals (signal at each Q terminal) according to the feedback signal and the plurality of enable signals to respectively control the plurality of individual clock signals to be turned on or turned off ([27]); and
an output logic circuit (20), electrically connected to the plurality of clock enable circuits, for performing an OR operation on the plurality of individual output signals to generate an output signal (clkout), wherein:
when switching clock filters, a source individual clock signal (selected clock before switching) and a target individual clock signal (selected clock after switching) are controlled to be turned on at different times (non-overlapping, [59], [69]-[70]).
Meguro fails to teach:
a plurality of clock filters for respectively outputting a plurality of individual clock signals;
However, examiner takes official notice that it is notoriously old and well known to use a low-pass filter to remove noise from a signal.
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to filter each of Meguro’s clk_1 to clk_x using a low-pass filter in order to remove jitter and/or high frequency noise from each of the plurality of individual clock signals.
Furthermore, the particular known technique (filtering noise using a low pass filter) was recognized as part of the ordinary capabilities of one skilled in the art.
For claim 2, Meguro in view of official notice teaches the limitations of claim 1 and further teaches:
the plurality of clock control circuits comprise a first clock control circuit (40 which receives sel_1) corresponding to a first clock filter (low pass filter for clk_1) and a first clock enable circuit (10-1, as understood by examination of Figure 4), wherein:
the first clock enable circuit being for generating a first enable signal (cken_1) according to a first individual clock signal (clk_1), a filter selection signal (sel_1), and the feedback signal (as understood by examination of Figures 4-5), and
the first clock control circuit being for generating a first control signal (signal at Q terminal) according to the feedback signal, the first enable signal (as explained in the rejection of claim 1 above) and an input signal (signal at D terminal).
For claim 4, Meguro teaches a system (Figures 4-5), comprising:
a plurality of clock generation circuits (circuits not shown which generate clk_1 to clk_x) for respectively outputting a plurality of individual clock signals (clk_1 to clk_x);
a plurality of clock enable circuits (10, as understood by Figures 4-5), correspondingly electrically connected to the plurality of clock generation circuits (as understood by examination of Figures 4-5), for respectively outputting a plurality of individual output signals (ckout_1 to ckout_x) and a plurality of enable signals (cken_1 to cken_x);
a feedback logic circuit (30), electrically connected to the plurality of clock enable circuits, for performing an inverse OR (NOR) operation on the plurality of enable signals to generate a feedback signal (chen, as understood by examination of Figure 4);
a plurality of clock control circuits (40), electrically connected to the feedback logic circuit (each 40 is connected to clkout, which is based upon each clkout_, each of which is based upon the feedback signal chen) and correspondingly electrically connected to the plurality of clock generation circuits (each 40 is connected to clkout, which is based upon each clkout_, each clkout_ is based upon clk_), for respectively generating and outputting a plurality of control signals (signal at each Q terminal) according to the feedback signal and the plurality of enable signals to respectively control the plurality of individual clock signals to be turned on or turned off ([27]); and
an output logic circuit (20), electrically connected to the plurality of clock enable circuits, for performing an OR operation on the plurality of individual output signals to generate an output signal (clkout), wherein:
when switching clock filters, a source individual clock signal (selected clock before switching) and a target individual clock signal (selected clock after switching) are controlled to be turned on at different times (non-overlapping, [59], [69]-[70]).
Meguro fails to teach:
a bypass circuit for outputting a bypass output signal and a bypass enable signal; and
a plurality of clock filters for respectively outputting a plurality of individual clock signals;
However, examiner takes official notice that it is notoriously old and well known to use a low-pass filter to remove noise from a signal.
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to filter each of Meguro’s clk_1 to clk_x using a low-pass filter in order to remove jitter and/or high frequency noise from each of the plurality of individual clock signals.
Furthermore, the particular known technique (filtering noise using a low pass filter) was recognized as part of the ordinary capabilities of one skilled in the art.
The combination of Meguro and official notice as cited above fails to teach the bypass circuit as claimed.
However, Meguro teaches that the input clock signals can be “generated from one reference clock signal by dividing at different dividing ratios” or alternatively, clock signals individually generated by a plurality of different PLL circuits or oscillators” [26].
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to implement Meguro’s clock signals (clk_1 to clk_x) using a combination of divided clock signals and a non-divided clock (i.e., bypassing all dividers) since Meguro’s clock switching circuit is designed for “freely selected…clock signals having different frequencies and phases while preventing generation of a hazard” (Abstract).
Furthermore, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention.
The modified combination of Meguro and official notice teaches:
a bypass circuit (10 corresponding to a non-divided clock clk_) for outputting a bypass output signal (ckout_ corresponding to the non-divided clock) and a bypass enable signal (cken_ corresponding to the non-divided clock);
For claim 5, the modified combination of Meguro and official notice teaches the limitations of claim 4 and further teaches:
the plurality of clock control circuits comprise a first clock control circuit (40 which receives sel_1) corresponding to a first clock filter (low pass filter for clk_1) and a first clock enable circuit (10-1, as understood by examination of Figure 4), wherein:
the first clock enable circuit being for generating a first enable signal (cken_1) according to a first individual clock signal (clk_1), a filter selection signal (sel_1), and the feedback signal (as understood by examination of Figures 4-5), and
the first clock control circuit being for generating a first control signal (signal at Q terminal) according to the feedback signal, the first enable signal (as explained in the rejection of claim 1 above) and an input signal (signal at D terminal).
For claim 7, the modified combination of Meguro and official notice teaches the limitations of claim 4 and further teaches:
the bypass circuit is not directly electrically connected to a clock filter (the subcircuit within 10 corresponding to the non-divided clock is distinct from the remaining elements within 10, i.e., the plurality of clock enable circuits) and is for generating the bypass enable signal according to an input signal (non-divided clock), a filter selection signal (sel_ signal corresponding to the non-divided clock), and the feedback signal (as understood by examination of Figures 4-5).
For claim 9, Meguro teaches a method, adapted for a clock filter system, the clock filter switching method comprising:
after a triggering event of switching clock signals occurs (after T1, Figures 3C and 3D), setting a selection signal to stop indicating a source clock (Figure 3C) and thereby triggering a source enable signal (corresponding cken_, Figure 5) output by a source clock enable circuit (corresponding 10) to switch off (as understood by examination of Figures 3-5 and [46]-[63]), and triggering a source control signal output (at Q terminal) by a source clock control circuit (corresponding 40) to control the source clock to stop outputting a source individual clock signal (as understood by examination of the Figures and [46]-[63]); and
setting the selection signal to start indicating a target clock (Figure 3D) and thereby triggering a target enable signal (corresponding cken_, Figure 5) output by a target clock enable circuit to switch on (as understood by examination of the Figures and [46]-[63]), and triggering a target control signal output (at Q terminal) by a target clock control circuit (corresponding 40) to control the target clock to output a target individual clock signal (as understood by examination of Figure 3I), wherein:
a feedback signal (chen) is generated by performing an NOR operation on the source enable signal and the target enable signal (as understood by examination of Figure 4), the source control signal is generated based on the feedback signal and the source enable signal (as understood by examination of the Figures), and the target control signal is generated based on the feedback signal and the target enable signal (as understood by examination of the Figures).
Meguro fails to teach a clock filter as claimed.
However, examiner takes official notice that it is notoriously old and well known to use a low-pass filter to remove noise from a signal.
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to filter each of Meguro’s clk_1 to clk_x using a low-pass filter in order to remove jitter and/or high frequency noise from each of the plurality of individual clock signals.
Furthermore, the particular known technique (filtering noise using a low pass filter) was recognized as part of the ordinary capabilities of one skilled in the art.
For claim 10, the combination of Meguro and official notice teaches the limitations of claim 9 but fails to teach a bypass circuit as claimed.
However, Meguro teaches that the input clock signals can be “generated from one reference clock signal by dividing at different dividing ratios” or alternatively, clock signals individually generated by a plurality of different PLL circuits or oscillators” [26].
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to implement Meguro’s clock signals (clk_1 to clk_x) using a combination of divided clock signals and a non-divided clock (i.e., bypassing all dividers) since Meguro’s clock switching circuit is designed for “freely selected…clock signals having different frequencies and phases while preventing generation of a hazard” (Abstract).
Furthermore, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention.
The modified combination of Meguro and official notice teaches:
after a triggering event of switching voltages occurs, setting the selection signal to switch to indicate a bypass circuit (10 corresponding to a non-divided clock clk_) and thereby triggering the source enable signal to switch off (as understood by examination of Figures 3-5), and triggering a bypass enable signal output by the bypass circuit to switch on (as understood by examination of Figures 3-5);
after switching to the bypass circuit, determining whether a target voltage (voltage level associated with cken_ corresponding to target, Figure 5) is lower than a source voltage (voltage level associated with cken_ corresponding to source, Figure 5); and if the target voltage is lower than the source voltage, after completing switching to the target voltage, setting the selection signal to switch to indicate the target clock filter and thereby triggering the bypass enable signal to switch off, and triggering the target enable signal to switch on (as understood by examination of Figures 3-5).
Allowable Subject Matter
Claims 3, 6 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Specifically, the prior art fails to teach the OR gate of claims 3 and 6, and the encoding of claim 8.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL CALRISSIAN PUENTES whose telephone number is (571)270-5070. The examiner can normally be reached M-F 9-6:30 (flex).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL C PUENTES/Primary Examiner, Art Unit 2849