DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 6/15/2026 have been fully considered but they are not persuasive. Applicant’s first argument is as follows:
“Regarding claims 1 and 2, while utilizing an identical logical operation, when such an operation is integrated with the specific "clock filter" and "clock control circuit" of the present application, the resultant control objective and physical efficacy accomplished by the overall hardware closed-loop feedback path diverge fundamentally and significantly from the teachings of Meguro…During operation, once the enabling signal is activated, a clock signal of any frequency propagates through the circuit completely unmodified. Consequently, the internal topology of Meguro entirely lacks the physical architecture or characteristics required to establish a "cutoff frequency." This is in sharp contrast to the claimed invention.”
Meguro was not relied upon for the teaching a clock filter, see ¶16-20 of the 3/16/2026 Non-Final Rejection.
Applicant’s second argument is as follows:
“That is, conversely, the "clock filter of the claimed invention (as explicitly supported by paragraphs [0043] and [0044] of the specification) incorporates a physical delay chain of a predetermined length, pulse generators, and an SR latch, effectively functioning as a physical "low-pass filter" within the microelectronics domain. Its structural hardware utility dictates that when an input clock frequency exceeds the filter's designated cutoff frequency, the filter structurally attenuates, filters out, and obstructs the propagation of said high-frequency clock signal. Therefore, the digital gating logic of Meguro and the physical filter of the present application are structurally and electronically distinct in circuitry essence and must not be conflated.”
Meguro was not relied upon to teach the claimed plurality of clock filters, see ¶16-20 of the 3/16/2026 Non-Final Rejection.
Since it was believed that Applicant’s argument was directed to the combination of Meguro and official notice, Examiner proposed amending the independent claims in accordance with the cited argument to require that the clock filter comprises a delay, pulse generator and an SR latch, see Interview Summary. Since the Applicant declined the proposed amendment, Examiner will continue to interpret the claimed clock filter under broadest reasonable interpretation.
Applicant’s third argument is as follows:
“Moreover, in Meguro, the sole intent of the inverse OR (NOR) operation performed by the NOR gate is to establish a "clock state interlock" during transitions between clock sources of differing frequencies and phases. Its feedback loop merely verifies that the previous clock output has ceased before allowing the subsequent clock path to activate, strictly for the purpose of hazard avoidance. This is in sharp contrast to the claimed invention… in contrast to Meguro, in the claimed invention, the feedback signal generated by the NOR operation is coupled to a plurality of "clock control circuits," with the explicit control purpose of implementing real-time "clock gating" for the plurality of clock filters in response to a Dynamic Voltage Frequency Scaling (DVFS) environment… this synergistic, unexpected dual effect of "preventing switching glitches" and "deep power management of the clock filters" is neither disclosed nor suggested in Meguro, which entirely neglects power management and lacks any filter delay chain architecture. Thus, the claimed invention (e.g., as defined at least by claims 1 and 2) is not obvious in view of Meguro.”
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., real time clock gating in response to a DVFS environment, preventing glitches and deep power management) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant’s fourth argument is as follows:
“Meguro-whether in its drawings or specification-fails to disclose or imply the unique inverse OR (NOR) logic input vector configuration specified in claim 4 of the present application…
Applicant’s arguments with respect to claim 4 have been considered and are found persuasive. The rejection of claims 4, 5 and 7 have been withdrawn.
Applicant’s fifth argument is as follows:
“Finally, regarding claims 9 and 10, Applicants have incorporated all the technical features of original dependent claim 10 into independent claim 9.”
Applicant’s arguments with respect to claim 9 have been considered and are found persuasive. The rejection of claim 9 has been withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 and 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Meguro et al (US 2004/0012435) in view of official notice.
For claim 1, Meguro teaches a system (Figure 4), comprising:
a plurality of clock generation circuits (circuits not shown which generate clk_1 to clk_x) for respectively outputting a plurality of individual clock signals (clk_1 to clk_x);
a plurality of clock enable circuits (10, as understood by Figures 4-5), correspondingly electrically connected to the plurality of clock generation circuits (as understood by examination of Figures 4-5), for respectively outputting a plurality of individual output signals (ckout_1 to ckout_x) and a plurality of enable signals (cken_1 to cken_x);
a feedback logic circuit (30), electrically connected to the plurality of clock enable circuits, for performing an inverse OR (NOR) operation on the plurality of enable signals to generate a feedback signal (chen, as understood by examination of Figure 4);
a plurality of clock control circuits (40), electrically connected to the feedback logic circuit (each 40 is connected to clkout, which is based upon each clkout_, each of which is based upon the feedback signal chen) and correspondingly electrically connected to the plurality of clock generation circuits (each 40 is connected to clkout, which is based upon each clkout_, each clkout_ is based upon clk_), for respectively generating and outputting a plurality of control signals (signal at each Q terminal) according to the feedback signal and the plurality of enable signals to respectively control the plurality of individual clock signals to be turned on or turned off ([27]); and
an output logic circuit (20), electrically connected to the plurality of clock enable circuits, for performing an OR operation on the plurality of individual output signals to generate an output signal (clkout), wherein:
when switching clock filters, a source individual clock signal (selected clock before switching) and a target individual clock signal (selected clock after switching) are controlled to be turned on at different times (non-overlapping, [59], [69]-[70]).
Meguro fails to teach:
a plurality of clock filters for respectively outputting a plurality of individual clock signals;
However, examiner takes official notice that it is notoriously old and well known to use a low-pass filter to remove noise from a signal.
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to filter each of Meguro’s clk_1 to clk_x using a low-pass filter in order to remove jitter and/or high frequency noise from each of the plurality of individual clock signals.
Furthermore, the particular known technique (filtering noise using a low pass filter) was recognized as part of the ordinary capabilities of one skilled in the art.
For claim 2, Meguro in view of official notice teaches the limitations of claim 1 and further teaches:
the plurality of clock control circuits comprise a first clock control circuit (40 which receives sel_1) corresponding to a first clock filter (low pass filter for clk_1) and a first clock enable circuit (10-1, as understood by examination of Figure 4), wherein:
the first clock enable circuit being for generating a first enable signal (cken_1) according to a first individual clock signal (clk_1), a filter selection signal (sel_1), and the feedback signal (as understood by examination of Figures 4-5), and
the first clock control circuit being for generating a first control signal (signal at Q terminal) according to the feedback signal, the first enable signal (as explained in the rejection of claim 1 above) and an input signal (signal at D terminal).
Allowable Subject Matter
Claims 4-9 are allowed.
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Specifically, the prior art fails to teach the OR gate.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Sharma et al (US 7,944,241) teaches clock enable circuits as claimed (200) and an OR gate (300) but fails to teach the bypass circuit as claimed.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL CALRISSIAN PUENTES whose telephone number is (571)270-5070. The examiner can normally be reached M-F 9-6:30 (flex).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Taelor Kim can be reached at (571) 270-7166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL C PUENTES/Primary Examiner, Art Unit 2836
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