DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/16/24 has been considered by the examiner.
Drawings
The drawings were received on 12/16/24 are acceptable.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 12, 13 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamamoto Shotaro (US 2023/179196 A1).
Yamamoto et al. disclose a drive control device for power semiconductor element and power module in Figures 1-15.
Regarding claim 1. A gate drive circuit (Figure 2, 10A) for driving an electrical gate quantity present at a gate electrode of a semiconductor switch of an inverter (Figure 1, 103), the gate drive circuit (10A) configured to: in a pre-defined operating interval during operation of the inverter (Figure 8, interval t1-t5), alternate the electrical gate quantity (Figure 8, charge driving capability, discharge driving capability) between a maximum gate quantity value and a minimum gate quantity value to switch the semiconductor switch in order to connect or disconnect a supply voltage (Figure 1, PL) to an output of the inverter (Figure 1, Nu), wherein the gate drive circuit is further configured to , at an adjustment time point (Figure 8, ta) during the operating interval, adjust the maximum gate quantity value to an adjusted maximum gate quantity value (see Figure 8, see Figure 7, see paragraphs 102, 110, 113-118), to further alternate the electrical gate quantity between the adjusted maximum gate quantity value and the minimum gate quantity value to switch the semiconductor switch.
Regarding Claim 12. The gate drive circuit according to claim 1, wherein the adjustment time point and the adjusted maximum gate quantity value are pre-set before a start of operation of the inverter (see Figure 8, see Figure 7, see paragraphs 102, 110, 113-118).
Regarding claim 13. An assembly comprising an inverter (Figure 1, 103), a power cable (PL, NL) and an electrical load (motor 104), an output of the inverter is electrically connected to the electrical load by the power cable in order to electrically supply the electrical load, and the inverter comprising at least one semiconductor switch and a gate drive circuit for driving an electrical gate quantity (Figure 8, charge driving capability, discharge driving capability) present at a gate electrode of a semiconductor switch of the inverter (103), the gate drive circuit configured to: in a pre-defined operating interval during operation of the inverter (103), alternate the electrical gate quantity between a maximum gate quantity value and a minimum gate quantity value to switch the semiconductor switch in order to connect or disconnect a supply voltage to the output of the inverter, wherein the gate drive circuit is further configured to, at an adjustment time point during the operating interval, adjust the maximum gate quantity value to an adjusted maximum gate quantity value , (see Figure 8, see Figure 7, see paragraphs 102, 110, 113-118), to further alternate the electrical gate quantity between the adjusted maximum gate quantity value and the minimum gate quantity value to switch the semiconductor switch .
Regarding claim 15. A method for operating a gate drive circuit (Figure 2, 10A) for driving an electrical gate quantity present at a gate electrode of a semiconductor switch of an inverter (Figure 1, 103), comprising: in a pre-defined operating interval during operation of the inverter (Figure 8, interval t1-t5), alternating the electrical gate quantity (Figure 8, charge driving capability, discharge driving capacity) between a maximum gate quantity value and a minimum gate quantity value in order to switch the semiconductor switch.
Allowable Subject Matter
Claims 2-11, 14 and 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 2 is allowed because the prior art of record fails to disclose or suggest a gate driver circuit including the limitation “wherein the gate drive circuit is further configured to at an at least one detection time point during the operating interval detect at least one measured value of a physical inverter quantity (x) representative of an operating condition assumed by the inverter during the operating interval wherein the adjustment time point is provided as an adjustment time point during the operating interval after the detection time point, and wherein the gate drive circuit is configured to, at the adjustment time point, adjust the maximum gate quantity value to the adjusted maximum gate quantity value depending on the at least one measured value of the physical inverter quantity“ in addition to other limitations recited therein.
Dependent claims 7-10 and 16-17 are allowable by virtue of their dependency.
Claim 3 is allowed because the prior art of record fails to disclose or suggest a gate driver circuit including the limitation “wherein the maximum gate quantity value is pre-set before a start of operation of the inverter and adjusted to the adjusted maximum gate quantity value during operation of the inverter t the adjustment time point“ in addition to other limitations recited therein.
Claim 4 is allowed because the prior art of record fails to disclose or suggest a gate driver circuit including the limitation “wherein the adjusted maximum gate quantity value is smaller than the maximum gate quantity value or in that the adjusted maximum gate quantity value is larger than the maximum gate quantity value“ in addition to other limitations recited therein.
Claim 5 is allowed because the prior art of record fails to disclose or suggest a gate driver circuit including the limitation “wherein an electrical supply unit to supply the gate electrode with an electrical supply quantity to create the electrical gate quantity, a main gate resistor, at least one switchable gate resistor, and a bypass switch are provided in the gate drive circuit, the supply unit resistor electrically connected to the gate electrode by a second switchable gate resistor terminal, and in that the gate drive circuit is configured to switch the bypass switch, hence bypassing the at least one switchable gate resistor, in order to adjust the maximum gate quantity value to the adjusted maximum gate quantity value“ in addition to other limitations recited therein.
Claim 6 is allowed because the prior art of record fails to disclose or suggest a gate driver circuit including the limitation “wherein an electrical supply unit to supply the gate electrode with an electrical supply quantity to create the electrical gate quantity and a push-pull converter are provided in the gate drive circuit, the push-pull converter electrically connected to the supply unit by an electrical connection between a supply unit output terminal and a first push-pull converter terminal, the at least one push-pull converter electrically connected to the gate electrode via a second push-pull converter terminal, and in that the gate drive circuit is configured to switch at least one switch of the push-pull converter to adjust the maximum gate quantity value to the adjusted maximum gate quantity value“ in addition to other limitations recited therein.
Claim 11 is allowed because the prior art of record fails to disclose or suggest a gate driver circuit including the limitation “wherein the gate drive circuit, in order to adjust the maximum value maximum gate quantity value, is configured to modify at least one value selected from the group consisting of a gate resistance, a gate power supply voltage, a gate current, a gate-emitter capacitance and a gate-emitter capacitance“ in addition to other limitations recited therein.
Claim 14 is allowed because the prior art of record fails to disclose or suggest a gate driver circuit including the limitation “wherein: the gate drive circuit is configured to detect an electrical cable quantity of the power cable as the at least one measured value the gate drive circuit is further configured to identify at least one cable parameter from the least one measured value, the cable parameter representative of the operating condition assumed by the inverter during the operating interval, and the gate drive circuit is configured to adjust the maximum gate quantity value dependent on the at least one cable parameter “ in addition to other limitations recited therein.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Schalk et al. (US 2025/0246976 A1) disclose an electrical motor assembly with a motor cable and a method for identifying a motor cable in an electrical motor assembly.
Examiner has cited particular columns, line numbers and/or paragraphs in the
references applied to the claims above for the convenience of the applicant. Although
the specified citations are representative of the teachings of the art and are applied to
specific limitations within the individual claim(s), other passages and figures may apply
as well.
Additionally, in the event that other prior art is provided and made of record by the
Examiner, as being relevant or pertinent to applicant's disclosure but not relied upon.
The references are provided for the convenience of the applicant.
The Examiner request that the references be considered in any subsequent amendments, as they are also representative of the art and may apply to the specific limitations of any newly amended claim(s).
It is respectfully requested from the applicant in preparing amendments or responses, to
fully consider the references in their entirety as potentially teaching all or part of the
claimed invention, as well as the context of the passage as taught by the prior art and/or
disclosed by the Examiner.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADOLF D BERHANE whose telephone number is (571)272-2077. The examiner can normally be reached 7 AM - 10 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal Hammond can be reached at 571-270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ADOLF D BERHANE/Primary Examiner, Art Unit 2838
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