Detailed Action
Summary
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1.This office action is in response to the application filed on December 16,2024.
2. Claims 1-15 are pending and has been examined.
Information Disclosure Statement
3.The information disclosure statement (IDS) submitted on 12/15/2025 and 12/16/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
4. The drawings submitted on 12/16/2024 are acceptable.
Claim Objections
5. Claim 5 is objected to because of the following informalities:
Claim 5 recites “first switch ( and “ in line 9 and an open parathesis should be removed. Appropriate correction is required.
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 9-15 are rejected under 35 U.S.C. 103 as being unpatentable over Chandrasekaran “20140169049” in a view of Park “KR 20150085638”.
In regard to claim 1, Chandrasekaran discloses a power control device (Figs. 3 and 5 ; controller 310/510 are used for power converter formed with two interleaved boost switching regulators , see paragraphs 23-28) comprising:
a rectifier (Figure 3, rectifier 350; see paragraphs 23-28) configured to rectify an
input current (Figure 3, input current from the ac power source providing an
input voltage VIN; Paragraph 23);
a first switch (Figure 3, first switch SA1; Paragraphs 23-28) and a second switch
(Figure 3, second switch SA₂; Paragraphs 23-28) connected to an output of the
rectifier to control a phase of the output of the rectifier (350);
a first current sensor (Figure 3, first current sensor resistor R1; Paragraphs
23-28) configured to sense a current through the first switch (SA1) and a second
current sensor (Figure 3, second current sensor resistor R2; Paragraphs 23-28)
configured to sense a current through the second switch (SA2);
at least one processor (Paragraph 39) configured to sample the currents filtered
by the low pass filter once per entire switching cycle of the first switch and the
second switch and perform balancing control based on the sampled currents
such that an average value of the current through the first switch and the current
through the second switch is uniform for a certain period (Figures 3-4;
Paragraphs 27-29, current balancing is achieved by comparing the current
samples from the two interleaved boost switching regulators. Average currents
are obtained by sampling currents in the first and second main power switches
SA₁ and SA₂ at their respective mid-points of their ON durations) but fails to discloses a low pass filter configured to filter the current sensed by the first current sensor
and the current sensed by the second current sensor; and
Whereas , Park discloses a low pass filter configured to filter the current sensed by the first current sensor and the current sensed by the second current sensor (Figs. 2 and 5 shows current sensing Rsense1 and Rsense2 are configured to sense a current flowing thru switches SW1 and SW2 and first and second low-pass filters 19 and 21 are coupled to Rsense1 and 2 and sensing voltage is passed through a low-pass filter 19 and 21 (equivalent to LPF) to eliminating switching noise and digital signal processor 23 receives the filtering current input through the first and second low-pass filters 19 and 21 and compares the filtered current with the reference rated current (S503). see abstract , pages 3 ,lines 15-36 and page 4, lines 1-25.
Therefore, it would have been obvious to one of ordinary skilled in the art before the effective filing date of the claimed invention to have modified the power control device of Chandrasekaran to include LPF as taught by Park because eliminating switching noise /noise reduction and creates smoothing signal data which improve the reliability and efficiency of the converter.
In regard to claim 2, Chandrasekaran as modified discloses (Figs. 3-6) wherein a first value of the first current (Park; current flowing SW1) filtered by the low pass filter (low pass filter 19) has a first uniform value within a first deviation value in the switching cycle of the first switch (SW1), and wherein a second value of the second current (current flowing SW2) filtered by the low pass filter (low pass filter 21) has a second uniform value within a second deviation value in the switching cycle of the second switch (SW2).
In regard to claim 3, Chandrasekaran as modified discloses (Figs. 3-6) wherein the at least one processor (Paragraph 0039) is further configured to perform power factor correction (see parag. 0004-005 and 0023) based on the performed balancing control (Figures 3-4; and Paragraphs 27-29, current balancing is achieved by comparing the current samples from the two interleaved boost switching regulators).
In regard to claim 4, Chandrasekaran as modified discloses (Figs. 3-6) wherein the at least one processor (parag. 0039) is further configured to simultaneously obtain an average value per switching cycle of the first current flowing through the first switch and the second current flowing through the second switch by sampling the filtered first current and the filtered second current once per switching cycles of the first switch and the second switch (see parag. 0025 and 0027-0029).
In regard to claim 5, Chandrasekaran as modified discloses (Figs. 3-6) further comprising: an output current sensor configured to sense an output current of the rectifier (the inverting input of the error amplifier 320 is coupled to the output voltage Vout through a resistor-divider (not shown) to produce a scaled value of the output voltage Vout., see, parag.0026); a direct current (DC) link capacitor (CH) configured to smooth an output voltage of the rectifier (350) ; and a voltage sensor configured to sense a voltage across the DC link capacitor, wherein the output current of the rectifier and the voltage across the DC link capacitor are input to a controller, and wherein the at least one processor is further configured to controls switching of the first switch (and the second switch through an output of the controller (the inverting input of the error amplifier 320 is coupled to the output voltage Vout through a resistor-divider (not shown) to produce a scaled value of the output voltage Vout., see prag.0026-0027).
In regard to claim 9, Chandrasekaran as modified discloses (Figs. 3-6) further comprising: a DC link capacitor (CH) configured to smooth an output voltage of the rectifier (Vout); and a power factor correction (PFC) converter including at least two legs connected in parallel to the DC link capacitor (Fig. 3: each leg including a switch and an inductor Lb1 &SA1 and Lb2 and SA2 are in parallel to the output capacitor CH) , wherein one of the at least two legs includes the first switch and another one of the at least two legs includes the second switch (SA1 and SA2) , and wherein the at least one processor (parag. 0039) is further configured to randomly select at least one of the at least two legs and turn on/off the first switch or the second switch included in the randomly-selected at least one leg based on a pulse width modulation (PWM) switching signal (the duty-cycle controller 340 to produce a gate-drive signal GD1 and GS2 to control/(ON and off) the first main power switch S.sub.A1 and S.sub.A2, see prag. 0025 and 0028-0029. Furthermore, Park discloses frequency pulse width modulation (PWM) signals to turn on/off the first and second switches, thus controlling the intensity of the LED module, see abstract) .
In regard to claim 10, Chandrasekaran as modified discloses (Figs. 3-6) further comprising: a DC link capacitor (CH) configured to smooth an output voltage of the rectifier (Vout); and a power factor correction (PFC) converter including at least two legs connected in parallel to the DC link capacitor (Fig. 3: each leg including a switch and an inductor Lb1 &SA1 and Lb2 and SA2 are in parallel to the output capacitor CH) , wherein one of the at least two legs includes the first switch and another one of the at least two legs includes the second switch (SA1 and SA2) and wherein the at least one processor is further configured to sequentially select the at least two legs and turn on/off the first switch or the second switch included in the selected at least one leg among the at least two legs based on a PWM switching signal (the duty-cycle controller 340 to produce a gate-drive signal GD1 and GS2 to control the first main power switch S.sub.A1 and S.sub.A2, see prag. 0025 and 0028-0029. Furthermore, Park discloses frequency pulse width modulation (PWM) signals to turn on/off the first and second switches, thus controlling the intensity of the LED module, see abstract) .
In regard to claim 10, Chandrasekaran as modified discloses (Figs. 3-6) wherein the at least one processor (parag. 0039) is further configured to sample the first current and the second current (see parag. 0025 and Paragraphs 0027-0029 ) filtered by the low pass filter once per switching cycles of the first switch and the second switch by sampling the first current and the second current at any point in the switching cycles (see parag. 0025 and Paragraphs 0027-0029. Furthermore, Park discloses the first and second current is filtered by LPF 19 and 21 ) .
In regard to claim 12, Chandrasekaran as modified discloses (Figs. 3-6) wherein a cutoff frequency of the low pass filter is set to be 1/10 or less of a switching frequency of the first switch or the second switch (Park discloses a low-pass filters (19 and 21) are an electronic circuit or signal processing tool that allows signals with frequencies below a chosen cutoff frequency to pass through while blocking or reducing higher-frequency signals. Examiner noted that the a cutoff frequency of the low pass filter is set to be 1/10 or less of a switching frequency of the first switch or the second switch based upon a design needs / intended purpose for specific reason or goal for acquiring a desired outcome . Therefore, any skilled person designing the circuit of “ Fig. 3” would have to exercise a routine experiment to get the cut off frequency , thereby arriving to the subject matter of claim 10).
In regard to claim 13, Chandrasekaran as modified discloses (Figs. 3-6) further comprising a direct current (DC) link capacitor (CH) configured to smooth an output voltage of the rectifier (Vout) , wherein at least a portion of the rectifier (350) comprises a switching device (SA1 and SA2), wherein the at least one processor (see parag. 0039) is further configured to control the switching device of the rectifier to gradually increase a size of a charge voltage charged into the DC link capacitor when a system including the power control device operates ( see parg. 0022, 0024) .
In regard to claim 14, Chandrasekaran as modified discloses (Figs. 3-6) wherein at least a portion of the switching device of the rectifier comprises a thyristor(four-diode bridge 350. Examiner noted that rectifier comprises a thyristor a design needs / intended purpose for specific reason or goal for acquiring a desired outcome ).
In regard to claim 15 , A power control method of a power control device (Figs. 3 and 5 ; controller 310/510 are used for power converter formed with two interleaved boost switching regulators , see paragraphs 23-28), comprising: rectifying, by a rectifier of the power control device (Figure 3, rectifier 350; see paragraphs 23-28), an input current of a system comprising the power control device (Figure 3, input current from the ac power source providing an input voltage VIN; Paragraph 23);
; sensing, by a current sensor of the power control device (Figure 3, first current sensor resistors R1 and R2; Paragraphs 23-28), a first current through a first switch (first switch SA1) and a second current through a second switch (second switch (SA2)), wherein the first switch and the second switch are connected to an output of the rectifier (first and second switches (SA1 and SA2) are connected to 350);
sampling, by at least one processor of the power control device (see prag. 0039) , the filtered first current and the filtered second current once per switching cycles of the first switch and the second switch; and performing balancing control based on the sampled first current and the sampled second current such that an average value of the first current through the first switch and the second current through the second switch is uniform or is substantially uniform for a period (Figures 3-4; Paragraphs 27-29, current balancing is achieved by comparing the current samples from the two interleaved boost switching regulators. Average currents are obtained by sampling currents in the first and second main power switches SA₁ and SA₂ at their respective mid-points of their ON durations) but fails to discloses filtering the sensed first current sensor and the current sensed by the second current sensor through a low pass filter.
Whereas , Park discloses filtering the sensed first current sensor and the current sensed by the second current sensor through a low pass filter (Figs. 2 and 5 shows current sensing Rsense1 and Rsense2 are configured to sense a current flowing thru switches SW1 and SW2 and first and second low-pass filters 19 and 21 are coupled to Rsense1 and 2 and sensing voltage is passed through a low-pass filter 19 and 21 (equivalent to LPF) to eliminating switching noise and digital signal processor 23 receives the filtering current input through the first and second low-pass filters 19 and 21 and compares the filtered current with the reference rated current (S503). see abstract , pages 3 ,lines 15-36 and page 4, lines 1-25.
Therefore, it would have been obvious to one of ordinary skilled in the art before the effective filing date of the claimed invention to have modified the power control device of Chandrasekaran to include LPF as taught by Park because eliminating switching noise /noise reduction and creates smoothing signal data which improve the reliability and efficiency of the converter.
Allowable Subject Matter
7. Claim 6-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter.
Claim 6 is objected because the prior art of record fails to disclose or suggest the controller circuit including the limitation of “an input current sensor configured to detect the input current, wherein the at least one processor is further configured to: obtain a harmonic component from the input current detected by the input current sensor, determine a non-conducting period size of the first switch and the second switch such that the obtained harmonic component is less than a harmonic reference value, and generate a current command value corresponding to the determined non-conducting period size.”
Claims 7-8 are dependent on claim 6, thus are objected because of their dependency.
Conclusion
8. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhang “10141848” the present disclosure relates to field of circuit technology, and more particularly, to an interleaved power factor corrector.
Tan “20220158545” the present invention relates to self-tuning regulators for interleaved power factor correction (PFC) circuits and devices. More specifically, the present invention relates to self-tuning regulators that counteract inaccuracy and characteristic drift of sampling circuits to enhance current sharing performance in PFC circuits.
Terui “10038366” the present invention disclosure relates to a multiphase power factor improvement circuit such as an interleaved converter.
Bernardinis “201301948486” the invention generally relate to interleaved circuits and, more particularly, to balancing current in circuits having interleaved phases.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SISAY G TIKU whose telephone number is (571)272-6898. The examiner can normally be reached 8:30AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal L Hammond can be reached at (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SISAY G TIKU/
Primary Examiner, Art Unit 2838
Prosecution Insights