DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
1. Claims 1-2 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Lee et al (USPN 2019/0098404).
Regarding claim 1, Lee discloses an integrated circuit (an integrated circuit 1310), comprising:
an external signal node (such as node P1) connected to receive an injected current (such as current Lout);
an output buffer (an output driver 150, see figure 6) comprising a first output stage (a first stage includes T1, T2) connected between a first voltage supply (VDD2) and the external signal node (the node P1); and
a current injection protection circuit (100 200) comprising:
a first comparator (a first comparator 211) configured to generate a first current injection control signal (a first control signal C1) by comparing the first voltage supply to a first overvoltage signal (such as a first overvoltage signal generated at a node DV associates with the comparator 211) generated from a voltage on the external signal node; and
a multiplex selection circuit (a multiplexer 250) comprising a first input connected to receive a first gate control signal (such as OVD signal) that is generated from the first current injection control signal (the control signal C1), a second input connected to receive a first pre-driver signal (such as cOVD signal configured to control operations of the driver 150 via the multiplexer 250, see par. 0111-0112), and an output (an output of the multiplexer 250) connected to a control gate terminal of the output buffer (T1, T2) (via a switch SW5) which clamps the external signal node (P1) to the first supply voltage if the voltage on the external signal node passes a trip threshold of the first comparator (the switch SW5 configured to turn on due to the overvoltage signal OVD and voltage at the out put node P1 is clamped) (see par. 0145, and figures 9, 11).
Regarding claim 2, Lee discloses an excursion limiter circuit (a limiter circuit include a divider RD1, RD2 shown in figure 6) connected to the external signal node (P1) to generate the first overvoltage signal (the first overvoltage signal at the node DV associates with the first comparator 211).
Allowable Subject Matter
2. Claims 9-20 are allowed over prior art of record.
The following is an examiner's statement of reasons for allowance:
The prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach:
A method for controlling I/O pad voltage excursions past a reference voltage that are caused by current injection fault, comprising: selectively supplying a first pair of pre driver gate control signals to an output buffer during normal operation, where the output buffer is connected to drive an I/O pad between a first reference voltage and a second reference voltage during normal operation; detecting a current injection event which causes an I/O pad voltage excursion past either the first or second reference voltages; selectively supplying a second pair of pre driver gate control signals to the output buffer in response to the detected current injection event, where the output buffer is connected to clamp the I/O pad voltage to a first clamped voltage within approximately one volt of whichever of the first reference voltage or second reference voltage which experienced the I/O pad voltage excursion during the detected current injection event as recited in claim 9.
An electronic device, comprising: said protection circuit comprising: one or more first pre-driver circuits connected and configured to generate first pre-driver gate control signals during normal operation; one or more current injection detector circuits connected and configured to generate second pre-driver gate control signals in response to detecting a current injection event at the I/O pad; and one or more multiplexer selection circuits connected and configured to supply the first pre-driver gate control signals to the output driver during normal operation, and to supply the second pre-driver gate control signals to the output driver during normal operation, where the output driver is connected to clamp the I/O pad voltage to a first clamped voltage within approximately one volt of the first reference voltage during the detected current injection event as recited in claim 16.
3. Claims 3-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANNY NGUYEN whose telephone number is (571)272-2054. The examiner can normally be reached M-F 8:00AM-4:30PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at 571-271-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANNY NGUYEN/ Primary Examiner, Art Unit 2838
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