DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present Office Action is in response to Applicant Arguments/Remarks and amended claims filed on 04/20/2026. Claims 1, 9, 15, and 17 have been amended. Claims 1-20 remain pending in the application.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 9 is objected to because of the following informalities: there is an extra “A” at the beginning of the claim language that needs to be removed.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 9, and 17 recites the limitation “the data structure … comprising unique criteria for inbound and outbound notifications of the network adapter”, which can be interpreted in more than one way. The limitation can be interpreted as 1) criteria that uniquely distinguish inbound notifications and outbound notifications of a particular network adapter (from another network adapter), 2) criteria that are unique for a set/group of inbound/outbound notifications, or 3) criteria that uniquely distinguish inbound from outbound notifications. Since the example of criteria used in specification are “packet counts, packet arrival rates, and timers for packet blocking parameters”, for the purpose of examination, the Examiner has interpreted the limitation as 2), unique packet parameters that categorizes inbound and outbound messages.
Claims 2-8, 10-16, and 18-20 are depending on claims 1, 9, and 17 respectively and the dependent claims are rejected for the same reason as they do not cure the deficiencies set forth above.
Response to Amendments and Arguments
Applicant’s amendments and remarks have been fully considered, with the Examiner’s response set forth below.
(1)Applicant contends that, regarding claim 1, the combination of Pardo, Toivanen, Blackmore, and Bogin does not disclose the amended limitation “the data structure being configured by firmware associated with the network adapter and comprising unique criteria for inbound and outbound notifications of the network adapter”. The Examiner respectfully disagree.
Pardo teaches a network adapter (NIC 26) comprises a prediction logic 56 which includes firmware ([0027]). The prediction logic 56 configures the data structure associated with completion packet. Inbound messages can be categorized based on packet header information. Blackmore discloses both inbound and outbound messages including packet header information. Therefore, the combination of Pardo and Blackmore teaches the above amended limitation. See claim analysis for claims 1, 9, and 17 below for details.
(2) The rest of Applicant’s arguments are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
(3) Another iteration of claim analysis has been made. Refer to the corresponding sections of the claim analysis below for details.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 9, 10, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pardo et al. (US2021/0073130), hereinafter Pardo in view of Toivanen (US 2019/0324912), hereinafter Toivanen, and further in view of Blackmore et al. (US 2006/0075067), hereinafter Blackmore and Bogin et al. (US6,523,093), hereinafter Bogin.
Regarding claim 1, Pardo teaches a method of adapter snooping in hardware using a split structure cache, the method comprising:
receiving, by a hardware snooping module (Pardo, [0030], prediction logic 56 typically sniffs and analyzes data transactions on bus 28), a completion packet (Pardo, [0002], the completion report takes the form of a data structure known as a completion queue element (CQE), which the NIC writes to a completion queue in the memory) from a network adapter (network interface controller) (Pardo, [0007], the peripheral device includes a network interface controller (NIC), and the data items include data packets that are received by the NIC from a network; [0032], CQE write sniffer process 70 is applied by prediction logic 56 in detecting and tracking DMA transactions on bus 28 in which NIC 26 writes CQEs 48 to completion queue 50);
storing, by the hardware snooping module, a data structure associated with the completion packet in a split structure cache included within the hardware snooping module (Pardo, [0028], For purposes of identifying addresses 52 of context metadata 54 that are associated with each CQE, prediction logic 56 maintains a CQE table 58 … address tracking table 62, Fig.1), the data structure being configured by firmware associated with the network adapter (Pardo, [0026], NIC 26 comprises prediction logic 56; [0027], prediction logic 56 may comprise an embedded microcontroller, which performs these functions under the control of suitable software or firmware) and comprising unique criteria (packet category) for inbound and outbound notifications of the network adapter (Pardo, [0023]-[0024]; [0025], by reading the CQE, the software is able to categorize the data packet to which it corresponds (for example on the basis of packet address information and/or other packet header fields). Based on the packet category, the software identifies context metadata 54 at one or more addresses 52 in memory 24 for use in processing packet data 44; [0028], Packet processing circuitry 42 assigns a context ID to each CQE depending on the category to which the corresponding data packet belongs; [0042]);
performing, by the hardware snooping module, a hardware snoop on the data structure (Pardo, [0030], prediction logic 56 typically sniffs and analyzes data transactions on bus 28, including memory read operations performed by CPU 22, as well as write operations performed by NIC 26 in writing CQEs 48 to completion queue 50; [0038]), including updating the data structure based on the completion packet (Pardo, [0028], Packet processing circuitry 42 assigns a context ID to each CQE depending on the category to which the corresponding data packet belongs … Each context ID 60 in turn points to an entry 64 in an address tracking table 62, where prediction logic 56 writes addresses 52 of context metadata 54 that are associated with CQEs 48 having this context ID.), wherein the hardware snooping module is configured to determine whether to interrupt firmware based on the hardware snoop of the data structure; and
sending, by the hardware snooping module, the updated data structure to system memory.
Pardo teaches a cache storing a data structure, nevertheless, Pardo does not explicitly teach the cache is a split structure cache, as claimed. Pardo also does not explicitly teach outbound notifications; wherein the hardware snooping module is configured to determine whether to interrupt firmware based on the hardware snoop of the data structure; and sending, by the hardware snooping module, the updated data structure to system memory, as claimed.
However, Pardo in view of Toivanen teaches a split structure cache (Toivanen, abstract, A device including a cache memory that is partitioned into at least a first partition and a second partition. The first partition and the second partition are distinguishable by memory addresses; [0032]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Pardo to incorporate teachings of Toivanen to include a cache with multiple independent partitions. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Pardo with Toivanen because it improves performance of the storage system disclosed in Pardo by allowing parallel access to different partitions of a cache memory.
The combination of Pardo does not explicitly teach outbound notifications; wherein the hardware snooping module is configured to determine whether to interrupt firmware based on the hardware snoop of the data structure; sending, by the hardware snooping module, the updated data structure to system memory, as claimed.
However, the combination of Pardo in view of Blackmore teaches the data structure … comprising unique criteria for inbound and outbound notifications of the network adapter (Blackmore, [0081]; [0083]; [0098]; [0274]);
wherein the hardware snooping module is configured to determine whether to interrupt firmware based on the hardware snoop of the data structure (Pardo, [0040], Once the count value has reached the list size, prediction logic sets valid flag 66 for this context ID 60 in address tracking table 62, and the process terminates; Blackmore, [0083], Interrupts are based on the FIFO queue count threshold for the given adapter window).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Pardo to incorporate teachings of Blackmore to include unique criteria for outbound notifications as well as inbound notifications and send an interrupt message in response to the count value (in Pardo) has reached the list size when the process is terminated. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Pardo with Blackmore because the it improves communication of the storage system disclosed in the combination of Pardo by providing notifications when specific events have occurred.
The combination of Pardo does not explicitly teach sending, by the hardware snooping module, the updated data structure to system memory, as claimed.
However, the combination of Pardo in view of Bogin teaches sending, by the hardware snooping module, the updated data structure to system memory (Bogin, col.6, line 55 – col.7, line 15, the write data residing in the write cache 210 is flushed out to the main memory. For example, if a watermark in the write cache 210 indicates that more than a defined number of entries in the write cache are occupied with write data, this causes the write data, destined for the memory controller 128, to be flushed to the flush queue (FQ) 212. ).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Pardo to incorporate teachings of Bogin to write buffered data back in a main memory when the size of data stored in a buffer exceeds a threshold, such as the buffer memory in prediction logic 56. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Pardo with Bogin because it improves efficiency of the storage system disclosed in the combination of Pardo by allowing a cache to maintain sufficient memory space to store most frequently accessed data.
Regarding claim 2, the combination of Pardo teaches all the features with respect to claim 1 as outlined above. The combination of Pardo further teaches the method of claim 1, wherein the split structure cache includes a first SRAM (static random-access memory) and a second SRAM (Toivanen, [0029], In one embodiment, the cache 220 may include a static random access memory (SRAM) device and/or other volatile or non-volatile memory devices.).
Regarding claims 9 and 17, taking claim 17 as exemplary, Pardo teaches a system for adapter snooping in hardware using a split structure cache, the system comprising:
a system memory (Pardo, [0022], system memory 24; Fig.1, see memory 24);
a network adapter (Pardo, [0002], network interface controller (NIC); Fig.1, see NIC 26);
a firmware (Pardo, [0027], prediction logic 56 may comprise an embedded microcontroller, which performs these functions under the control of suitable software or firmware); and
a hardware snooping module (Pardo, Fig.1, prediction logic 56) comprising:
a split structure cache comprising a first memory (Pardo, Fig.1, see memory storing tables 58 and table 62) and a second memory; and
a snooping controller configured to:
receive a completion packet from the network adapter (Pardo, [0002], the completion report takes the form of a data structure known as a completion queue element (CQE), which the NIC writes to a completion queue in the memory; [0032], CQE write sniffer process 70 is applied by prediction logic 56 in detecting and tracking DMA transactions on bus 28 in which NIC 26 writes CQEs 48 to completion queue 50);
store a data structure associated with the completion packet in the split structure cache (Pardo, [0028], For purposes of identifying addresses 52 of context metadata 54 that are associated with each CQE, prediction logic 56 maintains a CQE table 58 … address tracking table 62, Fig.1), the data structure being configured by firmware associated with the network adapter (Pardo, [0026], NIC 26 comprises prediction logic 56; [0027], prediction logic 56 may comprise an embedded microcontroller, which performs these functions under the control of suitable software or firmware) and comprising unique criteria (packet category) for inbound and outbound notifications of the network adapter (Pardo, [0023]-[0024]; [0025], by reading the CQE, the software is able to categorize the data packet to which it corresponds (for example on the basis of packet address information and/or other packet header fields). Based on the packet category, the software identifies context metadata 54 at one or more addresses 52 in memory 24 for use in processing packet data 44; [0028], Packet processing circuitry 42 assigns a context ID to each CQE depending on the category to which the corresponding data packet belongs; [0042]);
perform a hardware snoop on the data structure (Pardo, [0030], prediction logic 56 typically sniffs and analyzes data transactions on bus 28, including memory read operations performed by CPU 22, as well as write operations performed by NIC 26 in writing CQEs 48 to completion queue 50; [0038]), including updating the data structure based on the completion packet (Pardo, [0028], Packet processing circuitry 42 assigns a context ID to each CQE depending on the category to which the corresponding data packet belongs … Each context ID 60 in turn points to an entry 64 in an address tracking table 62, where prediction logic 56 writes addresses 52 of context metadata 54 that are associated with CQEs 48 having this context ID); and
send the updated data structure to the system memory.
Pardo teaches a cache storing a data structure, nevertheless, Pardo does not explicitly teach outbound notifications; the cache is a split structure cache comprising a first memory and a second memory, as claimed. Pardo also does not explicitly teach send the updated data structure to the system memory, as claimed.
However, Pardo in view of Toivanen teaches a split structure cache (Toivanen, abstract, A device including a cache memory that is partitioned into at least a first partition and a second partition. The first partition and the second partition are distinguishable by memory addresses; [0032]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Pardo to incorporate teachings of Toivanen to include a cache with multiple independent partitions. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Pardo with Toivanen because it improves performance of the storage system disclosed in Pardo by allowing parallel access to different partitions of a cache memory.
The combination of Pardo does not explicitly teach outbound notifications and send the updated data structure to the system memory, as claimed.
However, the combination of Pardo in view of Blackmore teaches the data structure … comprising unique criteria for inbound and outbound notifications of the network adapter (Blackmore, [0081]; [0083]; [0098]; [0274]);
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Pardo in view of Blackmore to include unique criteria for outbound notifications as well as inbound notifications. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Pardo with Blackmore because network traffic includes both incoming and outgoing I/O messages.
The combination of Pardo does not explicitly teach send the updated data structure to the system memory, as claimed.
However, the combination of Pardo in view of Bogin teaches send the updated data structure to the system memory (Bogin, col.6, line 55 – col.7, line 15, the write data residing in the write cache 210 is flushed out to the main memory. For example, if a watermark in the write cache 210 indicates that more than a defined number of entries in the write cache are occupied with write data, this causes the write data, destined for the memory controller 128, to be flushed to the flush queue (FQ) 212. ).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Pardo to incorporate teachings of Bogin to write buffered data back in a main memory when the size of data stored in a buffer exceeds a threshold, such as the buffer memory in prediction logic 56. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Pardo with Bogin because it improves efficiency of the storage system disclosed in the combination of Pardo by allowing a cache to maintain sufficient memory space to store most frequently accessed data.
Claim 9 has similar limitations as claim 17 and is rejected for the similar reasons.
Regarding claim 10, the claim has similar limitations as claim 2 and is rejected for the similar reasons.
Claim(s) 3, 11, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Pardo, Toivanen, Blackmore, and Bogin as applied to claims 2, 10, and 17 respectively above, and further in view of Ajanovic et al. (US 7,899,943), hereinafter Ajanovic.
Regarding claims 3, 11, and 19, taking claim 3 as exemplary, the combination of Pardo teaches all the features with respect to claim 2 as outlined above. The combination of Pardo does not explicitly teach the method of claim 2, wherein the data structure includes a software portion and a hardware portion, and wherein storing the data structure in the split structure cache includes storing the software portion of the data structure in the first SRAM and storing the hardware portion of the data structure in the second SRAM, as claimed.
However, the combination of Pardo in view of Ajanovic teaches the method of claim 2, wherein the data structure includes a software portion (Pardo, [0030], address tracking table 62; [0028], Each entry 64 contains a valid flag 66, which is set to indicate that the entry is complete and up to date) and a hardware portion (Pardo, [0030], CQE table 58; Ajanovic, claim 11, the completion packet to include a requestor identifier (ID) associated with the request packet, a completer ID associated with the device that performed the RMW operation, and an old value of the memory location read as part of the RMW operation; col.3, line 64 – col.4, line 8, Device 125 includes any internal or external device or component to be coupled to an electronic system, such as an I/O device, a Network Interface Controller (NIC), an add-in card, an audio processor, a network processor, a hard-drive, a storage device, a CD/DVD ROM, a monitor, a printer, a mouse, a keyboard, a router, a portable storage device, a Firewire device, a Universal Serial Bus (USB) device, a scanner, and other input/output devices; Note – devices are hardware), and wherein storing the data structure in the split structure cache includes storing the software portion of the data structure in the first SRAM and storing the hardware portion of the data structure in the second SRAM (Toivanen, [0029], In one embodiment, the cache 220 may include a static random access memory (SRAM) device and/or other volatile or non-volatile memory devices; Pardo, Fig.1, prediction logic includes two table and two SRAM. As such, each SRAM stores one of the tables.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Pardo to incorporate teachings of Ajanovic to include hardware information in completion packet. As such, the CQE table stored in a SRAM contains hardware information while the address tracking table contains software information. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Pardo with Ajanovic because it improves communication and performance of the storage system disclosed in Pardo by including information, such as status and metadata, about specific requests/commands.
Claims 11 and 19 have similar limitations as claim 3 and they are rejected for the similar reasons.
Claim(s) 4 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Pardo, Toivanen, Blackmore, and Bogin as applied to claims 1 and 9 respectively above, and further in view of Marolia et al. (US2019/0297015), hereinafter Marolia.
Regarding claim 4, the combination of Pardo teaches all the features with respect to claim 1 as outlined above. The combination of Pardo does not explicitly teach the method of claim 1, wherein storing the data structure includes: sending, by the hardware snooping module, a request to the system memory for the data structure corresponding with the completion packet; receiving, by the hardware snooping module in response to the request, the data structure from the system memory; and storing, by the hardware snooping module, the data structure in the split structure cache, as claimed.
However, the combination of Pardo in view of Marolia teaches the method of claim 1, wherein storing the data structure includes: sending, by the hardware snooping module, a request to the system memory for the data structure corresponding with the completion packet; receiving, by the hardware snooping module in response to the request, the data structure from the system memory; and storing, by the hardware snooping module, the data structure in the split structure cache (Marolia, [0028], device may implement an address translation cache (ATC) that keeps a copy of the translated physical address. If a cached copy of the translated address is not available, then network interface 250 generates an address translation request via the primary head to get a translated address … a PCIe compatible address translation unit (ATU) can return Host physical address (HPA) to network interface 250. Network interface 250 receives an HPA from an IOMMU; [0042], Some examples use an Address Translation cache to keep a copy of the translated address locally within cache 314; [0044], the translated address is provided as a response for storage as a pair of destination address and translated address is stored in address translation cache 314; Fig.3C, see Address Trans Cache 314 resides in network interface controller (NIC)).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Pardo to incorporate teachings of Marolia to include an address translation cache in a network interface controller to provide address translation for completion queue entry (CQE). A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Pardo with Marolia because it improves efficiency and performance of the storage system disclosed in the combination of Pardo by reducing cost/latency of address translation (Marolia, [0028]).
Claim 12 has similar limitations as claim 4 and is rejected for the similar reasons.
Claim(s) 5, 13, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Pardo, Toivanen, Blackmore, and Bogin as applied to claims 1, 9, and 17 respectively above, and further in view of Emmes et al. (US2006/0095606), hereinafter Emmes.
Regarding claims 5, 13, and 20, taking claim 5 as exemplary, the combination of Pardo teaches all the features with respect to claim 1 as outlined above. The combination of Pardo does not explicitly teach the method of claim 1, wherein updating the data structure includes: finding a most up to date version of the data structure; and updating the most up to date version of the data structure based on the completion packet, as claimed.
However, the combination of Pardo in view of Emmes teaches the method of claim 1, wherein updating the data structure includes: finding a most up to date version of the data structure (Emmes, Fig.5); and updating the most up to date version of the data structure based on the completion packet (Emmes, [0095], Increment current CQ Use Count 524 in new version).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Pardo to incorporate teachings of Emmes to update a most up to date version of data structure based on a completion queue entry. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Pardo with Emmes because it improves reliability of the storage system disclosed in the combination of Pardo by using the most up to date version of data during storage operations.
Claims 13 and 20 have similar limitations as claim 5 and they are rejected for the similar reasons.
Claim(s) 6 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Pardo, Toivanen, Blackmore, and Bogin as applied to claims 1 and 9 respectively above, and further in view of Desai et al. (US 2005/0027945), hereinafter Desai.
Regarding claims 6 and 14, taking claim 6 as exemplary, the combination of Pardo teaches all the features with respect to claim 1 as outlined above. The combination of Pardo does not explicitly teach the method of claim 1, wherein sending the updated data structure to the system memory includes: copying, by the hardware snooping module, the updated data structure from the split structure cache to an output buffer included within the hardware snooping module; and sending, by the hardware snooping module from the output buffer, the updated data structure to the system memory, wherein the system memory is coherent with the split structure cache, as claimed.
However, the combination of Pardo in view of Desai teaches the method of claim 1, wherein sending the updated data structure to the system memory includes: copying, by the hardware snooping module, the updated data structure from the split structure cache to an output buffer included within the hardware snooping module; and sending, by the hardware snooping module from the output buffer, the updated data structure to the system memory, wherein the system memory is coherent with the split structure cache (Desai, [0033], Similarly a write-back queue 306 may be used to move a cache line from the L2 cache 204 b to the main memory 110 when the cache line is being victimized in the L2 cache 204 b.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Pardo to incorporate teachings of Desai to include a write-back queue in NIC 26 (of Pardo) such that entries from CQE table 58 and table 62 can be copied to the write-back queue and transmitted to main memory. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Pardo with Desai because it improves efficiency of the storage system disclosed in the combination of Pardo by allowing cache data to be written back from a cache to a main memory via a queue.
Claim 14 has similar limitations as claim 6 and is rejected for the similar reasons.
Claim(s) 7 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Pardo, Toivanen, Blackmore, and Bogin as applied to claims 1 and 15 respectively above, and further in view of Zheng et al. (US 2025/0036453), hereinafter Zheng.
Regarding claims 7 and 16, taking claim 7 as exemplary, the combination of Pardo teaches all the features with respect to claim 1 as outlined above. The combination of Pardo does not explicitly teach the method of claim 1, further comprising, responsive to determining, by the hardware snooping module and based on the hardware snoop, to interrupt the firmware: sending hardware snoop information associated with the hardware snoop to a firmware trigger queue included within the hardware snooping module; and sending, from the firmware trigger queue, an interrupt to the firmware, as claimed.
However, the combination of Pardo in view of Zheng teaches the method of claim 1, further comprising, responsive to determining, by the hardware snooping module and based on the hardware snoop, to interrupt the firmware: sending hardware snoop information associated with the hardware snoop to a firmware trigger queue included within the hardware snooping module; and sending, from the firmware trigger queue, an interrupt to the firmware (Zheng, [0041]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Pardo to incorporate teachings of Zheng to include an event queue in a network interface controller to store interrupt messages to be issued to a firmware. A person of ordinary skill in the art would have been motivated to combine the teachings of Pardo with Zheng because it improves efficiency of the storage system disclosed in the combination of Pardo by streamlining the storing and issuing of interrupt messages.
Claim 16 has similar limitations as claim 7 and is rejected for the similar reasons.
Claim(s) 8 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Pardo, Toivanen, Blackmore, and Bogin as applied to claims 2 and 17 respectively above, and further in view of Cochell et al. (US 11,055,106), hereinafter Cochell.
Regarding claims 8 and 18, taking claim 8 as exemplary, the combination of Pardo teaches all the features with respect to claim 1 as outlined above. The combination of Pardo does not explicitly teach the method of claim 1, wherein the network adapter is a PCIe adapter, as claimed.
However, the combination of Pardo in view of Cochell teaches the method of claim 1, wherein the network adapter is a PCIe adapter (Cochell, col.6, lines 48-53, the I/O interface 128 through which host computer 102 communicates with NIC 104 is a PCIe adapter. ).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Pardo to incorporate teachings of Cochell to including a PCIe adapter in an network interface controller. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Pardo because it improves performance of the storage system disclosed in the combination of Pardo as PCIe allows for faster data transfer speeds.
Claim 18 has similar limitations as claim 8 and is rejected for the similar reasons.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Pardo, Toivanen, Blackmore, and Bogin as applied to claim 9 above, and further in view of Blackmore et al. (US 2006/0075067), hereinafter Blackmore.
Regarding claim 15, the combination of Pardo teaches all the features with respect to claim 9 as outlined above. The combination of Pardo does not explicitly teach the apparatus of claim 9, wherein the snooping controller is further configured to determine whether to interrupt the firmware based on the hardware snoop of the data structure, as claimed.
However, the combination of Pardo in view of Blackmore teaches the apparatus of claim 9, wherein the snooping controller is further configured to determine whether to interrupt the firmware based on the hardware snoop of the data structure (Pardo, [0040], Once the count value has reached the list size, prediction logic sets valid flag 66 for this context ID 60 in address tracking table 62, and the process terminates; Blackmore, [0083], Interrupts are based on the FIFO queue count threshold for the given adapter window).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Pardo to incorporate teachings of Blackmore to send an interrupt message in response to the count value (in Pardo) has reached the list size and the process is terminated. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Pardo with Blackmore because the it improves communication of the storage system disclosed in the combination of Pardo by providing notifications when specific events have occurred.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hayut et al. (US2014/0143454) teaches a network interface controller comprises a CQE cache storing completion queue entries.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NANCI N WONG/ Primary Examiner, Art Unit 2137
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