DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6, 11-28 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Zeng et al. (US 20230021750, hereinafter “Zeng”) and further in view of Wang et al. (US 20190158133, hereinafter “Wang”).
Regarding claim 1, Zeng discloses,
An apparatus (Referring to FIG. 1, an electronic paper display apparatus 100 of this embodiment includes a radio frequency rectifier circuit 110, a driver circuit 120, and an electronic paper display panel 130 [0029]) comprising:
a plurality of detectors including at least a first passive detector and a second passive detector coupled to the first passive envelope detector (Referring to FIGS. 4A and 4B, a power stage 610 of this embodiment includes a first end A, a second end B, and a third end C. The first end A of the power stage 610 is coupled to a previous-stage switch circuit (a first switch circuit). The second end B of the power stage 610 is coupled to a next-stage switch circuit (a second switch circuit). The third end C of the power stage 610 is coupled to the radio frequency signal VRF [0034]; 0044] Table 1 shows the corresponding relationship between the output voltage values and the equivalent stage numbers according to the embodiment of FIG. 6: In Table 1, a radio frequency signal with higher energy corresponds to a higher output voltage, and a higher output voltage corresponds to a smaller equivalent stage number, [0044]-[0047]); and
a plurality of switches configured to couple the first passive detector to the second passive detector as multiple stages in a first configuration (Referring to FIGS. 4A and 4B, a power stage 610 of this embodiment includes a first end A, a second end B, and a third end C. The first end A of the power stage 610 is coupled to a previous-stage switch circuit (a first switch circuit). The second end B of the power stage 610 is coupled to a next-stage switch circuit (a second switch circuit). The third end C of the power stage 610 is coupled to the radio frequency signal VRF. Taking the power stage 610_3 of FIG. 3 as an example, a first end of the power stage 610_3 is coupled to the previous-stage switch circuit 620_2. A second end of the power stage 610_3 is coupled to the next-stage switch circuit 620_3. A third end of the power stage 610_3 is coupled to the radio frequency signal VRF. The switch circuit 620_2 and the switch circuit 620_3 are two adjacent switch circuits [0034]-[0039] and [0050]-[0053]) and further configured to couple the first passive detector to the second passive detector as a single stage in a second configuration (the power stages 610_1 and 610_2 are configured in series; when the switch circuit 620_1 is not conducted, the power stages 610_1 and 610_2 are configured in parallel [0031]-[0032]; , the switch circuit 620 includes transmission gates 622, 624, and 626. The control signal SW and a control signal SWB are used to control the conduction status of the transmission gates 622, 624, and 626, and the control signal SWB is an inverted signal of the control signal SW. When the transmission gate 622 is conducted….the transmission gates 624 and 626 are conducted, so that two adjacent power stages coupled to the switch circuit 620 may be configured to be coupled in parallel [0039]-[0041).
However, Zheng does not explicitly disclose, a plurality of envelope detectors including at least a first passive envelope detector and a second passive envelope detector.
In the same field of endeavor, Wang discloses, a plurality of envelope detectors including at least a first passive envelope detector and a second passive envelope detector (The tunable passive pseudo-balun ED architecture 12a is a N-stage rectifier with the middle node connected to V.sub.CM (common mode voltage) and the bulk nodes connected to a tunable voltage, Vbulk, to set the bandwidth. As such, the baseband ac currents flow in opposite directions relative to ground to form a pseudo-differential output V.sub.out,p, V.sub.out,n [0046]-[0048]).
Therefore, it would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify Zheng by specifically providing a plurality of envelope detectors including at least a first passive envelope detector and a second passive envelope detector, as taught by Wang for the purpose of improves sensitivity and interferer rejection both the primary and secondary stages resonate at the same center frequency, providing filtering and performing the impedance transformation, which results in a passive voltage gain [0029].
Regarding clam 2, the combination of Zheng and Wang discloses everything claimed as applied above (see claim 1), further Zheng discloses, wherein the first passive envelope detector is coupled to the second passive envelope detector via a serial connection in the first configuration, and wherein the first passive envelope detector is coupled in parallel to the second passive envelope detector in the second configuration (the power stages 610_1 and 610_2 are configured in series; when the switch circuit 620_1 is not conducted, the power stages 610_1 and 610_2 are configured in parallel [0031]-[0032]; , the switch circuit 620 includes transmission gates 622, 624, and 626. The control signal SW and a control signal SWB are used to control the conduction status of the transmission gates 622, 624, and 626, and the control signal SWB is an inverted signal of the control signal SW. When the transmission gate 622 is conducted….the transmission gates 624 and 626 are conducted, so that two adjacent power stages coupled to the switch circuit 620 may be configured to be coupled in parallel [0039]-[0041]; , when the switch circuit 620_1 is conducted, the power stages 610_1 and 610_2 are configured in series; when the switch circuit 620_1 is not conducted, the power stages 610_1 and 610_2 are configured in parallel [0032]-[0034]).
Regarding clam 3, the combination of Zheng and Wang discloses everything claimed as applied above (see claim 1), further Zheng discloses, wherein the first passive envelope detector and the second passive envelope detector are configurable as a first two-stage envelope detector, and wherein the plurality of envelope detectors further include a third passive envelope detector and a fourth passive envelope detector that are configurable as a second two-stage envelope detector in parallel with the first two-stage envelope detector (the power stages 610_1 and 610_2 are configured in series; when the switch circuit 620_1 is not conducted, the power stages 610_1 and 610_2 are configured in parallel [0031]-[0032]; , the switch circuit 620 includes transmission gates 622, 624, and 626. The control signal SW and a control signal SWB are used to control the conduction status of the transmission gates 622, 624, and 626, and the control signal SWB is an inverted signal of the control signal SW. When the transmission gate 622 is conducted….the transmission gates 624 and 626 are conducted, so that two adjacent power stages coupled to the switch circuit 620 may be configured to be coupled in parallel [0039]-[0041]; , when the switch circuit 620_1 is conducted, the power stages 610_1 and 610_2 are configured in series; when the switch circuit 620_1 is not conducted, the power stages 610_1 and 610_2 are configured in parallel [0032]-[0034]).
Regarding clam 4, the combination of Zheng and Wang discloses everything claimed as applied above (see claim 1), in addition Wang discloses, wherein the first configuration is associated with a first data rate, and wherein the second configuration is associated with a second data rate that is different than the first data rate (To compare to prior work using direct envelope detection architecture with different data rate and therefore, baseband bandwidth, BW.sub.BB [0040]-[0042]; An envelope detector with a larger number of stages, N, requires large transistor widths and has a larger input capacitance to maintain a given output bandwidth, which limits transformer gain. Parasitic capacitance increases with transistor width, adding to the capacitive load at the output and requiring a decrease in output resistance [0046]-[0049]).
Regarding clam 5, the combination of Zheng and Wang discloses everything claimed as applied above (see claim 1), further Zheng discloses, wherein the first configuration is associated with a first gain, and wherein the second configuration is associated with a second gain that is different than the first gain (FIG. 4A illustrates a schematic block diagram of a power stage according to an embodiment of the disclosure. FIG. 4B illustrates a schematic circuit diagram of the power stage of the embodiment of FIG. 4A. Referring to FIGS. 4A and 4B, a power stage 610 of this embodiment includes a first end A, a second end B, and a third end C. The first end A of the power stage 610 is coupled to a previous-stage switch circuit (a first switch circuit). The second end B of the power stage 610 is coupled to a next-stage switch circuit (a second switch circuit). The third end C of the power stage 610 is coupled to the radio frequency signal VRF [0031]-0038]).
Regarding clam 6, the combination of Zheng and Wang discloses everything claimed as applied above (see claim 1), further Zheng discloses, wherein the first passive envelope detector and the second passive envelope detector each have a differential configuration, and wherein, in accordance with the differential configuration, at least the first passive envelope detector includes a first inverter and a second inverter that is cross-coupled to the first inverter (As shown in FIG. 5B, the switch circuit 620 includes transmission gates 622, 624, and 626. The control signal SW and a control signal SWB are used to control the conduction status of the transmission gates 622, 624, and 626, and the control signal SWB is an inverted signal of the control signal SW, Fig. 5A-5B and [0039]-[0042]).
Regarding clam 11, the combination of Zheng and Wang discloses everything claimed as applied above (see claim 1), further Zheng discloses, wherein the plurality of switches includes one or more of: a first switch coupled to an output of the first passive envelope detector and to an input of the second passive envelope detector; a second switch coupled to the first switch and to an output node of the plurality of envelope detectors; or a third switch coupled to the first switch and to a ground node of the plurality of envelope detectors (As shown in FIG. 5B, the switch circuit 620 includes transmission gates 622, 624, and 626. The control signal SW and a control signal SWB are used to control the conduction status of the transmission gates 622, 624, and 626, and the control signal SWB is an inverted signal of the control signal SW. When the transmission gate 622 is conducted, the transmission gates 624 and 626 are not conducted, so that two adjacent power stages coupled to the switch circuit 620 may be configured to be coupled in series [0039]-[0041]).
Regarding clam 12, the combination of Zheng and Wang discloses everything claimed as applied above (see claim 1), further Zheng discloses, an automatic gain control (AGC) circuit coupled to the plurality of switches (the controller circuit 114 maintains the power stages of the control rectifier circuit 112 at a configuration with the largest equivalent stage number to derive the most energy. For example, when the initial voltage of the output voltage VOUT is less than the first default value VREF1 (that is, curves 320 and 330), the controller circuit 114 controls all the switch circuits 620_1 to 620_5 to be conducted, so that the equivalent stage number of the power stages of the rectifier circuit 112 is 6 [0046]-[0048]).
Regarding clam 13, the combination of Zheng and Wang discloses everything claimed as applied above (see claim 12), further Zheng discloses, wherein the AGC circuit is configured to provide a plurality of control signals to the plurality of switches to select either the first configuration or the second configuration (the controller circuit 114 maintains the power stages of the control rectifier circuit 112 at a configuration with the largest equivalent stage number to derive the most energy. For example, when the initial voltage of the output voltage VOUT is less than the first default value VREF1 (that is, curves 320 and 330), the controller circuit 114 controls all the switch circuits 620_1 to 620_5 to be conducted, so that the equivalent stage number of the power stages of the rectifier circuit 112 is 6 [0046]-[0048]).
Regarding clam 14, the combination of Zheng and Wang discloses everything claimed as applied above (see claim 1), in addition Wang discloses, a wakeup circuit that includes the plurality of envelope detectors and the plurality of switches (Example wake-up receivers according to embodiments of the invention can provide, among other benefits, a highly networked environment where extremely low power (sub-uW) electronics are necessary for battery life and cost…To enable operation at higher frequencies without significantly compromising sensitivity or power consumption, an example embodiment of the invention provides a WuRX featuring an active pseudo-balun envelope detector (ED). The pseudo-balun envelop detector has higher input resistance, lower input capacitance, and higher conversion gain via a current re-use common gate (CG) architecture than the state-of-the-art discussed in the background, [0024]-[00227]).
Regarding clam 15, the combination of Zheng and Wang discloses everything claimed as applied above (see claim 14), in addition Wang discloses, an antenna coupled to the wakeup circuit and configured to receive a signal (A 400 MHz high-Q transformer 14 improves sensitivity and interferer rejection Both the primary and secondary stages resonate at the same center frequency, providing filtering and performing the impedance transformation, which results in a passive voltage gain, A.sub.V=18.5 dB [0029]); and a rectifier coupled to the wakeup circuit, wherein the rectifier is configured to generate harvested energy based at least in part on the signal (The tunable passive pseudo-balun ED architecture 12a is a N-stage rectifier with the middle node connected to V.sub.CM (common mode voltage) and the bulk nodes connected to a tunable voltage, Vbulk, to set the bandwidth. As such, the baseband ac currents flow in opposite directions relative to ground to form a pseudo-differential output V.sub.out,p, V.sub.out,n. Compared to a single-branch N-stage Dickson rectifier, this passive ED 12a achieves 2× conversion gain and a 1.5-dB sensitivity improvement under the same input signal level without sacrificing output bandwidth. Although the second branch (bottom half of rectifier 86) of the N-stage ED could be connected in parallel with the first branch (top half of rectifier 84) without flipping the polarity [0047]).
Regarding clam 16, the combination of Zheng and Wang discloses everything claimed as applied above (see claim 14), in addition Wang discloses, an ambient Internet-of-Things (IoT) device that includes the wakeup circuit (The high-power consumption of conventional wireless, e.g., radio, receivers often dictates the battery life of, for instance, small Internet of Things (IoT)-like devices [0024]).
Regarding claim 17, Zeng discloses,
A method (Referring to FIG. 1, an electronic paper display apparatus 100 of this embodiment includes a radio frequency rectifier circuit 110, a driver circuit 120, and an electronic paper display panel 130 [0029]) comprising:
receiving, at a plurality of detectors including a first passive detector and a second passive detector (Referring to FIGS. 4A and 4B, a power stage 610 of this embodiment includes a first end A, a second end B, and a third end C. The first end A of the power stage 610 is coupled to a previous-stage switch circuit (a first switch circuit). The second end B of the power stage 610 is coupled to a next-stage switch circuit (a second switch circuit). The third end C of the power stage 610 is coupled to the radio frequency signal VRF [0034]; 0044] Table 1 shows the corresponding relationship between the output voltage values and the equivalent stage numbers according to the embodiment of FIG. 6: In Table 1, a radio frequency signal with higher energy corresponds to a higher output voltage, and a higher output voltage corresponds to a smaller equivalent stage number, [0044]-[0047]), a plurality of control signals at a plurality of switches to select a configuration corresponding to one of a first configuration or a second configuration (The controller circuit 114 is coupled to the rectifier circuit 112. The controller circuit 114 is used to output a control signal Vctrl to control the conduction number of the switch circuits 620_1 to 620_5 according to the value of the output voltage VOUT. In this embodiment, the control signal Vctrl includes control signals SW1, SW2, SW3, SW4, and SW5, which are respectively used to control the conduction status of the switch circuits 620_1 to 620_5 [0032]), the first configuration configuring the first passive detector and the second passive detector as multiple stages (Referring to FIGS. 5A and 5B, a switch circuit 620 of this embodiment includes a first end D, a second end E, a third end F, and a control end. The first end D of the switch circuit 620 is coupled to a previous-stage power stage (a first power stage). The second end E of the switch circuit 620 is coupled to a next-stage power stage (a second power stage). The third end F of the switch circuit 620 is coupled to the output voltage VOUT of the rectifier circuit 112. The control end of the switch circuit 620 is coupled to a control signal SW [0039]-[0041]), the second configuration configuring the first passive detector and the second passive detector as a single stage (the power stages 610_1 and 610_2 are configured in series; when the switch circuit 620_1 is not conducted, the power stages 610_1 and 610_2 are configured in parallel [0031]-[0032]; , the switch circuit 620 includes transmission gates 622, 624, and 626. The control signal SW and a control signal SWB are used to control the conduction status of the transmission gates 622, 624, and 626, and the control signal SWB is an inverted signal of the control signal SW. When the transmission gate 622 is conducted….the transmission gates 624 and 626 are conducted, so that two adjacent power stages coupled to the switch circuit 620 may be configured to be coupled in parallel [0039]-[0041);
receiving, at the plurality of detectors, one or more voltages via one or more input nodes of the plurality of detectors ( When a previous-stage switch circuit is conducted, the power stage 610 receives an input voltage V1 via the first end A. The input voltage V1 is, for example, the voltage output by a previous-stage power stage [0035]-[0038]). However, However, Zheng does not explicitly disclose, a plurality of envelope detectors including at least a first passive envelope detector and a second passive envelope detector and generating, by the plurality of envelope detectors, a wakeup signal based on the one or more voltages and further based on the selected configuration.
In the same field of endeavor, Wang discloses, a plurality of envelope detectors including at least a first passive envelope detector and a second passive envelope detector (The tunable passive pseudo-balun ED architecture 12a is a N-stage rectifier with the middle node connected to V.sub.CM (common mode voltage) and the bulk nodes connected to a tunable voltage, Vbulk, to set the bandwidth. As such, the baseband ac currents flow in opposite directions relative to ground to form a pseudo-differential output V.sub.out,p, V.sub.out,n [0046]-[0048]) and generating, by the plurality of envelope detectors, a wakeup signal based on the one or more voltages and further based on the selected configuration (The high-power consumption of conventional wireless, e.g., radio, receivers often dictates the battery life of, for instance, small Internet of Things (IoT)-like devices. To reduce the power consumption of such devices and other devices, wake-up receivers (WuRXs) can be used to monitor the RF environment and wake-up a high-performance (and typically high power) conventional radio upon the reception of a predetermined wake-up packet [0024]; a direct envelope detection architecture is implemented where the RF signal is directly demodulated via the 2nd order non-linearity of an envelope detector [0027]; multiple sets of diode-connected transistors are configured in a cascade according to a Dickson charge-pump-like structure. The advantage of this approach is that power consumption is zero, and there is no 1/f noise since there are no DC bias currents. Vin is received at an input node 80, which is also connected to the second stage coil of the transformer filter. An envelope detector cell 82 provides the envelope function for the input signal [0047]) .
Therefore, it would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify Zheng by specifically providing a plurality of envelope detectors including at least a first passive envelope detector and a second passive envelope detector and generating, by the plurality of envelope detectors, a wakeup signal based on the one or more voltages and further based on the selected configuration, as taught by Wang for the purpose of improves sensitivity and interferer rejection both the primary and secondary stages resonate at the same center frequency, providing filtering and performing the impedance transformation, which results in a passive voltage gain [0029].
Regarding clam 18, the combination of Zheng and Wang discloses everything claimed as applied above (see claim 17), further Zheng discloses, the first passive envelope detector to the second passive envelope detector via a serial connection in the first configuration based on the plurality of control signals (the power stages 610_1 and 610_2 are configured in series; when the switch circuit 620_1 is not conducted, the power stages 610_1 and 610_2 are configured in parallel [0031]-[0032]; , the switch circuit 620 includes transmission gates 622, 624, and 626. The control signal SW and a control signal SWB are used to control the conduction status of the transmission gates 622, 624, and 626, and the control signal SWB is an inverted signal of the control signal SW. When the transmission gate 622 is conducted….the transmission gates 624 and 626 are conducted, so that two adjacent power stages coupled to the switch circuit 620 may be configured to be coupled in parallel [0039]-[0041]; , when the switch circuit 620_1 is conducted, the power stages 610_1 and 610_2 are configured in series; when the switch circuit 620_1 is not conducted, the power stages 610_1 and 610_2 are configured in parallel [0032]-[0034]).
Regarding clam 19, the combination of Zheng and Wang discloses everything claimed as applied above (see claim 17), further Zheng discloses, the first passive envelope detector in parallel to the second passive envelope detector in the second configuration based on the plurality of control signals (the power stages 610_1 and 610_2 are configured in series; when the switch circuit 620_1 is not conducted, the power stages 610_1 and 610_2 are configured in parallel [0031]-[0032]; , the switch circuit 620 includes transmission gates 622, 624, and 626. The control signal SW and a control signal SWB are used to control the conduction status of the transmission gates 622, 624, and 626, and the control signal SWB is an inverted signal of the control signal SW. When the transmission gate 622 is conducted….the transmission gates 624 and 626 are conducted, so that two adjacent power stages coupled to the switch circuit 620 may be configured to be coupled in parallel [0039]-[0041]; , when the switch circuit 620_1 is conducted, the power stages 610_1 and 610_2 are configured in series; when the switch circuit 620_1 is not conducted, the power stages 610_1 and 610_2 are configured in parallel [0032]-[0034]).
Regarding clam 20, the combination of Zheng and Wang discloses everything claimed as applied above (see claim 17), further Zheng discloses, the first passive envelope detector and the second passive envelope detector as a first two-stage envelope detector (the power stages 610_1 and 610_2 are configured in series; when the switch circuit 620_1 is not conducted, the power stages 610_1 and 610_2 are configured in parallel [0031]-[0032]; , the switch circuit 620 includes transmission gates 622, 624, and 626. The control signal SW and a control signal SWB are used to control the conduction status of the transmission gates 622, 624, and 626, and the control signal SWB is an inverted signal of the control signal SW. When the transmission gate 622 is conducted….the transmission gates 624 and 626 are conducted, so that two adjacent power stages coupled to the switch circuit 620 may be configured to be coupled in parallel [0039]-[0041]; , when the switch circuit 620_1 is conducted, the power stages 610_1 and 610_2 are configured in series; when the switch circuit 620_1 is not conducted, the power stages 610_1 and 610_2 are configured in parallel [0032]-[0034]).
Regarding clam 21, the combination of Zheng and Wang discloses everything claimed as applied above (see claim 20), further Zheng discloses, the first passive envelope detector and the second passive envelope detector as a first two-stage envelope detector (the power stages 610_1 and 610_2 are configured in series; when the switch circuit 620_1 is not conducted, the power stages 610_1 and 610_2 are configured in parallel [0031]-[0032]; , the switch circuit 620 includes transmission gates 622, 624, and 626. The control signal SW and a control signal SWB are used to control the conduction status of the transmission gates 622, 624, and 626, and the control signal SWB is an inverted signal of the control signal SW. When the transmission gate 622 is conducted….the transmission gates 624 and 626 are conducted, so that two adjacent power stages coupled to the switch circuit 620 may be configured to be coupled in parallel [0039]-[0041]; , when the switch circuit 620_1 is conducted, the power stages 610_1 and 610_2 are configured in series; when the switch circuit 620_1 is not conducted, the power stages 610_1 and 610_2 are configured in parallel [0032]-[0034]).
Regarding clam 22, the combination of Zheng and Wang discloses everything claimed as applied above (see claim 17), in addition Wang discloses, wherein the first configuration is associated with a first data rate, and wherein the second configuration is associated with a second data rate that is different than the first data rate (To compare to prior work using direct envelope detection architecture with different data rate and therefore, baseband bandwidth, BW.sub.BB [0040]-[0042]; An envelope detector with a larger number of stages, N, requires large transistor widths and has a larger input capacitance to maintain a given output bandwidth, which limits transformer gain. Parasitic capacitance increases with transistor width, adding to the capacitive load at the output and requiring a decrease in output resistance [0046]-[0049]).
Regarding clam 23, the combination of Zheng and Wang discloses everything claimed as applied above (see claim 17), further Zheng discloses, wherein the first configuration is associated with a first gain, and wherein the second configuration is associated with a second gain that is different than the first gain (FIG. 4A illustrates a schematic block diagram of a power stage according to an embodiment of the disclosure. FIG. 4B illustrates a schematic circuit diagram of the power stage of the embodiment of FIG. 4A. Referring to FIGS. 4A and 4B, a power stage 610 of this embodiment includes a first end A, a second end B, and a third end C. The first end A of the power stage 610 is coupled to a previous-stage switch circuit (a first switch circuit). The second end B of the power stage 610 is coupled to a next-stage switch circuit (a second switch circuit). The third end C of the power stage 610 is coupled to the radio frequency signal VRF [0031]-0038]).
Regarding clam 24, the combination of Zheng and Wang discloses everything claimed as applied above (see claim 17), in addition Wang discloses, wherein the first passive envelope detector and the second passive envelope detector each have a differential configuration, and wherein, in accordance with the differential configuration, the one or more voltages correspond to a differential voltage (With the present pseudo-balun ED, two n- and p-type CG amplifiers 20, 22 are stacked in a current re-use structure (FIG. 2B) with impedance 23 to provide single-ended to pseudo-differential conversion, eliminating the need of an explicit reference. Interestingly, the preferred ED acts as a pseudo-balun only to 2nd order non-linearities: linear RF currents flow symmetrically through the n- and p-CG amplifiers to partially cancel at the outputs (and are then further filtered), yet the baseband 2nd order components flow pseudo-differentially with slightly different gains due to the asymmetric loading. Compared to a fully (pseudo)-differential CS design [5], the present pseudo-balun ED's input is inherently an AC ground because of the transformer and thus no bias circuits (with their additional parasitic capacitance) are required at the input [0031]).
Regarding clam 25, the combination of Zheng and Wang discloses everything claimed as applied above (see claim 17), further Zheng discloses, wherein the first passive envelope detector and the second passive envelope detector each have a single-ended configuration, and wherein, in accordance with the single-ended configuration, the one or more voltages correspond to a single-ended voltage (Using an RC low-pass filter at the ED output as a dynamic reference is another solution, but at the expense of degraded SNR due to the pulsed nature of the baseband signal. With the present pseudo-balun ED, two n- and p-type CG amplifiers 20, 22 are stacked in a current re-use structure (FIG. 2B) with impedance 23 to provide single-ended to pseudo-differential conversion, eliminating the need of an explicit reference [0031]).
Regarding claim 26, Zeng discloses,
An apparatus (Referring to FIG. 1, an electronic paper display apparatus 100 of this embodiment includes a radio frequency rectifier circuit 110, a driver circuit 120, and an electronic paper display panel 130 [0029]) comprising:
first means for passive detection and second means for passive detection (Referring to FIGS. 4A and 4B, a power stage 610 of this embodiment includes a first end A, a second end B, and a third end C. The first end A of the power stage 610 is coupled to a previous-stage switch circuit (a first switch circuit). The second end B of the power stage 610 is coupled to a next-stage switch circuit (a second switch circuit). The third end C of the power stage 610 is coupled to the radio frequency signal VRF [0034]; 0044] Table 1 shows the corresponding relationship between the output voltage values and the equivalent stage numbers according to the embodiment of FIG. 6: In Table 1, a radio frequency signal with higher energy corresponds to a higher output voltage, and a higher output voltage corresponds to a smaller equivalent stage number, [0044]-[0047]); and
means for coupling the first means for passive detection to the second means for passive detection as multiple stages in a first configuration (Referring to FIGS. 4A and 4B, a power stage 610 of this embodiment includes a first end A, a second end B, and a third end C. The first end A of the power stage 610 is coupled to a previous-stage switch circuit (a first switch circuit). The second end B of the power stage 610 is coupled to a next-stage switch circuit (a second switch circuit). The third end C of the power stage 610 is coupled to the radio frequency signal VRF. Taking the power stage 610_3 of FIG. 3 as an example, a first end of the power stage 610_3 is coupled to the previous-stage switch circuit 620_2. A second end of the power stage 610_3 is coupled to the next-stage switch circuit 620_3. A third end of the power stage 610_3 is coupled to the radio frequency signal VRF. The switch circuit 620_2 and the switch circuit 620_3 are two adjacent switch circuits [0034]-[0039] and [0050]-[0053])and for coupling the first means for passive detection to the second means for passive detection as a single stage in a second configuration (the power stages 610_1 and 610_2 are configured in series; when the switch circuit 620_1 is not conducted, the power stages 610_1 and 610_2 are configured in parallel [0031]-[0032]; , the switch circuit 620 includes transmission gates 622, 624, and 626. The control signal SW and a control signal SWB are used to control the conduction status of the transmission gates 622, 624, and 626, and the control signal SWB is an inverted signal of the control signal SW. When the transmission gate 622 is conducted….the transmission gates 624 and 626 are conducted, so that two adjacent power stages coupled to the switch circuit 620 may be configured to be coupled in parallel [0039]-[0041).
However, Zheng does not explicitly disclose, a plurality of envelope detectors including at least a first passive envelope detector and a second passive envelope detector.
In the same field of endeavor, Wang discloses, a plurality of envelope detectors including at least a first passive envelope detector and a second passive envelope detector (The tunable passive pseudo-balun ED architecture 12a is a N-stage rectifier with the middle node connected to V.sub.CM (common mode voltage) and the bulk nodes connected to a tunable voltage, Vbulk, to set the bandwidth. As such, the baseband ac currents flow in opposite directions relative to ground to form a pseudo-differential output V.sub.out,p, V.sub.out,n [0046]-[0048]).
Therefore, it would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify Zheng by specifically providing a plurality of envelope detectors including at least a first passive envelope detector and a second passive envelope detector, as taught by Wang for the purpose of improves sensitivity and interferer rejection both the primary and secondary stages resonate at the same center frequency, providing filtering and performing the impedance transformation, which results in a passive voltage gain [0029].
Regarding clam 27, the combination of Zheng and Wang discloses everything claimed as applied above (see claim 26), further Zheng discloses, wherein the first means for passive envelope detection is coupled to the second means for passive envelope detection via a serial connection in the first configuration, and wherein the first means for passive envelope detection is coupled in parallel to the second means for passive envelope detection in the second configuration (the power stages 610_1 and 610_2 are configured in series; when the switch circuit 620_1 is not conducted, the power stages 610_1 and 610_2 are configured in parallel [0031]-[0032]; , the switch circuit 620 includes transmission gates 622, 624, and 626. The control signal SW and a control signal SWB are used to control the conduction status of the transmission gates 622, 624, and 626, and the control signal SWB is an inverted signal of the control signal SW. When the transmission gate 622 is conducted….the transmission gates 624 and 626 are conducted, so that two adjacent power stages coupled to the switch circuit 620 may be configured to be coupled in parallel [0039]-[0041]; , when the switch circuit 620_1 is conducted, the power stages 610_1 and 610_2 are configured in series; when the switch circuit 620_1 is not conducted, the power stages 610_1 and 610_2 are configured in parallel [0032]-[0034]).
Regarding clam 28, the combination of Zheng and Wang discloses everything claimed as applied above (see claim 26), further Zheng discloses, wherein the first means for passive envelope detection and the second means for passive envelope detection are configurable as a first two-stage envelope detector (the power stages 610_1 and 610_2 are configured in series; when the switch circuit 620_1 is not conducted, the power stages 610_1 and 610_2 are configured in parallel [0031]-[0032]; , the switch circuit 620 includes transmission gates 622, 624, and 626. The control signal SW and a control signal SWB are used to control the conduction status of the transmission gates 622, 624, and 626, and the control signal SWB is an inverted signal of the control signal SW. When the transmission gate 622 is conducted….the transmission gates 624 and 626 are conducted, so that two adjacent power stages coupled to the switch circuit 620 may be configured to be coupled in parallel [0039]-[0041]; , when the switch circuit 620_1 is conducted, the power stages 610_1 and 610_2 are configured in series; when the switch circuit 620_1 is not conducted, the power stages 610_1 and 610_2 are configured in parallel [0032]-[0034]).
Regarding clam 30, the combination of Zheng and Wang discloses everything claimed as applied above (see claim 26), further Zheng discloses, wherein the first configuration is associated with a first data rate and with a first gain, and wherein the second configuration is associated with a second data rate that is different than the first data rate and with a second gain that is different than the first gainr (the power stages 610_1 and 610_2 are configured in series; when the switch circuit 620_1 is not conducted, the power stages 610_1 and 610_2 are configured in parallel [0031]-[0032]; , the switch circuit 620 includes transmission gates 622, 624, and 626. The control signal SW and a control signal SWB are used to control the conduction status of the transmission gates 622, 624, and 626, and the control signal SWB is an inverted signal of the control signal SW. When the transmission gate 622 is conducted….the transmission gates 624 and 626 are conducted, so that two adjacent power stages coupled to the switch circuit 620 may be configured to be coupled in parallel [0039]-[0041]; , when the switch circuit 620_1 is conducted, the power stages 610_1 and 610_2 are configured in series; when the switch circuit 620_1 is not conducted, the power stages 610_1 and 610_2 are configured in parallel [0032]-[0034]; To compare to prior work using direct envelope detection architecture with different data rate and therefore, baseband bandwidth, BW.sub.BB [0040]-[0042]; An envelope detector with a larger number of stages, N, requires large transistor widths and has a larger input capacitance to maintain a given output bandwidth, which limits transformer gain. Parasitic capacitance increases with transistor width, adding to the capacitive load at the output and requiring a decrease in output resistance [0046]-[0049]).
Allowable Subject Matter
Claims 7-10 and 29 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 7, The following is a statement of reasons for the indication of allowable subject matter: the closest prior art, Zheng and Wang, whether taken alone or in combination does not teach the following novel feature: “a first capacitor having a first terminal coupled to a first input node and further having a second terminal coupled to the first inverter; and a second capacitor having a first terminal coupled to a second input node and further having a second terminal coupled to the second inverter”, in combination with the other limitations in claims 1 and 6.
Claim 8 is allowed as those inherit the allowable subject matter from claim 7.
Regarding claim 9, The following is a statement of reasons for the indication of allowable subject matter: the closest prior art, Zheng and Wang, whether taken alone or in combination does not teach the following novel feature: “wherein the first passive envelope detector and the second passive envelope detector each have a single-ended configuration, and wherein, in accordance with the single-ended configuration, the first passive envelope detector and the second passive envelope detector each include: a first capacitor having a first terminal coupled to an input node; a first transistor having a source terminal coupled to a second terminal of the first capacitor; a second transistor having a drain terminal and a gate terminal that are coupled to the source terminal of the first transistor and that are further coupled to the second terminal of the first capacitor; and a second capacitor having a first terminal coupled to a source terminal of the second transistor and further having a second terminal coupled to a ground node”, in combination with the other limitations in claim 1.
Claim 10 is allowed as those inherit the allowable subject matter from claim 9.
Regarding claim 29, The following is a statement of reasons for the indication of allowable subject matter: the closest prior art, Zheng and Wang, whether taken alone or in combination does not teach the following novel feature: “third means for passive envelope detection; and fourth means for passive envelope detection, wherein the third means for passive envelope detection and the fourth means for passive envelope detection are configurable as a second two-stage envelope detector in parallel with the first two-stage envelope detector”, in combination with the other limitations in claims 26 and 28.
Prior Art of the Record:
The prior art made of record not relied upon and considered pertinent to
Applicant’s disclosure:
US 20240106469: Methods and systems for operating a transceiver are described. A transceiver can include an upconverting mixer, a downconverting mixer, a controller, and an envelope detector. The upconverting mixer can mix an input signal with a local oscillator (LO) signal to generate a transmitter signal. The envelope detector can receive the transmitter signal outputted from the upconverting mixer and output an envelope of the transmitter signal to an output line of the downconverting mixer.
US 20180316312: Apparatus and methods for power amplifiers with positive envelope feedback are provided herein. In certain implementations, a power amplifier system includes a power amplification stage that amplifies a radio frequency signal, at least one envelope detector that generates one or more detection signals indicating an output signal envelope of the power amplification stage, and a wideband feedback circuit that provides positive envelope feedback to a bias of the power amplification stage based on the one or more detection signals.
US 20180123538: A power amplifier bias circuit with embedded envelope detection includes a bias circuit stage coupled to an envelope detector circuit to increases a bias provided to a power amplifier as a function of an incoming envelope signal. The envelope detector circuit includes a first source/emitter follower transistor, a current source, and a filter to generate a baseband envelope signal. The current source is coupled to an output node of the first source/emitter follower transistor and the filter is also coupled to the output node of the first source/emitter follower transistor.
Conclusion
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/GOLAM SOROWAR/ Primary Examiner, Art Unit 2641
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