DETAILED ACTION
Claims 1-20 are pending.
Priority: 9/16/2022
Assignee: Kioxia
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim(s) 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim(s) 1-13 of U.S. Patent No. 12210450. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims are obvious variants of each other.
18/983,022(instant)
(1)A memory system connectable to a host, the memory system comprising:
a nonvolatile memory; and
a controller electrically connected to the nonvolatile memory and configured to:
determine, as a first write data set, write data which have been requested from the host to be written into the nonvolatile memory but lost due to unexpected power loss by acquiring, from a logical address list stored in a volatile memory, logical addresses corresponding to write data of which writing into the nonvolatile memory is incomplete at a time of the unexpected power loss; and
save, into the nonvolatile memory, a first list indicating a list of logical addresses corresponding to the first write data set.
Claim 11 is a method claim that is similar.
12,210,450(Parent)
Claim 1, 10
Analysis
Single-list/generic form of patented lost-write list and error-marking mechanism. Claim 10 directly supports the incomplete-write/list-generation concept.
18/983,022(instant
2. The memory system according to claim 1, wherein
the controller is further configured to:
manage address translation information indicating a correspondence between each of logical addresses in a logical address space of the memory system and each of physical addresses of locations in the nonvolatile memory; and
in response to restoration of power to the memory system,
read the first list from the nonvolatile memory;
specify at least one of the logical addresses corresponding to the first write data set listed in the read first list; and
set, in the address translation information, a value indicating an error for the at least one of the logical addresses corresponding to the first write data set.
Claim 12 is a method claim that is similar.
12,210,450(Parent)
Claim 1
Analysis
Reads saved list after restoration, identifies listed logical address, and sets error value in address translation information; patent claim 1 already updates rebuilt address translation information based on saved lost-write list.
18/983,022(instant
3. The memory system according to claim 2, wherein the controller is further configured to: in response to receiving, from the host, a read request that specifies the at least one of the logical addresses corresponding to the first write data, transmit an error response to the host.
Claim 13 is a method claim that is similar.
12,210,450(Parent)
Claim 1
Analysis
Transmitting an error response on a read to a lost-write logical address is the predictable result of the patented error-value association.
18/983,022(instant
4. The memory system according to claim 2, further comprising: a volatile memory, wherein the controller is further configured to: manage the address translation information using a logical-to-physical address translation table stored in the volatile memory; divide the logical address space of the memory system into a plurality of logical address ranges; divide the logical-to-physical address translation table into a plurality of table areas respectively corresponding to the plurality of logical address ranges; and perform first processing of writing, into the nonvolatile memory, a piece of the address translation information on one of the plurality of table areas stored in the volatile memory at a first timing and an update log indicating an update content of the piece of the address translation information on the one of the plurality of table areas updated after the first timing.
Claim 14 is a method claim that is similar.
12,210,450(Parent)
Claim 1
Analysis
Generic one-table-area version of patented L2P table areas, logical address ranges, saved address translation information, and update logs.
18/983,022(instant
5. The memory system according to claim 4, wherein the piece of the address translation information on the one of the plurality of table areas includes a plurality of fragments including at least a first fragment and a second fragment, and the controller is configured to: perform the first processing by performing: processing of acquiring the first fragment from the volatile memory; processing of writing, into the nonvolatile memory, the first fragment and a first update log indicating an update content regarding all of the plurality of fragments of the piece of the address translation information on the one of the plurality of table areas updated after the acquisition of the first fragment; processing of acquiring the second fragment from the volatile memory; and processing of writing, into the nonvolatile memory, the second fragment and a second update log indicating an update content regarding all of the plurality of fragments of the piece of the address translation information on the one of the plurality of table areas updated after the acquisition of the second fragment.
Claim 15 is a method claim that is similar.
12,210,450(Parent)
Claim 5
Analysis
Generic fragment/update-log version of patented first/second address translation information and update logs.
18/983,022(instant
6. The memory system according to claim 4, wherein the controller is further configured to: in response to the restoration of power to the memory system, notify the host that the memory system is ready to process an input/output command; and when an input/output command specifying a logical address belonging to one of the plurality of logical address ranges corresponding to the one of the plurality of table areas is received from the host, rebuild, onto the volatile memory, based on the piece of the address translation information on the one of the plurality of table areas stored in the nonvolatile memory and the update log of the piece of the address translation information stored in the nonvolatile memory, latest address translation information on the one of the plurality of table areas; and set the value indicating the error into the rebuilt latest address translation information.
Claim 16 is a method claim that is similar.
12,210,450(Parent)
Claim 1
Analysis
Rebuilds latest address translation information after power restoration and sets error value, matching patent claim 1.
18/983,022(instant
7. The memory system according to claim 6, wherein the piece of the address translation information on the one of the plurality of table areas includes a plurality of fragments including at least a first fragment and a second fragment, and the controller is further configured to: perform the first processing by performing: processing of acquiring the first fragment from the volatile memory; processing of writing, into the nonvolatile memory, the first fragment and a first update log indicating an update content regarding all of the plurality of fragments of the piece of the address translation information on the one of the plurality of table areas updated after the acquisition of the first fragment; processing of acquiring the second fragment from the volatile memory; and processing of writing, into the nonvolatile memory, the second fragment and a second update log indicating an update content regarding all of the plurality of fragments of the piece of the address translation information on the one of the plurality of table areas updated after the acquisition of the second fragment, in rebuilding the latest address translation information on the one of the plurality of table areas onto the volatile memory, copy, from the nonvolatile memory to the volatile memory, the second fragment and the first fragment; reflect, to the first fragment on the volatile memory, a content of the first update log stored in the nonvolatile memory; and reflect, to the first fragment and the second fragment on the volatile memory, a content of the second update log stored in the nonvolatile memory; and after the latest address translation information on the one of the plurality of table areas is rebuilt, set the value indicating the error into the rebuilt latest address translation information.
Claim 17 is a method claim that is similar.
12,210,450(Parent)
Claim 6
Analysis
Copies fragments/address translation information, reflects update logs, then sets error value after rebuild, matching patent claim 6.
18/983,022(instant
8. The memory system according to claim 1, further comprising: a capacitor, wherein the controller is configured to: in response to the unexpected power loss, save the first list into the nonvolatile memory using power stored in the capacitor.
Claim 18 is a method claim that is similar.
12,210,450(Parent)
Claim 2
Analysis
Uses capacitor power to save lost-write list into nonvolatile memory; patent claim 2 saves first and second lists with capacitor power.
18/983,022(instant
9. The memory system according to claim 1, wherein the first write data is received from the host and writing of the first write data into the nonvolatile memory is not completed.
Claim 19 is a method claim that is similar.
12,210,450(Parent)
Claim 10
Analysis
Host write data whose writing is incomplete corresponds to the remaining addresses after removal of completed writes in patent claim 10.
18/983,022(instant
10. The memory system according to claim 1, wherein the unexpected power loss is power loss to the memory system without notification from the host.
Claim 20 is a method claim that is similar.
12,210,450(Parent)
Claim 1
Analysis
Unexpected power loss without host notification is an expected characterization of the patented unexpected power loss context.
Allowable Subject Matter
Claim(s) 4-5, 6-7, 14-15, 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable based on the prior art, if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and the above double patenting rejection is settled.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mylavarapu(20160246530), and further in view of Kern et al.(20090158085).
As per claim 1, Mylavarapu discloses:
A memory system connectable to a host(Mylavarapu, [0021 -- the data processing system 10 may include a host device 100 and a memory system 200.]), the memory system comprising:
a nonvolatile memory(Mylavarapu, [0025 -- The memory device 220 may be implemented with a volatile memory device such as a dynamic random access memory (DRAM) and a static random access memory (SRAM) or a non-volatile memory device such as a read only memory (ROM)]);
and a controller electrically connected to the nonvolatile memory(Mylavarapu, [0024 -- The controller 210 may control storage of data in the memory device 220. The memory device 220 may store data to be accessed by the host device 100.]) and configured to:
and save, into the nonvolatile memory, a first list indicating a list of logical addresses corresponding to the first write data set(Mylavarapu, [0087 -- FIG. 8 is a flow chart illustrating an operation after a power loss (or a power down) 620 in a memory system in accordance with the present invention. For example, the operation 620 may be performed by the controller 310 of the memory system 300 as shown in FIGS. 3 to 5B.], [0088 -- Referring to FIG. 8, at the step 810, the controller 310 checks whether the L2P area 1 332-1 of the NAND 320 can accommodate the journal 314. If the L2P area 1 332-1 can accommodate the journal 314, at the step 820, the controller 310 drops the journal 314 in the L2P area 1 332-1. If the L2P area 1 332-1 cannot accommodate the journal 314, at the step 830, the controller 310 drops the journal 314 in the L2P area 2 332-2.]).
Mylavarapu does not explicitly disclose the following, however Kern discloses:
determine, as a first write data set(Kern, [0019 -- In some aspects, the recoding of the address modifying transactions and bookend data, along with providing for integrity check protection, such as error correction code (ECC) protection or the like, over the data to be written, limits the amount of data that may be lost in the event of an operational error or failure. In the event that the write operation of the data was completed prior to the error or failure but the current translated physical address was not written to the write buffer, the data can be recovered in an auditing process that is performed at power-up]), write data which have been requested from the host to be written into the nonvolatile memory but lost due to unexpected power loss by acquiring, from a logical address list stored in a volatile memory(Kern, [0021 -- In one specific aspect of the system, the volatile memory may include a translation table cache operable for storing the address translation table and bookend recordings of the previous, i.e., last-in-time, physical address translation and the current translated physical address based on the recorded address-modifying transactions.]), logical addresses corresponding to write data of which writing into the nonvolatile memory is incomplete at a time of the unexpected power loss(Kern, [0051 -- the translation table cache 308 may additionally include bookend recordings 320 that provide of a mapping of the previous (i.e., last-in-time translated physical address to the current translated physical address based on the recoded address modifying transactions], [0058 -- According to present embodiments, in addition to recording to the new physical address in the translation table cache 410, a bookend entry may also be recorded in the memory for the purpose of subsequent data recovery in the event of an error/failure during a subsequent memory operation, for example a power failure occurring during a subsequent write operation]);
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the features of Kern into the system of Mylavarapu for the benefit of providing a mechanism that allows for recovery of write operations in the event of failure such as power failure, or error occurring during the write operation. The system provides the accuracy of address translations. The system provides transaction recording and integrity check protection for allowing recovery of write operations that are fully completed due to the failure/error(Kern, [0018]).
Claim 11 is directed to method steps that are implemented by the system claim 1. Therefore the corresponding mappings are similarly incorporated.
Claim(s) 2-3, 8, 10, 12-13, 18, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mylavarapu(20160246530), in view of Kern et al.(20090158085), and further in view of Royer et al.(20090172466).
As per claim 2, the rejection of claim 1 is incorporated, in addition, Mylavarapu discloses:
wherein the controller is further configured to:
manage address translation information indicating a correspondence between each of logical addresses in a logical address space of the memory system and each of physical addresses of locations in the nonvolatile memory(Mylavarapu, [0088 -- Referring to FIG. 8, at the step 810, the controller 310 checks whether the L2P area 1 332-1 of the NAND 320 can accommodate the journal 314. If the L2P area 1 332-1 can accommodate the journal 314, at the step 820, the controller 310 drops the journal 314 in the L2P area 1 332-1. If the L2P area 1 332-1 cannot accommodate the journal 314, at the step 830, the controller 310 drops the journal 314 in the L2P area 2 332-2.]);
Mylavarapu does not explicitly disclose the following, however Royer discloses:
specify at least one of the logical addresses corresponding to the first write data set listed in the read first list(Royer, [0037 -- For each write to a logical address, a sequence number is saved in page metadata to enable identification of the current (most recent) write for the logical address. This is required for proper power-fail recovery.]);
and in response to restoration of power to the memory system, read the first list from the nonvolatile memory(Royer, [0041 -- At operation 325 a Grown Defect Map (GDM) is loaded from its known primary physical location (or from its backup location in case the primary page reports errors). Operations 330-390 are performed for each page in each erase block (EB) that is not marked as defective in the GDM.]);
and based on the read first list, set, in the address translation information, a value indicating an error to at least one of the logical addresses corresponding to the first write data(Royer, [0042 -- If, at operation 335, the metadata read returns an ECC error, then control passes to operation 340 and the page is marked as invalid in Page Metadata Array.], [0042 -- If, at operation 355, the read causes an ECC failure, then control passes to operation 360 and the page is marked as invalid in Page Metadata Array.]).
Therefore it would have been obvious to a person of ordinary skill to at the time of filing to incorporate the features of Royer into the system of Mylavarapu for the benefit of allowing actions on individual pages by using consumption state information, thus avoiding the need to erase entire blocks, and hence enabling fast disk caching and solid-state-disk operation(Royer, [0020]).
As per claim 3, the rejection of claim 2 is incorporated, in addition, Mylavarapu discloses:
wherein the controller is further configured to: in response to receiving, from the host, a read request that specifies the at least one of the logical addresses corresponding to the first write data, transmit an error response to the host(Mylavarapu, [0032 -- The ECC unit 213 may detect and correct errors in the data read from the memory device 220 during the read operation. The ECC unit 213 may not correct error bits when the number of the error bits is greater than or equal to a threshold number of correctable error bits, and may output an error correction fail signal indicating failure in correcting the error bits.]).
As per claim 8, the rejection of claim 1 is incorporated, in addition, Mylavarapu discloses:
a capacitor, wherein the controller is configured to: in response to the unexpected power loss, save the first list into the nonvolatile memory using power stored in the capacitor(Mylavarapu, [0040 -- Flushing tables to the NAND might potentially be the longest operation after a power down (e.g., after a specific command to enter a low power mode or a surprise power loss). Typically, enterprise drives as the memory device 220 (or the storage) have limited charge in the capacitors (e.g., to support only few milliseconds) after power goes down]).
As per claim 10, the rejection of claim 1 is incorporated, in addition, Mylavarapu discloses:
wherein the unexpected power loss is power loss to the memory system without notification from the host(Mylavarapu, [0040 -- Flushing tables to the NAND might potentially be the longest operation after a power down (e.g., after a specific command to enter a low power mode or a surprise power loss).]).
Claim 12-13, 18, 20 are directed to method steps that are implemented by the system claims 2-3, 8, 10, respectively. Therefore the corresponding mappings are similarly incorporated.
Claim(s) 9, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mylavarapu(20160246530), in view of Kern et al.(20090158085), in view of Royer et al.(20090172466) and further in view of Kojima et al.(20160070336).
As per claim 9, the rejection of claim 1 is incorporated, in addition, Mylavarapu does not explicitly disclose the following, however Kojima discloses:
wherein the first write data is received from the host and writing of the first write data into the nonvolatile memory is not completed(Kojima, [0044 -- In addition, the FE 10 cancels a command in process (step S23). A command in process in the FE 10 is a command that is included in commands sent from the host 2 and that is not completed in processing in the BE 20. Therefore, the command in process in the FE 10 is a command for which the FE 10 does not give a completion response to the host 2.]).
Therefore it would have been obvious to a person of ordinary skill to at the time of filing to incorporate the features of Kojima into the system of Mylavarapu for the benefit of utilizing multiple-level cell (MLC) direct write operation as compared with single-level cell (SLC) cache operation to reduce write amplification factor (WAF) in a work load of an enterprise that is low in localization. The system prevents error correction that is high in correction intensity from being executed at time of PLP processing. (Kojima, [0072]).
Claim 19 is directed to method steps that are implemented by the system claim 9. Therefore the corresponding mappings are similarly incorporated.
Examiner Notes
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Mangold et al.(20140223231) where the apparatus has a non-volatile memory and a memory controller that is coupled with the non-volatile memory, and configured to defragment the non- volatile memory to write valid data from an erase block into a page, and thus enables improving input or output performance of computer system, and enables reducing chance of data corruption due to power loss, and enables reducing or eliminating write cycles of the non-volatile memory due to pad data is designed to be written to the pages, and enables preventing lower-page corruption, and enables improving integrity of the data stored in the non- volatile memory, and also reducing cost and space required for the power-fail protection circuitry.
Trika et al.(20070005928) where the method involves performing write operations to store data in different physical memory locations being associated with logical address shared in common among physical memory locations. The sequence information including global sequence, local sequence number and time stamp, is stored in physical memory locations to indicate which one of the write operations occurred last(Trika, abstract).
Response to Arguments
Applicant's arguments filed 3/30/2026 regarding the double patenting rejection have been fully considered but they are not persuasive. The double patenting rejection is further elaborated including the amended claims.
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on the combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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Arvind Talukdar
Primary Examiner
Art Unit 2132
/ARVIND TALUKDAR/Primary Examiner, Art Unit 2132
Prosecution Insights