DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to RCE filed on 08/02/2026. In this RCE, claims 3-12 and 14-19 were canceled and new dependent claims 21-36 were added. Claims 1-2, 13, and 20-36 have been examined and are pending in this application.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/02/2026 has been entered.
Claim Objections
Claim 13 is objected to because of the following informalities: typographical error in the sentence “storage space the DDR” line 7. Appropriate correction is required.
Response to Arguments
Applicant’s arguments with respect to claims 1-2, 13, and 20-36 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Prior art of record Conway US 2017/0212845 which was previously applied in the rejection of one or more dependent claims now anticipate one or more of the amended claims. Applicant did not put forth any argument regarding this reference.
In view of this reference, independent claims 1, 13, and 20 are not in a condition for allowance. Claims 2, 21-25, 29-33, and 36 are also not in a condition for allowance because of this reference and one or more additional new references.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 13 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Conway U S 2017/0212845 (“Conway”).
As per independent claim 1, Conway teaches A data processing method for an electronic device (“a method includes profiling a stream of memory accesses to generate an access frequency ranked list of address ranges of main memory and corresponding access frequencies based on memory addresses in the stream of memory accesses.” Para 0008) comprising a dual data rate RAM (DDR) (“double data rate (DDR4) memory” para 0049) and a high bandwidth memory (HBM) (“high bandwidth memory 324” para 0049), the method performed by a CPU (a processor generates address range’s access frequency, para 0014), the method comprising:
obtaining a data processing request of an application, wherein the data processing request is configured to indicate processing of associated data located in a first storage space in the DDR (Request buffer 806 receives a stream of DDR4 main memory (para 0049) requests and stores associated frequency of accesses, para 0037);
in response to the data processing request, returning the associated data to the CPU (“The controller may be configured to service any read memory accesses to the region using the main memory during the transfer.” Para 0012);
determining whether the associated data is hot data (“range profiler 322 identifies one or more most frequently accessed regions of main memory 110 for allocation to high bandwidth memory 324.” Para 0047. “rather than update high bandwidth memory 324 in response to a particular memory access, updates to high bandwidth memory 324 occur periodically in the background to regular memory operations.” Para 0046);
based on the associated data is the hot data and the associated data is not in the HBM, copying the associated data from the DDR to the HBM in order that the associated data can be directly accessed from the HBM instead of from the DDR (“The allocation operation of the periodic migration may include creating a tag map entry in the region migration cache tag map and triggering direct memory access controller 332 to transfer data from main memory 110 to high bandwidth memory 324.” Para 0050).
As per dependent claim 2, Conway discloses the method of claim 1. Conway teaches wherein a usage manner of the HBM is a cache mode, and the cache mode indicates that the HBM is used as a cache of the memory (“high-bandwidth memory 324 is fully associative.” Para 0043).
As per independent claim 13, this claim is rejected based on arguments provided above for similar rejected independent claim 1. See FIG. 1 of Conway for processor and memory.
As per independent claim 20, this claim is rejected based on arguments provided above for similar rejected independent claim 1. For computer program product on a non-transitory computer readable medium, see para 0057 of Conway.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21-23, 25, 29-33, and 36 are rejected under 35 U.S.C. 103 as being unpatentable over Conway in view of Jin et al. US 2017/0277640 (“Jin”).
As per dependent claim 21, Conway discloses the method of claim 1. Conway teaches wherein the memory bypass flag indicates a storage manner of using the HBM (“Hit logic in region migration cache tag map and controller 320 compares tag bits of the memory address of a memory request to tag bits associated with the stored data in the high bandwidth memory 324 to determine whether high bandwidth memory 324 includes contents of the target memory location and generates an indication of that comparison (i.e., indicating a hit or a miss).” Para 0043), the storage manner is set based on an access requirement of the application for the first storage space (“a memory access profiler configured to generate an access frequency ranked list of address ranges of main memory and corresponding access frequencies based on memory addresses in a stream of memory requests.” Para 0011).
Conway may not explicitly disclose, but in an analogous art in the same field of endeavor, Jin teaches wherein the determining whether the associated data is hot data comprises: determining, based on a memory bypass flag corresponding to the first storage space, whether the associated data is hot data (“The overlap field records different content according to different PD flags: when PD is 0, the field is used as a counter and records the number of memory accesses to the page referenced by the page table entry;” para 0031. Overlap field is utilized to monitor a page access frequency, para 0082).
Given the teaching of Jin, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Conway with “wherein the determining whether the associated data is hot data comprises: determining, based on a memory bypass flag corresponding to the first storage space, whether the associated data is hot data”. The motivation would be that the overlap field improves the efficiency of address translation, para 0014 of Jin.
As per dependent claim 22, Conway in combination with Jin discloses the method of claim 21. Conway may not explicitly disclose, but Jin teaches wherein the method further comprises: invoking a first application programming interface (API) in an operating system (“calling a page copy interface” see claim 4);
setting a bypass flag field in a page table entry of a page table of the DDR, wherein the bypass flag field is for storing the memory bypass flag; and adding, based on the access requirement recorded in the application, the memory bypass flag to the bypass flag field in the page table entry corresponding to the first storage space (“The overlap field records different content according to different PD flags: when PD is 0, the field is used as a counter and records the number of memory accesses to the page referenced by the page table entry;” para 0031).
The same motivation that was utilized for combining Conway and Jin as set forth in claim 21 is equally applicable to claim 22.
As per dependent claim 23, Conway in combination with Jin discloses the method of claim 22. Conway may not explicitly disclose, but Jin teaches wherein the invoking the first application programming interface (API) in the operating system and setting the bypass flag field in the page table entry of the page table of the DDR comprises: when the application applies to the operating system for allocating a storage space in the DDR or after the application completes applying for allocating the storage space, invoking the first API and setting the bypass flag field in the page table entry of the page table (“The overlap field records different content according to different PD flags: when PD is 0, the field is used as a counter and records the number of memory accesses to the page referenced by the page table entry;” para 0031).
The same motivation that was utilized for combining Conway and Jin as set forth in claim 22 is equally applicable to claim 23.
As per dependent claim 25, Conway in combination with Jin discloses the method of claim 22. Conway may not explicitly disclose, but Jin teaches wherein the adding, based on the access requirement recorded in the application, the memory bypass flag to the bypass flag field in the page table entry corresponding to the first storage space comprises: querying, based on the access requirement recorded in the application and a virtual address of the first storage space, the page table entry corresponding to the first storage space; and adding the memory bypass flag to the page table entry (“The overlap field records different content according to different PD flags: when PD is 0, the field is used as a counter and records the number of memory accesses to the page referenced by the page table entry;” para 0031. Overlap field is utilized to monitor a page access frequency, para 0082).
The same motivation that was utilized for combining Conway and Jin as set forth in claim 22 is equally applicable to claim 25.
As per dependent claim 29, Conway in combination with Jin discloses the method of claim 21. Conway may not explicitly disclose, but Jin teaches wherein the data processing request comprises a virtual address of the first storage space, and the memory bypass flag is obtained by: querying, based on the virtual address, a page table entry corresponding to the first storage space; and obtaining the memory bypass flag from the page table entry (“address translation in TLB: acquiring the physical page number (ppn), the P flag, and content of the overlap tlb field from an TLB entry which corresponds to a virtual page number (vpn), and translating the virtual address into an NVM physical address according to the ppn;” para 0008).
The same motivation that was utilized for combining Conway and Jin as set forth in claim 21 is equally applicable to claim 29.
As per dependent claim 30, Conway in combination with Jin discloses the method of claim 29. Conway may not explicitly disclose, but Jin teaches wherein the querying, based on the virtual address, the page table entry corresponding to the first storage space comprises: querying, based on the virtual address, the page table of the DDR for the page table entry corresponding to the first storage space; or
querying, based on the virtual address, a translation lookaside buffer (TLB) of a processor for the page table entry corresponding to the first storage space (“address translation in TLB: acquiring the physical page number (ppn), the P flag, and content of the overlap tlb field from an TLB entry which corresponds to a virtual page number (vpn), and translating the virtual address into an NVM physical address according to the ppn;” para 0008).
The same motivation that was utilized for combining Conway and Jin as set forth in claim 29 is equally applicable to claim 30.
As per dependent claims 31-33 and 36, these claims are respectively rejected based on arguments provided above for similar rejected dependent claims 21-22, 25 and 29.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Conway in view of Jin and in further view of Li et al. US 2018/0268170 (“Li”).
As per dependent claim 24, Conway in combination with Jin discloses the method of claim 22. Conway and Jin may not explicitly disclose, but in an analogous art in the same field of endeavor, Li teaches wherein the invoking the first application programming interface (API) in the operating system and setting the bypass flag field in the page table entry of the page table of the DDR comprises: in a process of compiling the application by a compiler, invoking the first API through a second API or a directive provided by the compiler, and setting the bypass flag field in the page table entry of the page table (“the protection domain identifier may be stored in bits 62 to 59 of each page table entry. To write the protection domain identifiers, the computing device 100 may execute a system call or access another system-level application programming interface (API) provided by an operating system or other privileged code of the computing device 100. The code and data of the managed runtime environment may include, for example, virtual machines, interpreters, just-in-time-compilers, class libraries, and other components of the managed runtime environment 210.” Para 0027 and FIGS. 3A-B).
Given the teaching of Li, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Conway and Jin with “wherein the invoking the first application programming interface (API) in the operating system and setting the bypass flag field in the page table entry of the page table of the DDR comprises: in a process of compiling the application by a compiler, invoking the first API through a second API or a directive provided by the compiler, and setting the bypass flag field in the page table entry of the page table”. The motivation would be that secure code may be provided, para 0027 of Li.
Allowable Subject Matter
Claims 26-28 and 34-35 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Allowance
The following is an examiner’s statement of reasons for allowance.
After careful considerations, examination and search of the claimed invention, the closest prior art of record does not teach or anticipate the claimed feature of claims 26 and 34, taking claim 26 as exemplary, “wherein the method further comprises: predicting, based on a data transmission attribute of at least one of the DDR or the HBM, the access requirement of the application for the first storage space, wherein the data transmission attribute indicates impact of the storage medium on efficiency of data transmission; and setting the memory bypass flag for the first storage space based on the access requirement” in combination with the overall claimed limitations when interpreted in light of the specification.
Conway, Jin, and Li are completely silent about predicting the access requirement of an application, let alone the predicting the access requirement of the application based on storage medium transmission attributes. No other suitable reference was found. Therefore, claims 26 and 34 are objected as being allowable dependent claims.
Claims 27-28 directly and indirectly, respectively, depend from claim 26 and these claims are allowable by virtue of their dependency.
Claim 35 directly depend from claim 34 and this claim is allowable by virtue of its dependency.
Conclusion
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/ZUBAIR AHMED/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
