DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to amendment filed on 03/23/2026. Claims 1-20 have been examined and are pending in this application.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot in view of the current rejection.
A new reference Nakahara et al. US 2023/0143732 is cited in this Office Action necessitated by the amendment.
Applicant argues regarding the Roberts reference, page 11 of the remarks, “Roberts does not disclose storing a copy of the associated data into the second storage medium based on the memory bypass flag.”
The Examiner respectfully disagrees. The Examiner submits that Roberts explicitly teaches this claim feature. “the processing sub-system 12A may store a copy of a data block returned via the memory bus 20B directly into one or more registers 22 of the processing circuitry 16A, for example, when a cache bypass parameter is set (e.g., high or “1-bit”) by a memory access instruction (e.g., non-temporal load instruction) of an application (e.g., program or thread).” Paragraph [0090] of Roberts (emphasis added).
Applicant further argues regarding the Roberts reference, page 11 of the remarks, “Roberts does not disclose … and sending the copy from the second storage medium.”
The Examiner respectfully disagrees. Roberts teaches “supplying the target data block to the processing circuitry after the target data block is returned from the memory sub-system (process block 60).” Paragraph [0092] and FIG. 3. Regarding supplying the target data to the processing circuitry, Roberts further teaches “the processor-side memory controller 34A may instruct the processing sub-system 12 to store a copy of the target data block returned from the memory sub-system 14 in one or more registers 22 of the processing circuitry 16.” Paragraph [0100]. Since the one or more registers 22 are part of the processing circuitry 16, the data is supplied to the processing circuitry 16 via the one or more registers 22.
In view of the new reference and the foregoing remarks, independent claims 1, 13, and 20 are not in a condition for allowance. Claims depending therefrom, either directly or indirectly, are also not in a condition for allowance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7-8, 12-13, 16, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Roberts US 2020/0364146 (“Roberts”) in view of Nakahara et al. US 2023/0143732 (“Nakahara”).
As per independent claim 1, Roberts teaches A data processing method for an electronic device (“A method of operating a computing system,” see claim 12) comprising a first storage medium (“one or more processor-side caches 24” para 0082 and FIG. 1) and a second storage medium (“a first register 22A … an Nth register 22N” para 0082 and FIG. 1), the method comprising:
obtaining a data processing request of an application (“the processor-side memory controller 34A may output a read memory access that requests return of data targeted by the processing circuitry 16A.” para 0089 and FIG. 1), the data processing request indicating processing associated data of a first storage space in the first storage medium (“the processor-side memory controller 34A may control data storage in the processing sub-system 12A such that data received (e.g., returned) via the memory bus 20B is stored in a … processor-side cache 24A.” Para 0090 and FIG. 1), the first storage medium is a memory of the electronic device (“one or more processor-side caches 24” para 0082 and FIG. 1), and the second storage medium is a cache of the memory (“one or more registers 22, which provide storage locations directly accessible to its processing circuitry 16.” para 0082 and FIG. 1), wherein a read/write access performance of the second storage medium is better than the first storage medium (“hierarchical memory levels may be implemented such that lower memory levels provide faster data access (e.g., read and/or write) speed compared to higher memory levels, for example, at least in part by implementing a lower memory level with less (e.g., smaller) storage capacity compared to a higher memory level.” Para 0026 and FIGS. 1 and 2. Since registers 22 are part of the processing circuitry 16 and “one or more registers 22, which provide storage locations directly accessible to its processing circuitry 16”, para 0082 and FIGS. 1 and 2, registers 22 provide faster access than cache memories depicted in FIGS. 1 and 2);
obtaining, based on the data processing request, a memory bypass flag corresponding to the first storage space, the memory bypass flag indicating a storage manner of using the second storage medium, the storage manner being set based on an access requirement of the application for the first storage space (“the processing sub-system 12A may store a copy of a data block returned via the memory bus 20B directly into one or more registers 22 of the processing circuitry 16A, for example, when a cache bypass parameter is set (e.g., high or ‘1-bit’) by a memory access instruction (e.g., non-temporal load instruction) of an application (e.g., program or thread).” Para 0090 and FIG. 1);
and sending the copy from the second storage medium (“supplying the target data block to the processing circuitry after the target data block is returned from the memory sub-system (process block 60).” Paragraph [0092] and FIG. 3. Regarding supplying the target data to the processing circuitry, Roberts further teaches “the processor-side memory controller 34A may instruct the processing sub-system 12 to store a copy of the target data block returned from the memory sub-system 14 in one or more registers 22 of the processing circuitry 16.” Paragraph [0100]. Since the one or more registers 22 are part of the processing circuitry 16, the data is supplied to the processing circuitry 16 via the one or more registers 22).
Roberts discloses all of the claim limitations from above and additionally teaches caching target data blocks if they are accessed again (e.g., hot data). See paragraph [0090] and throughout the disclosure of Roberts. However, Roberts does not teach that his cache bypass parameter indicates, when set high, the data is hot. Therefore, Roberts does not teach “storing a copy of the associated data into the second storage medium based on the memory bypass flag indicating that the associated data is hot data”.
However, in an analogous art in the same field of endeavor, Nakahara teaches storing a copy of the associated data into the second storage medium based on the memory bypass flag indicating that the associated data is hot data (“The first control unit 112 sets the rewrite flag 114 to a rewrite state at a time point when data held in the first memory 116 is rewritten.” Para 0035. “The rewrite flag 114 in a rewrite state indicates that the rewrite frequency of data is high,” para 0032).
Given the teaching of Nakahara, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Roberts with “storing a copy of the associated data into the second storage medium based on the memory bypass flag indicating that the associated data is hot data”. The motivation would be that the invention improves access efficiency without increasing circuit size, para 0023 of Nakahara.
As per dependent claim 7, Roberts in combination with Nakahara discloses the method of claim 1. Roberts teaches wherein before the obtaining, based on the data processing request, the memory bypass flag corresponding to the first storage space, the method further comprises: predicting, based on a data transmission attribute of at least one of the first storage medium or the second storage medium, the access requirement of the application for the first storage space, wherein the data transmission attribute indicates impact of the storage medium on efficiency of data transmission (“a memory controller may predictively control data storage in one or more hierarchical memory levels.” Para 0031);
setting the memory bypass flag for the first storage space based on the predicted access requirement (“the processing sub-system 12A may store a copy of a data block returned via the memory bus 20B directly into one or more registers 22 of the processing circuitry 16A, for example, when a cache bypass parameter is set (e.g., high or ‘1-bit’) by a memory access instruction (e.g., non-temporal load instruction) of an application (e.g., program or thread).” Para 0090 and FIG. 1).
As per dependent claim 8, Roberts in combination with Nakahara discloses the method of claim 7. Roberts teaches wherein the predicting, based on the data transmission attribute of the at least one of the first storage medium and the second storage medium, the access requirement of the application for the first storage space comprises: inputting the data transmission attribute to a prediction network, and predicting, based on the input data transmission attribute using the prediction network, the access requirement of the application for the first storage space (“To facilitate improving prediction accuracy, … a memory controller may predict a subsequent data access pattern at least in part by analyzing historical data access information in view of transaction context associated with one or more data (e.g., memory) accesses.” Para 0042).
As per dependent claim 12, Roberts in combination with Nakahara discloses the method of claim 1. Roberts teaches wherein the processing the associated data based on the memory bypass flag comprises: if the memory bypass flag indicates to use the second storage medium to store data in the first storage medium, processing the associated data of the first storage space and copying the associated data of the first storage space to the second storage medium (“the processing sub-system 12A may store a copy of a data block returned via the memory bus 20B directly into one or more registers 22 of the processing circuitry 16A, for example, when a cache bypass parameter is set (e.g., high or ‘1-bit’) by a memory access instruction (e.g., non-temporal load instruction) of an application (e.g., program or thread).” Para 0090 and FIG. 1); or if the memory bypass flag indicates not to use the second storage medium to store data in the first storage medium, processing the associated data of the first storage space and skipping performing the step of copying the associated data of the first storage space to the second storage medium.
As per claims 13, 16, and 19, these claims are respectively rejected based on arguments provided above for similar rejected claims 1, 7, 12. For processor and memory see FIG. 1 of Roberts.
As per independent claim 20, this claim is rejected based on arguments provided above for similar rejected independent claim 1. For computer program product on a non-transitory computer readable medium, see para 0113 of Roberts.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Roberts in view of Nakahara and in further view of Conway US 2017/0212845 (“Conway”).
As per dependent claim 2, Roberts in combination with Nakahara discloses the method of claim 1. Roberts and Nakahara may not explicitly disclose, but in an analogous art in the same field of endeavor, Conway teaches wherein the second storage medium is a high bandwidth memory (HBM), a usage manner of the HBM is a cache mode, and the cache mode indicates that the HBM is used as the cache of the memory (“If the search results in a hit and the memory access is a read, high bandwidth memory 324 provides a corresponding addressable unit of the region to memory data bus 334. If the search results in a hit and the memory access is a write, region migration cache tag map and controller 320 writes data to the corresponding region of high bandwidth memory 324 and range profiler 322 updates access information for a region of main memory associated with the memory access.” Para 0045).
Given the teaching of Conway, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Roberts and Nakahara with “wherein the second storage medium is a high bandwidth memory (HBM), a usage manner of the HBM is a cache mode, and the cache mode indicates that the HBM is used as the cache of the memory”. The motivation would be that the invention improves memory latency in sparsely-used memory systems, para 0031 of Conway.
Claims 3-6 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Roberts in view of Nakahara and in further view of Heil et al. US 2009/0204769 (“Heil”) and in further view of Kaminski et al. US 2011/0161620 (“Kaminski”).
As per dependent claim 3, Roberts in combination with Nakahara discloses the method of claim 1. Roberts and Nakahara do not explicitly teach “wherein before the obtaining the memory bypass flag corresponding to the first storage space, the method further comprises: invoking a first application programming interface (API) in an operating system; setting a bypass flag field in a page table entry of a page table of the first storage medium, wherein the bypass flag field is for storing the memory bypass flag; and adding, based on the access requirement recorded in the application, the memory bypass flag to the bypass flag field in the page table entry corresponding to the first storage space”.
However, in an analogous art in the same field of endeavor, Heil teaches setting a bypass flag field in a page table entry of a page table of the first storage medium, wherein the bypass flag field is for storing the memory bypass flag; and adding, based on the access requirement recorded in the application, the memory bypass flag to the bypass flag field in the page table entry corresponding to the first storage space (“To selectively bypass cache levels a page table entry (PTE) mechanism may be employed. To limit the number of PTE bits, the PTE may have a 2-bit ‘bypass type’ field among other attribute bits that index which bits of a Special Purpose Register (SPR) identify the cache levels to be bypassed.” Para 0013 and FIGS. 2A-B).
Given the teaching of Heil, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Roberts and Nakahara with “setting a bypass flag field in a page table entry of a page table of the first storage medium, wherein the bypass flag field is for storing the memory bypass flag; and adding, based on the access requirement recorded in the application, the memory bypass flag to the bypass flag field in the page table entry corresponding to the first storage space”. The motivation would be that system performance may be improved by selectively bypassing cache levels, para 0043 of Heil.
Roberts, Nakahara, and Heil may not explicitly disclose, but in an analogous art in the same field of endeavor, Kaminski teaches wherein before the obtaining the memory bypass flag corresponding to the first storage space, the method further comprises: invoking a first application programming interface (API) in an operating system (To modify a page table and release memory to an OS, a process invokes an API to release a block of memory back to the OS, para 0109).
Given the teaching of Kaminski, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Roberts, Nakahara, and Heil with “wherein before the obtaining the memory bypass flag corresponding to the first storage space, the method further comprises: invoking a first application programming interface (API) in an operating system”. The motivation would be that the API would allow removing page table entries from a page table, para 0109 of Kaminski, thereby improving the efficiency of the computing system.
As per dependent claim 4, Roberts in combination with Nakahara, Heil, and Kaminski discloses the method of claim 3. Roberts and Nakahara do not explicitly teach “wherein the invoking the first application programming interface (API) in the operating system and setting the bypass flag field in the page table entry of the page table of the first storage medium comprises: when the application applies to the operating system for allocating a storage space in the first storage medium or after the application completes applying for allocating the storage space, invoking the first API and setting the bypass flag field in the page table entry of the page table”.
However, Heil teaches and setting the bypass flag field in the page table entry of the page table (“To selectively bypass cache levels a page table entry (PTE) mechanism may be employed. To limit the number of PTE bits, the PTE may have a 2-bit ‘bypass type’ field among other attribute bits that index which bits of a Special Purpose Register (SPR) identify the cache levels to be bypassed.” Para 0013 and FIGS. 2A-B).
The same motivation that was utilized for combining Roberts and Heil as set forth in claim 3 is equally applicable to claim 4.
Roberts, Nakahara, and Heil may not explicitly disclose, but Kaminski teaches wherein the invoking the first application programming interface (API) in the operating system and setting the bypass flag field in the page table entry of the page table of the first storage medium comprises: when the application applies to the operating system for allocating a storage space in the first storage medium or after the application completes applying for allocating the storage space, invoking the first API (“the application may allocate a block of virtual memory where the data is read from disk. It may then process the data in place or it may copy the processed video file to another block in virtual memory. Using the DMA approach, the application will invoke an application programming interface (API) that will cause the OS or a device driver to pin the data block in physical memory, program the DMA controller and transfer the data between the physical memory and accelerator device.” Para 0008).
The same motivation that was utilized for combining Roberts and Kaminski as set forth in claim 3 is equally applicable to claim 4.
As per dependent claim 5, Roberts in combination with Nakahara, Heil, and Kaminski discloses the method of claim 3. Roberts and Nakahara may not explicitly disclose, but Heil teaches wherein the invoking the first application programming interface (API) in the operating system and setting the bypass flag field in the page table entry of the page table of the first storage medium comprises: in a process of compiling the application by a compiler, invoking the first API through a second API or a directive provided by the compiler, and setting the bypass flag field in the page table entry of the page table (“To selectively bypass cache levels a page table entry (PTE) mechanism may be employed. To limit the number of PTE bits, the PTE may have a 2-bit ‘bypass type’ field among other attribute bits that index which bits of a Special Purpose Register (SPR) identify the cache levels to be bypassed.” Para 0013 and FIGS. 2A-B).
The same motivation that was utilized for combining Roberts and Heil as set forth in claim 3 is equally applicable to claim 5.
As per dependent claim 6, Roberts in combination with Nakahara, Heil, and Kaminski discloses the method of claim 3. Roberts and Nakahara may not explicitly disclose, but Heil teaches wherein the adding, based on the access requirement recorded in the application, the memory bypass flag to the bypass flag field in the page table entry corresponding to the first storage space comprises: querying, based on the access requirement recorded in the application and a virtual address of the first storage space, the page table entry corresponding to the first storage space; and adding the memory bypass flag to the page table entry (“To selectively bypass cache levels a page table entry (PTE) mechanism may be employed. To limit the number of PTE bits, the PTE may have a 2-bit ‘bypass type’ field among other attribute bits that index which bits of a Special Purpose Register (SPR) identify the cache levels to be bypassed.” Para 0013 and FIGS. 2A-B. “A page table is the data structure used by a virtual memory system in a computer operating system to store the mapping between virtual addresses and physical addresses.” Para 0025).
The same motivation that was utilized for combining Roberts and Heil as set forth in claim 3 is equally applicable to claim 6.
As per dependent claims 14-15, these claims are respectively rejected based on arguments provided above for similar rejected dependent claims 3 and 6.
Claims 9-11 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Roberts in view of Nakahara and in further view of Heil.
As per dependent claim 9, Roberts in combination with Nakahara discloses the method of claim 7. Roberts and Nakahara may not explicitly disclose, but in an analogous art in the same field of endeavor, Heil teaches wherein the setting the memory bypass flag for the first storage space based on the predicted access requirement comprises: querying, based on the predicted access requirement and a physical address of the first storage space, a page table entry corresponding to the first storage space; and adding the memory bypass flag to the page table entry (“To selectively bypass cache levels a page table entry (PTE) mechanism may be employed. To limit the number of PTE bits, the PTE may have a 2-bit ‘bypass type’ field among other attribute bits that index which bits of a Special Purpose Register (SPR) identify the cache levels to be bypassed.” Para 0013 and FIGS. 2A-B).
Given the teaching of Heil, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Roberts and Nakahara with “wherein the setting the memory bypass flag for the first storage space based on the predicted access requirement comprises: querying, based on the predicted access requirement and a physical address of the first storage space, a page table entry corresponding to the first storage space; and adding the memory bypass flag to the page table entry”. The motivation would be that system performance may be improved by selectively bypassing cache levels, para 0043 of Heil.
As per dependent claim 10, Roberts in combination with Nakahara discloses the method of claim 1. Roberts and Nakahara may not explicitly disclose, but in an analogous art in the same field of endeavor, Heil teaches wherein the data processing request comprises a virtual address of the first storage space, and the obtaining, based on the data processing request, the memory bypass flag corresponding to the first storage space comprises: querying, based on a virtual address, a page table entry corresponding to the first storage space; and obtaining the memory bypass flag from the page table entry (“The bypass control bits may be used to "point" to a set of bits within a special purpose register that specify what levels, if any, of cache should be bypassed when accessing the data associated with the PTE.” Para 0034).
Given the teaching of Heil, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Roberts and Nakahara with “wherein the data processing request comprises a virtual address of the first storage space, and the obtaining, based on the data processing request, the memory bypass flag corresponding to the first storage space comprises: querying, based on a virtual address, a page table entry corresponding to the first storage space; and obtaining the memory bypass flag from the page table entry”. The motivation would be that system performance may be improved by selectively bypassing cache levels, para 0043 of Heil.
As per dependent claim 11, Roberts in combination with Nakahara and Heil discloses the method of claim 10. Roberts and Nakahara may not explicitly disclose, but Heil teaches wherein the querying, based on the virtual address, the page table entry corresponding to the first storage space comprises: querying, based on the virtual address, the page table of the first storage medium for the page table entry corresponding to the first storage space; or querying, based on the virtual address, a translation lookaside buffer (TLB) of a processor for the page table entry corresponding to the first storage space (“To selectively bypass cache levels a page table entry (PTE) mechanism may be employed. To limit the number of PTE bits, the PTE may have a 2-bit ‘bypass type’ field among other attribute bits that index which bits of a Special Purpose Register (SPR) identify the cache levels to be bypassed.” Para 0013 and FIGS. 2A-B. “A page table is the data structure used by a virtual memory system in a computer operating system to store the mapping between virtual addresses and physical addresses.” Para 0025).
The same motivation that was utilized for combining Roberts and Heil as set forth in claim 10 is equally applicable to claim 11.
As per dependent claims 17-18, these claims are respectively rejected based on arguments provided above for similar rejected dependent claims 9-10.
Conclusion
Another prior art reference Sharma et al. US 2023/0317145 (“Sharma”) was considered by the Examiner. Sharma was not applied in claim rejection, but the reference negates the patentability of the instant claimed invention.
For example, Sharma teaches “At reference 706, a first set of bits is written to the first array of the integrated circuit and a second set of bits is written to the second array of the integrated circuit upon determining the first set of bits is to be accessed more frequently than the second set of bits.” Paragraph [0092]. Sharma further teaches “an access frequency of each of the first and second sets of bits is determined based on a frequent value caching indication of the first and second sets of bits, and the first set of bits is written to the first array upon a determination that a corresponding frequent value caching indication of the first set of bits is set, and the second set of bits is written to the second array upon a determination that a corresponding frequent value caching indication of the second set of bits is not set.” Paragraph [0093]. Therefore, Sharma, in paragraphs [0092]-[0093], teaches against the patentability of the instant claimed invention.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ZUBAIR AHMED/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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