DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-7 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-13 of U.S. Patent No. 11289432 and 1-17 of U.S. Patent No.10032731. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-13 of U.S. Patent No. 11289432 and 1-17 of U.S. Patent No.10032731 disclose every limitation of claims 1-7 in the instant application.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated Ahn (PGPUB: 20090073078).
Regarding claims 1 and 4. Ahn teaches a radio frequency switch arrangement comprising:
a ground plane; a stack arranged in relation to the ground plane, the stack including a plurality of switching elements coupled in series with one another (see Fig. 4, paragraph 43 and 44, the receiver switch 404 may include stacked transistors 408, 410, 412, and 406, which may be complementary metal oxide semiconductor (CMOS) transistors, according to an example embodiment of the invention. The receiver switch 404 may further include capacitors 418, 420 . The transistor 408 may include a source 408a, a gate 408b, a drain 408c, and a body substrate 408d; a capacitor 418 may be provided between the source 408a and the gate 408b of the transistor 408. Likewise, the source 408a (or drain 408c) of the transistor 408 may be connected to its body substrate 408d. The drain 408c of transistor 408 may be connected to the source 410a of transistor 410 . In addition, the source 410a (or drain 410c) of transistor 410 may be connected to its body substrate 410d. The drain 410c of transistor 410 may be connected to the source 412a of transistor 412. Another external component such as a capacitor 420 may be positioned between the gate 412b and the drain 412c of transistor 412. Further, the body substrate 412a of the transistor 412 may be connected to the source 406a of the transistor 406. The drain 406c of the transistor 406 may be connected to ground); and
a plurality of capacitive elements, each of the plurality of capacitive elements providing a capacitive path across respective terminals of one of the plurality of switching elements (see Fig. 4, items 418 and 420).
Regarding claim 4. Ahn teaches the radio frequency switch arrangement of claim 1
wherein the ground plane comprises at least a portion of a semiconductor substrate (see Fig, 1 and 4, paragraph 56, with the receiver switch 404 in the ON state, the transmit switch 402 may be placed in the OFF (e.g., disabled, block) state to isolate the transmit switch 402 from the receiver switch 404. As shown in FIG. 4C, when the receiver switch 404 is in an ON state, the stacked transistor 406 may be placed in an OFF state 416, thereby providing an equivalent resistor between the body substrate 112d of transistor 412 and ground (i.e., body floating)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3, 5, and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ahn (PGPUB: 20090073078) in view of Kerr (PGPUB: 20140266415).
Regarding claim 2. Ahn does not expressly teach the radio frequency switch arrangement of claim 1
wherein the plurality of switching elements includes field effect transistors, wherein at least some of the field effect transistors are each coupled source-to-drain with one or more adjacent field effect transistors.
Kerr teaches that each field effect transistor (FET) in a stack of FETs making up either RF switch branch 10 or RF switch branch 12 that is in the off-state has an approximately equal part of a total RF voltage across the FET, and each FET acts as a nonlinear harmonic generator (see Fig. 1, paragraph 27); each of the plurality of series coupled harmonic cancellation circuits HC1-HC5 are coupled across a corresponding one of plurality of series coupled transistor switches M1-M5 making up the RF switch branch 24. An advantage of the configuration for the RF switch branch 24 is immunity to voltage stacking non-uniformity. Other combinations can also be used, such as two harmonic cancellation blocks per each transistor switch making up the RF switch branch 24 (see Fig. 4, paragraph 36).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Ahn by Kerr to obtain each field effect transistor (FET) in a stack of FETs making up either RF switch branch 10 or RF switch branch 12 that is in the off-state has an approximately equal part of a total RF voltage across the FET and each of the plurality of series coupled harmonic cancellation circuits HC1-HC5 are coupled across a corresponding one of plurality of series coupled transistor switches M1-M5 making up the RF switch branch 24, in order to provide wherein the plurality of switching elements includes field effect transistors, wherein at least some of the field effect transistors are each coupled source-to-drain with one or more adjacent field effect transistors. Therefore, combining the elements from prior arts according to known methods and technique would yield predictable results.
Regarding claim 3. The radio frequency switch arrangement of claim 1
wherein the plurality of switching elements includes at least one of diodes (see Fig. 5, paragraph 50, p-n junction diode 508a).
However, Ahn does not expressly teach wherein the plurality of switching elements includes at least one of field effect transistors, bipolar junction transistors, GaAs transistors, and micro-electromechanical devices.
The examiner is taking "Official Notice" that the limitation about wherein the plurality of switching elements includes at least one of field effect transistors, bipolar junction transistors, GaAs transistors, and micro-electromechanical devices is well known in the art.
Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to have modified Ahn so that wherein the plurality of switching elements includes at least one of field effect transistors, bipolar junction transistors, GaAs transistors, and micro-electromechanical devices would be available.
Regarding claim 5. Ahn does not expressly teach the radio frequency switch arrangement of claim 1
wherein the plurality of capacitive elements provide monotonically increasing or decreasing capacitance values across the stack.
Kerr teaches that an advantage of the configuration for the RF switch branch 24 is immunity to voltage stacking non-uniformity. Other combinations can also be used, such as two harmonic cancellation blocks per each transistor switch making up the RF switch branch 24; the capacitors, HC1-HC5, are connected in series and value of each varactor capacitor is set according harmonic signal and capacitance is increasing as number capacitors are increasing; an RF switch branch 28 includes a harmonic cancellation block 30 that is connected at two nodes within the RF switch branch 28. In particular, the plurality of series coupled harmonic cancellation circuits HC1-HC5 are coupled across only a portion of the plurality of series coupled transistor switches M1-M5 excluding ones of the plurality of series coupled transistor switches M1-M5 adjacent to a first port RFA and a second port RFB, which in this case excludes transistor switch M1 and transistor switch M5, respectively (see Fig. 4, paragraph 36 and 38).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Ahn by Kerr to obtain the capacitors, HC1-HC5, are connected in series and value of each varactor capacitor is set according harmonic signal and capacitance is increasing as number capacitors are increasing, in order to provide wherein the plurality of capacitive elements provide monotonically increasing or decreasing capacitance values across the stack. Therefore, combining the elements from prior arts according to known methods and technique would yield predictable results.
Regarding claim 7. The radio frequency switch arrangement of claim 1
wherein each of at least some of the plurality of capacitive elements provide a respective lateral capacitance between a drain and a source of a corresponding field effect transistor utilized as switching element.
Kerr teaches that harmonic cancellation circuits such as the disclosed improved harmonic cancellation circuits 16 (FIG. 2B), 18 (FIG. 2C), 20 (FIG. 3A), and 22 (FIG. 3B) are represented by varactor symbols HC1-HC5. The gate bias resistors R.sub.G and body bias resistors R.sub.B are omitted for clarity. In FIG. 4A, the same voltage that causes an RF switch branch 24 to generate an H3 signal is coupled to a harmonic cancellation block 26 made up of a plurality of series coupled harmonic cancellation circuits HC1-HC5. Each of the plurality of series coupled harmonic cancellation circuits HC1-HC5 are coupled across a corresponding one of plurality of series coupled transistor switches M1-M5 making up the RF switch branch 24. An advantage of the configuration for the RF switch branch 24 is immunity to voltage stacking non-uniformity. Other combinations can also be used, such as two harmonic cancellation blocks per each transistor switch making up the RF switch branch 24 (see Figs 4A, 4B, and 4C, paragraph 36).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Ahn by Kerr to obtain an RF switch branch 24 to generate an H3 signal is coupled to a harmonic cancellation block 26 made up of a plurality of series coupled harmonic cancellation circuits HC1-HC5. Each of the plurality of series coupled harmonic cancellation circuits HC1-HC5 are coupled across a corresponding one of plurality of series coupled transistor switches M1-M5 making up the RF switch branch 24, in order to provide wherein each of at least some of the plurality of capacitive elements provide a respective lateral capacitance between a drain and a source of a corresponding field effect transistor utilized as switching element. Therefore, combining the elements from prior arts according to known methods and technique would yield predictable results.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ahn (PGPUB: 20090073078) in view of Kerr (PGPUB: 20140266415). And further in view of Lin (PGPUB: 20110214912).
Regarding claim 6. Ahn does not expressly teach the radio frequency switch arrangement of claim 1
wherein at least some of the plurality of capacitive elements are formed with an excess of vias and metal available in a semiconductor manufacturing process.
Lin teaches that a multi-layer PCB 200 includes one or more closed, or partially closed, geometric structures formed on inner substrates of the multi-layer PCB to enclose a via structure 210. Additionally, these one or more closed, or partially closed, gemortric structure may be formed on outer substrates of the multi-layer PCB to enclose the via structure 210 (see Fig. 2, paragraph 37); the equivalent capacitance CEQ of the via structure 210 is less than the capacitance of the conventional via structure 110. As a result, the via structure 210 effectively increases the power levels of the signals passing through the via structure 210 as well as decreasing the reflections of these signals back through the conductive pathway 208 and/or the conductive pathway 212 at higher frequencies (see Fig. 2, paragraph 49); several substrates 102 through 106, each with their own conductive pathways, may be bonded together, typically with an epoxy resin prepreg, to form a conventional multi-layer PCB 100. The conventional multi-layer PCB 100 may include any number of substrates 104.1 through 104.n, also referred to as inner substrates, or it may not include any of the substrates 104.1 through 104.n. The conductive pathways foamed onto one substrate may be connected to the conductive pathways formed onto other substrates using via structures. Holes are typically drilled from one substrate to another substrate then filled and/or plated with conductive material to form the via structure. For example, a conductive pathway 108 may be connected to a conductive pathway 112 by drilling a hole through the substrates 102 through 106 then plating the hole with copper, or any other suitable metal, to form a conventional via structure 110 (see Fig. 1, paragraph 28).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination by Lin for providing that the equivalent capacitance CEQ of the via structure 210 is less than the capacitance of the conventional via structure 110. As a result, the via structure 210 effectively increases the power levels of the signals passing through the via structure 210 as well as decreasing the reflections of these signals back through the conductive pathway 208 and/or the conductive pathway 212 at higher frequencies and a conductive pathway 108 may be connected to a conductive pathway 112 by drilling a hole through the substrates 102 through 106 then plating the hole with copper, or any other suitable metal, to form a conventional via structure 110, as wherein at least some of the plurality of capacitive elements are formed with an excess of vias and metal available in a semiconductor manufacturing process. Therefore, combining the elements from prior arts according to known methods and technique would yield predictable results.
Conclusion
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/XIN JIA/Primary Examiner, Art Unit 2663
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