DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 45 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nie (US 2018/0211600).
In regard to claim 45, Nie teaches an electronic apparatus comprising: a display panel in which a plurality of pixels are arranged (paragraph 66, AMOLED display); and a controller output a control signal to the display panel (paragraph 77), wherein each of the plurality of pixels comprises: a light emitting diode (D1); a first transistor (T1); a second transistor comprising a first terminal connected to a gate of the first transistor (T2 connected to BG through C1), a second terminal connected to a data line and a gate connected to a first gate line (data and scan 2); a third transistor comprising a first terminal connected to the gate of the first transistor, a second terminal connected to a first voltage line and a gate connected to a second gate line (T3 and Vpre); a fourth transistor comprising a first terminal connected to a second terminal of the first transistor, a second terminal connected to the light emitting diode and a gate connected to a third gate line (T6 connected to Scan 3 and D1 through T1); a fifth transistor comprising a first terminal connected to the fourth transistor, a second terminal connected to a second voltage line and a gate connected to a fourth gate line (T5 connected to ground through C2 and a separate Scan 2 line); a sixth transistor (T4) comprising a first terminal connected to a third voltage line (VDD, the entire device is connected together. Any element in the pixel is connected to any other element), a second terminal connected to a first terminal of the first transistor (Scan 4 is connected to node D) and a gate connected to a fifth gate line (Scan 1); a first capacitor comprising a first electrode connected to the gate of the first transistor and a second electrode connected to the second terminal of the first transistor (C1, the entire device is connected); and a second capacitor comprising a first electrode connected to the third voltage line and a second electrode connected to the second terminal of the first transistor (C2), wherein the first transistor further comprises a second gate connected to the second electrode of the first capacitor and the second electrode of the second capacitor (fig. 1 T1 and paragraph 90).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 48, 49 and 51 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nie in view of Huangfu et al. (US 2020/0043990).
In regard to claim 48, Nie teaches all the elements of claim 46 except wherein the plurality of pixels comprise a first pixel emitting light in a first color and a second pixel emitting light in a second color, wherein the light emitting diode of the first pixel is connected to the pixel circuit of the first pixel through a first via hole, and the light emitting diode of the second pixel is connected to the pixel circuit of the second pixel through a second via hole.
Huangfu et al. teach wherein the plurality of pixels comprise a first pixel emitting light in a first color and a second pixel emitting light in a second color (paragraph 9), wherein the light emitting diode of the first pixel is connected to the pixel circuit of the first pixel through a first via hole, and the light emitting diode of the second pixel is connected to the pixel circuit of the second pixel through a second via hole (fig. 7 and fig. 10. Huangu et al. show the anode of each pixel is connected to the circuit through the via hold 35).
The two are analogous art because they both deal with the same field of invention of displays.
Before the effective filing date it would have been obvious to one of ordinary skill in the art to provide the apparatus of Nie with the circuit of Huangfu et al. The rationale is as follows: Before the effective filing date it would have been obvious to provide the apparatus of Nie with the circuit of Huangfu et al. because the pixel arrangement of Huangfu et al. would allow for high pixel density and would work equally as well as the pixel arrangement of Nie.
In regard to claim 49, Nie teaches a pixel defining layer (element 50 and paragraph 117), wherein the pixel defining layer has a first opening corresponding to a first emission area of the light emitting diode of the first pixel and a second opening corresponding to a second emission area of the light emitting diode of the second pixel (fig. 7 and paragraph 117).
In regard to claim 51, Nie teaches wherein the pixel defining layer overlaps the first via hole and the second via hole in a plan view (fig. 7).
Allowable Subject Matter
Claims 32-44 are allowed.
Claims 46, 47 and 50 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: In regard to claims 33-44, the prior art fails to teach or make obvious, in combination with the claim’s other features “wherein the light emitting diode of the first pixel and the light emitting diode of the second pixel are arranged adjacent to each other in a second direction perpendicular to the first direction, and wherein the first transistor further comprises a second gate connected to the second electrode of the first capacitor and the second electrode of the second capacitor.”
In regard to claims 46 and 47, the prior art fails to teach or make obvious, in combination with the claim’s other features “a second period in which the third transistor and the sixth transistor are turned on and the fourth transistor is turned off, the second period following the first period; and a write period in which the second transistor is turned on, the writing period following the second period.”
In regard to claim 50, the prior art fails to teach or make obvious, in combination with the claim’s other features “wherein the first opening and the second opening are adjacent to in an extension direction of the data line, and wherein the first via hole and the second via hole are between the first opening and the second opening in the extension direction of the data line in a plan view.”
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH R HALEY whose telephone number is (571)272-0574. The examiner can normally be reached 7:30am-5pm.
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/JOSEPH R HALEY/Primary Examiner, Art Unit 2621
