Prosecution Insights
Last updated: July 17, 2026
Application No. 18/983,513

POWER FACTOR CORRECTION (PFC) CIRCUITS

Non-Final OA §102§103
Filed
Dec 17, 2024
Examiner
NOVAK, PETER MICHAEL
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
NXP Semiconductors N.V.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
5m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
614 granted / 695 resolved
+20.3% vs TC avg
Moderate +9% lift
Without
With
+8.6%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
37 currently pending
Career history
724
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
75.3%
+35.3% vs TC avg
§102
4.0%
-36.0% vs TC avg
§112
15.6%
-24.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 695 resolved cases

Office Action

§102 §103
CTNF 18/983,513 CTNF 91503 DETAILED ACTION The instant action is in response to application 17 Dec 2024. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Specification 06-31 AIA The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification. Priority Acknowledgment is made of applicant's claim for priority to 17 December 2024. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. For method claims, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated. (The claims have been condensed.) 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim (s) 1-4, 8-12, 15-18 are rejected under 35 U.S.C. 102( a)(1) and 102 (a)(2 ) as being anticipated by Chin (US 20240014733) . As to claim 1, Chin discloses A power supply (Fig. 3), comprising: a power converter having a high-side switch (S1), a low-side switch (S2)coupled to the high-side switch, and a bootstrap capacitor (Fig. 3, Cqbst) coupled between the high-side switch and the low-side switch; and a control circuit (Fig. 3, the supply voltage, REG is connected to S2 and S1, as well as item generating gate signals) coupled to the low-side switch, the control circuit configured to activate the low-side switch and charge the bootstrap capacitor without changing an output voltage of the power converter (Vreg is tied to the driver and the switching node, which is similar to applicant’s invention). As to claim 2, Chin discloses wherein the bootstrap capacitor is coupled in series with a diode (the circuit shows a series combination of a diode, resistor, and bootstrap capacitor). As to claim 3, Chin discloses wherein the diode is coupled to a voltage source (REG), and wherein the bootstrap capacitor is coupled between the high-side and low-side switches. As to claim 4, Chin teaches wherein the control circuit is configured to activate the low-side switch to charge the bootstrap capacitor while the high-side switch is turned off (S1/S2 switch complimentarys, See figures 2a-2d). As to claim 8, Chin discloses wherein the control circuit is configured to activate the low-side switch for one or more switching cycles (this is shown in Figs 2a-2d). As to claim 9, Chin discloses wherein the control circuit is configured to activate the low-side switch following a selected pattern of switching cycles (Figs. 2a- 2d). As to claim 10, Chin discloses further comprising an inductor (Fig. 3, L) coupled between the high and low-side switches, wherein the control circuit is configured to turn the low-side switch off before the inductor accumulates sufficient energy to change the output voltage of the power converter. As to claim 11, Chin discloses An electronic circuit, comprising: a power converter having a high-side switch, a low-side switch coupled to the high-side switch, an output capacitor coupled across the high-side and low-side switches, and a bootstrap capacitor coupled between the high-side low-side switches; and a control module coupled to the power converter, wherein the control module is configured to activate the low-side switch to opportunistically charge the bootstrap capacitor without increasing an electrical charge across the output capacitor (this is similar to claim 1, with the only difference being applicant specifying an output voltage rather than capacitor voltage. However, the capacitor voltage and the output voltage are the same, so this is anticipated for similar reasons). As to claim 12, Chin teaches wherein the control circuit is configured to activate the low-side switch to charge the bootstrap capacitor while the high-side switch is turned off (S1/S2 switch complimentarys, See figures 2a-2d). As to claim 15, Chin discloses wherein the control circuit is configured to activate the low-side switch for one or more switching cycles (this is shown in Figs 2a-2d). As to claim 16, Chin discloses wherein the control circuit is configured to activate the low-side switch following an alternating pattern of switching cycles (Figs. 2a- 2d). As to claims 17-18 theres are method claims corresponding to apparatus claims 11 and 16, just with fewer limitations. As such, these are anticipated for similar reasons per MPEP 2112.02 Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 5, 13 are rejected under 35 U.S.C. 103 as being unpatentable over Chin (US 20240014733) in view of Kolar (US 20220085725) As to claim 5, Chin does not disclose wherein the control circuit is configured to activate the low-side switch to charge the bootstrap capacitor in response to a mains voltage reaching its negative peak. Kiolar teaches wherein the control circuit is configured to activate the low-side switch to charge the bootstrap capacitor in response to a mains voltage reaching its negative peak (¶134 “ii) statically operating the bridge leg that receives the minimum input voltage Umin includes switching off the high-side switch of the respective bridge leg and switching on the low-side switch of the respective bridge leg.”). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to activate the low side switches at an input minimum as disclosed in Kilar to improve DC voltage regulation. As to claim 5, Chin does not disclose wherein the control circuit is configured to activate the low-side switch to charge the bootstrap capacitor in response to a mains voltage reaching its negative peak. Kiolar teaches wherein the control circuit is configured to activate the low-side switch to charge the bootstrap capacitor in response to a mains voltage reaching its negative peak (¶134). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to activate the low side switches at an input minimum as disclosed in Kilar to improve DC voltage regulation . 07-21-aia AIA Claim s 6-7, 14, 19, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chin (US 20240014733) in view of Lind (US 20220158559) . As to claim 6, Chin does not disclose wherein the control circuit is configured to activate the low-side switch in response to the power supply operating in burst mode, a non-switching mode, or a low frequency switching mode. Lind teaches wherein the control circuit is configured to activate the low-side switch in response to the power supply operating in burst mode, a non-switching mode, or a low frequency switching mode (¶95 “It will be appreciated that other embodiments can also be implemented alternately to the fixed frequency DCM operation associated with low frequencies. For example, switching operation strategies may involve transitions into CrCM bursts (x cycles of switching and then y cycles of no switching), or DCM bursts or similar modes.”) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use DCM to improve light load efficiency. As to claim 7, Chin in view of Lind teaches wherein the control circuit is configured to activate the low-side switch in response to receiving a mode active signal (Lind, Fig. 2a/2b). As to claim14, Chin does not disclose wherein the control circuit is configured to activate the low-side switch in response to the power supply operating in burst mode, a non-switching mode, or a low frequency switching mode. Lind teaches wherein the control circuit is configured to activate the low-side switch in response to the power supply operating in burst mode, a non-switching mode, or a low frequency switching mode (¶95). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use DCM to improve light load efficiency. As to claim 19, Chin does not explicitly teach wherein the selected mode of operation comprises a burst mode. Lind teaches wherein the selected mode of operation comprises a burst mode(¶95). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use burst mode and DCM to improve light load efficiency. As to claim 20, Chin does not teach wherein the selected mode of operation comprises a non-switching mode or a low frequency switching mode. Lind teaches wherein the selected mode of operation comprises a non-switching mode or a low frequency switching mode. (¶95). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use burst mode and DCM to improve light load efficiency. Conclusion Examiner has cited particular column, paragraph, and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention. Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M NOVAK whose telephone number is (571)270-1375. The examiner can normally be reached on 9AM-5PM,Monday through Thursday, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal Hammond can be reached on 571-270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PETER M NOVAK/ Primary Examiner, Art Unit 2839 Application/Control Number: 18/983,513 Page 2 Art Unit: 2838 Application/Control Number: 18/983,513 Page 3 Art Unit: 2838 Application/Control Number: 18/983,513 Page 4 Art Unit: 2838 Application/Control Number: 18/983,513 Page 5 Art Unit: 2838 Application/Control Number: 18/983,513 Page 6 Art Unit: 2838 Application/Control Number: 18/983,513 Page 7 Art Unit: 2838
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Prosecution Timeline

Dec 17, 2024
Application Filed
Jun 17, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
97%
With Interview (+8.6%)
2y 0m (~5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 695 resolved cases by this examiner. Grant probability derived from career allowance rate.

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