Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application is a continuation under 35 U.S.C. 120 of Application Serial No. 18/083,735 filed December 19, 2022, now U.S. Patent No. 12,204,448 B2, which claims foreign priority under 35 U.S.C. 119 from United Kingdom Application No. 2118450.2 filed December 17, 2021. Claims 1-20 are pending for examination.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/17/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,204,448 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the differences between claims 1-20 of instant application and claims 1-18 of patent 12,204,448 B2 are not sufficient to render the claim patentably distinct (claim 1 of the instant application and patent 12,204,448 B2 both claimed the core limitations: processing a first work item and a second work item through a processing pipeline; and determining that the first and second work items are associated with the same memory address; wherein the processing of the first work item comprises writing first updated data to a register in the processing logic instead of writing updated data to a memory of the computing system; and wherein the processing of the second work item comprises reading the first updated data from the register instead of reading data from the memory. However, the limitations of the instant application are anticipated by the patent 12,204,448 B2.
The following table only compares claim 1 of instant application to claim 1 of the patent 12,204,448 B2.
Instant application 18/983,633
Patent 12,204,448 B2
A method of processing a plurality of work items in processing logic of a computing system, the method comprising:
A method of processing a plurality of work items in processing logic of a computing system, wherein the computing system comprises a memory, and wherein each of the work items is associated with a memory address in the memory, wherein the plurality of work items are processed through a processing pipeline comprising a plurality of stages in the processing logic, wherein at a given time different work items are at different stages of the pipeline, wherein the processing of a work item comprises: (i) reading data in accordance with the memory address associated with the work item, (ii) updating the read data, and (iii) writing the updated data in accordance with the memory address associated with the work item, the method comprising:
processing a first work item and a second work item through a processing pipeline; and
processing a first work item and a second work item through the processing pipeline, wherein the processing of the first work item through the pipeline is initiated earlier than the processing of the second work item; and
determining that the first and second work items are associated with the same memory address;
determining that the first and second work items are associated with the same memory address;
wherein the processing of the first work item comprises writing first updated data to a register in the processing logic instead of writing updated data to a memory of the computing system; and
wherein the processing of the first work item comprises writing first updated data to a register in the processing logic instead of writing updated data to the memory; and
wherein the processing of the second work item comprises reading the first updated data from the register instead of reading data from the memory
wherein the processing of the second work item comprises reading the first updated data from the register instead of reading data from the memory
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 9-10, 14-17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over MULLER et al., US 2021/0109760 A1, in view of Xia et al., US 2021/0096901 A1.
Regarding claims 1, 14 and 20, MULLER teaches a method of processing a plurality of work items (section 0075; a vector in this sense means an item of data that comprises multiple individual elements) in processing logic of a computing system (Fig.1 and claim 1), the method comprising:
processing a first work item and a second work item through a processing pipeline (Fig.1 and Fig.2; section 0050; The main processor 101 comprises a first pipeline 104 comprising a series of pipeline stages M1 . . . M5) ; and
wherein the processing of the first work item comprises writing first updated data to a register in the processing logic instead of writing updated data to the memory (section 0107; stage C6 writes to the co-processor register file 206); and
wherein the processing of the second work item comprises reading the first updated data from the register instead of reading data from the memory (section 0107; stage C2 reads/writes to the memory 102 and reads from the co-processor register file 206).
MULLER does not clearly teach determining that the first and second work items are associated with the same memory address.
However, Xia teaches determining that the first and second work items are associated with the same memory address (claim 2 of Xia; writing one or more work items into one or more locations in the shared memory).
It would have been obvious to the ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings Xia into MULLER such as determining that the first and second work items are associated with the same memory address because the shared memory may include one or more flags or one or more lists to allow the front end to control the behavior of the back end virtual IRQ forwarding logic without causing the back end to stop its existing processes (see abstract of Xia).
Regarding claim 2, MULLER teaches the work items to be processed are rays that are used to perform ray tracing (Fig.1a and section 0062; it is taught as a pipelined memory where memory access is divided into two stages).
Regarding claim 3, MULLER teaches the memory is a random-access memory (RAM) (section 0064; it is taught as data memory 102 where the data to be operated upon by computations and the results of the computations are ultimately stored).
Regarding claim 4, MULLER teaches the processing pipeline comprises three stages, wherein each of the stages is executed over a respective clock cycle (section 0055; performing stages of the pipeline on each processor clock cycle).
Regarding claim 5, MULLER teaches the processing of the second work item further comprises writing second updated data to the register (section 0107; stage C6 writes to the co-processor register file 206).
Regarding claim 6, MULLER teaches the processing of the second work item, including the reading of the first updated data from the register and the writing of the second updated data to the register, is executed over a single clock cycle (section 0081; in the case of a single combined memory access stage performing both addressing and read/write stage in a single cycle).
Regarding claim 9, MULLER teaches further comprising writing the data stored in the register to the memory (section 0080; The result can subsequently be stored from the co-processor register file 206 to the shared data memory 102 by a subsequent co-processor store instruction which acts on the co-processor memory stage(s) C1, C2).
Regarding claim 10, MULLER teaches the data stored in the register is written to a line of the memory at the memory address with which the first and second work items are associated (section 0080 and 0090; The co-processor 201 can be configured to operate on wider units of data than the main processor. That is to say, the memory access stage C2 in the co-processor pipeline 104 has a wider interface to the data memory 102 (can access a larger word per cycle) compared to that of the memory access stage M5 in the main pipeline 104; and the internal registers of the compute stage(s) C3, C4 of the co-processor 204 are wider (can hold longer words) that that/those M3 in the main pipeline 104. In embodiments at least some of the registers in the co-processor register file 206 are also wider than any of the operand registers in the main processor's register file 106).
Regarding claim 15, MULLER teaches the computing system is a ray tracing system (Fig.1a and section 0062; it is taught as a pipelined memory where memory access is divided into two stages).
Regarding claim 16, MULLER teaches the register is the same width as a line of the memory (section 0068; it can have a select few registers that are as wide as the memory and that can hold, for example, vector data).
Regarding claim 17, MULLER teaches the register is a first register, and the processing logic further comprises a second register (Fig.3; co-processor registers 206 and thread registers 106).
Allowable Subject Matter
Claims 7-8, 11-13, 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
The limitations not found in the prior art of record include processing a third work item associated with the same memory address as the first and second work items, the processing of the third work item through the pipeline being initiated later than the processing of the second work item, wherein processing the third work item comprises reading the second updated data from the register instead of reading data from the memory and writing third updated data to the register instead of writing data to the memory in combination with the other claimed limitations as described in the claim 7 (claim 8 is depended on claim 7).
The limitations not found in the prior art of record include the data stored in the register is written to the memory in response to determining that the processing of another work item, which is associated with a different memory address to the memory address with which the first and second work items are associated, is to write data to the register, further comprising overwriting the register with updated data from the processing of said another work item in combination with the other claimed limitations as described in the claims 11.
The limitations not found in the prior art of record include the register is a first register, and the method further comprises: processing a first further work item and a second further work item through the processing pipeline, wherein the processing of the first further work item through the pipeline is initiated earlier than the processing of the second further work item; and determining that the first further work item and the second further work item are associated with the same memory address, that memory address being different from the memory address with which the first and second work items are associated; wherein the processing of the first further work item comprises writing first further updated data to a second register in the processing logic; and wherein the processing of the second further work item comprises reading the first further updated data from the second register instead of reading data from the memory in combination with the other claimed limitations as described in the claims 12 and 18.
The limitations not found in the prior art of record include storing indications of the memory addresses associated with the work items that are currently in the processing pipeline, wherein the determination that the first and second work items are associated with the same memory address is made by comparing the stored indications of the memory addresses in combination with the other claimed limitations as described in the claims 13 and 19.
When responding to the office action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111 (c).
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/HUA J SONG/Primary Examiner, Art Unit 2133