Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
This is in response to communications filed on 12/17/24.
Claim Interpretation
The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent is not met. If the condition for performing a contingent step is not satisfied, the performance recited by the step need not be carried out in order for the claimed method to be performed. See Ex Parte Schulhauser. For example, assume a method claim requires step A if a first condition happens and step Bif a second condition happens. If the claimed invention may be practiced without either the first or second condition happening, then neither step A nor B is required by the broadest reasonable interpretation of the claim. If the claimed invention requires the first condition to occur, then the broadest reasonable interpretation of the claim requires step A. If the claimed invention requires both the first and second conditions to occur, then the broadest reasonable interpretation of the claim requires both steps A and B (MPEP 2111.04).
Claim 16 is a method claim that recite the conditional limitations “in response to the state indicators exceeding a state threshold”, which not a required condition to be occurred (i.e., state indicator may not exceed the state threshold). Thus, BRI does not include the condition and the functions based on the conditions when method can be practiced without conditions being met. For compact prosecution, the limitations are addressed as described below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 11 and claim 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites “the accepted response signals”, which lack antecedent basis. Claim 1 (the parent claim) recite “accepted response signal for each response type” and therefore, it is not clear whether the accepted response signals correspond to multiple response signal types or one response type indicated in claim 1.
Claim 20 recites “the method of claim 15”. However, claim 15 does not recite any method. Claim 15 is a system claim, not a method claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 10-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Naveh et al (US Patent Application Publication 2022/0413582; cited in IDS).
For claim 1, Naveh et al teach the following limitations: An integrated circuit (IC) (300 in Fig 3; [0033] – dies of 102 and 118 are vertically packaged in an integrated semiconductor device 140) comprising a power management circuit (PDP 416 , PMIC 118 and global module 414 in Fig 4); configured to: generate state indicators indicating respective states of logic circuits in an IC ([0085] – power samples are collected from power sensors and preprocessed at the global module 414; [0054]-[0057] sensors provides the states of the logic circuits); in response to the state indicators exceeding a state threshold (various thresholds for temperature, current and power are mentioned in [0039][0040][0041][0057][0059][0062] Fig 5 and other sections), generate suggested response signals ([0060] – 414/416 receives thresholds to do the throttle signals; current control signal is mentioned in [0065] to control current; thermal control is mentioned in [0039]; [0039][0040] – enable power control operations according to power budgets; thus power budget generation (P-state) is a suggested response signal; [0063] mentions global power control operation includes what throttling operations to take on individual domains; [0065] – current control signal is generated to request reduction in current; therefore, suggested response signal are generated) that each have a corresponding magnitude and a corresponding response signal type ([0039] mentions two response signals - thermal response with 500 microsec as first rate of global control and thermal response with 100 microsec as second rate of local control; the response signal type is “thermal response” and the magnitude is “500” or response signal type is “thermal response” and the magnitude is “100”; the type can be “current control” [0041][0057]; each response type (i.e., temperature or current control) has associated temporal lengths as mentioned in [0063] as rate, Fig 5 – represents the magnitude for the response signals; Fig 5C – each power control operation has it’s own rate of temporal length or the magnitude); and for each response signal type: determine a greatest magnitude among magnitudes of the corresponding suggested response signals ([0039] mentions first rate and second rate and determines second rate of local power control is faster; [0069] temperature response loop control time constant is determined; [0070] – long control loop and short control loop are determined; thus the fast responses temporal length is determined); generate an accepted response signal having the greatest magnitude ([0069] – [0080] – power burst and temperature response are addressed by the local power control operation with shorter power control loop; [0082] – “hard throttling” is triggered at a faster rate than soft throttling; [0099] – soft or hard throttling can be applied for temperature or power burst based on an urgency level; thus, based on urgency the response signal having the fastest/slowest response (i.e., greatest magnitude) is selected to generate the accepted response signal); and provide the accepted response signal to a response circuit that corresponds to the response signal type ([0057][0060][0066] mentions various throttling corresponding to temperature, current or power and the circuits such as clock, voltage regulators) and is configured to reduce at least one of the state indicators exceeding the state threshold ([0040][0041[0073] [0099][0100] [0116] mention that the current, temperature and power are controlled below the predefined upper limit).
For claim 2, Naveh teaches wherein the power management circuit is further configured to: generate an aggregated activity indicator from aggregated indications of activity in each of a plurality of logic circuits; and generate the state indicators based on the aggregated activity indicator ([0057] [0068][0076] [0085] mention calculating average power sample averaged over a plurality of samples for individual domain; thus domain level activity is aggregated from logic blocks’ aggregated activity indications to generate the state indicators of the domains, clusters or circuits).
For claim 3, response circuit is not part of IC. BRI does not include the elements of the response circuit. However, Naveh teaches wherein for each response signal type, the response circuit comprises one of the logic circuits, a clock control circuit, or a voltage control circuit ([0066] – voltage regulator; clock controller and traffic blocker circuits for power, temperature and current types in [0005]).
For claim 4, Naveh teaches wherein the power management circuit is further configured to provide the accepted response signal for at least two of the response signal types to the corresponding response circuits in parallel ([0100] – temperature type, power consumption type and current type can be monitored and controlled jointly. Thus, the accepted response signal can correspond to two response signal type in parallel).
For claim 5, Naveh teaches the power management circuit further comprises a plurality of state tracker circuits configured to generate, based on the aggregated activity indicator, the state indicators indicating a plurality of states in the plurality of logic circuits ([0057][0060] [0068][0076] [0085] mention that 408, 414, 406 perform the averaging and [0057] [0060][0063] mentions that 416 and 414 perform the processing with average power sample; thus, 414 and 416 generates state indicators) .
For claim 6, Naveh teaches wherein each of the plurality of state tracker circuits is programmable to generate one or more of the suggested response signals, each having a response signal type of a plurality of response signal types ([0060] – 414/416 generates the throttle signals; current control signal is mentioned in [0065] to control current; [0039][0040] – temperature control and enable power control operations according to power budgets; thus power budget generation (P-state) is a suggested response signal; [0063] mentions global power control operation includes what throttling operations to take on individual domains; therefore, suggested response signals are generated by 414 and 416).
For claim 7, Naveh teaches wherein the plurality of state tracker circuits is configured to generate, based on the aggregated activity indicator, the state indicators indicating two or more of a rate of change of current (di/dt), average power consumption of the plurality of logic circuits in a first time period, average current provided to the plurality of logic circuits in a second time period, total power consumption of the plurality of logic circuits in a third time period, rate of temperature change, and temperature (temperature is mentioned in [0039] [0073]; [0081]- rate of temperature (i.e., temperature difference over a period represents the rate); [0097][0100] – current and power as these samples are averaged in [0068][0085] – the power and current values are average value over a period).
For claim 10, Naveh teaches wherein the accepted response signals comprise a throttle signal to throttle the activity in the plurality of logic circuits (accepted signal is either “soft throttling” or “hard throttling” [0099]).
For claim 11, Naveh teaches wherein the accepted response signals comprise: a first cluster power signal to a first cluster-level power control circuit providing a first power signal to the plurality of logic circuits; and a second cluster power signal to a second cluster-level power control circuit providing a second power signal to the plurality of logic circuits ([0100] mention that different types of temperature, power consumption and current can be controlled jointly; [0066] [0079][0087][0099] – one or more of throttling which requires one or more of power signal including a first cluster power signal and second cluster power signal).
For claim 12, Naveh teaches wherein the accepted response signals comprise: a clock control signal to a clock control circuit providing a clock signal to the plurality of logic circuits; and a power control signal to a cluster-level power control circuit providing a power signal to the plurality of logic circuits ([0100] mention that different types of temperature, power consumption and current can be controlled jointly; [0066] [0079][0087][0099] – one or more of throttling which requires one or more of power signal including a first cluster power signal and second cluster power signal; [0065] mentions current control signal and [0099] mentions power burst control; performance point throttling include clock throttling).
For claim 13, Naveh teaches wherein the accepted response signals comprise: a firmware control signal to trigger a firmware response; and an IC power signal to an IC power circuit (Fig 5C shows the firmware control signal to trigger firmware response and HW signal or IC power signal; [0040]).
For claim 14, Naveh teaches wherein the plurality of logic circuits comprises a plurality of processor cores and a cache memory circuit (Fig 2).
For claim 15, Naveh teaches the IC integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; a drone; and a multicopter (Fig 1-2 shows the system, which is a processor based system or a computer)
For claim 16, Naveh et al teach the following limitations: A method of a power management circuit (PDP 416 , PMIC 118 and global module 414 in Fig 4) in an integrated circuit (IC) (300 in Fig 3; [0033] – dies of 102 and 118 are vertically packaged in an integrated semiconductor device 140), the method comprising: generating state indicators that each indicate one of a plurality of states of a plurality of logic circuits in an IC ([0085] – power samples are collected from power sensors and preprocessed at the global module 414; [0054]-[0057] sensors provides the states of the logic circuits; the samples corresponds to plural states of current, power, temperature [0054]); in response to the state indicators exceeding a state threshold (various thresholds for temperature, current and power are mentioned in [0039][0040][0041][0057][0059][0062] Fig 5 and other sections), generating suggested response signals ([0060] – 414/416 receives thresholds to do the throttle signals; current control signal is mentioned in [0065] to control current; thermal control is mentioned in [0039]; [0039][0040] – enable power control operations according to power budgets; thus power budget generation (P-state) is a suggested response signal; [0063] mentions global power control operation includes what throttling operations to take on individual domains; [0065] – current control signal is generated to request reduction in current; therefore, suggested response signal are generated), wherein each suggested response signal has a corresponding magnitude and a corresponding response signal type ([0039] mentions two response signals - thermal response with 500 microsec as first rate of global control and thermal response with 100 microsec as second rate of local control; the response signal type is “thermal response” and the magnitude is “500” or response signal type is “thermal response” and the magnitude is “100”; the type can be “current control” [0041][0057]; each response type (i.e., temperature or current control) has associated temporal lengths as mentioned in [0063] as rate, Fig 5 – represents the magnitude for the response signals; Fig 5C – each power control operation has it’s own rate of temporal length or the magnitude); and for each response signal type: determining a greatest magnitude among magnitudes of the corresponding suggested response signals ([0039] mentions first rate and second rate and determines second rate of local power control is faster; [0069] temperature response loop control time constant is determined; [0070] – long control loop and short control loop are determined; thus the fast responses temporal length is determined); generating an accepted response signal having the greatest magnitude ([0069] – [0080] – power burst and temperature response are addressed by the local power control operation with shorter power control loop; [0082] – “hard throttling” is triggered at a faster rate than soft throttling; [0099] – soft or hard throttling can be applied for temperature or power burst based on an urgency level; thus, based on urgency the response signal having the fastest/slowest response (i.e., greatest magnitude) is selected to generate the accepted response signal); and providing the accepted response signal to a response circuit that corresponds to the response signal type ([0057][0060][0066] mentions various throttling corresponding to temperature, current or power and the circuits such as clock, voltage regulators) and is configured to reduce at least one of the state indicators exceeding a state threshold ([0040][0041[0073] [0099][0100] [0116] mention that the current, temperature and power are controlled below the predefined upper limit).
For claim 17, Naveh teaches the method further comprising providing the accepted response signal of at least two response signal types to the corresponding response circuits in parallel ([0057] [0068][0076] [0085] mention calculating average power sample averaged over a plurality of samples for individual domain; thus domain level activity is aggregated from logic blocks’ aggregated activity indications to generate the state indicators of the domains, clusters or circuits).
For claim 18, Naveh teaches the method further comprising generating, by a programmable state tracker circuit (416 and 414 are programmable – [0069] firmware time and hardware time can be dynamically adjusted; [0088]-[0090] limit is programmable) corresponding to each state of the plurality of states in the plurality of logic circuits: the state indicator of the corresponding state ([0057][0060] [0068][0076] [0085] mention that 408, 414, 406 perform the averaging and [0057] [0060][0063] mentions that 416 and 414 perform the processing with average power sample; thus, 414 and 416 generates state indicators) and the suggested response signals having any one or more response signal type of the response signal types in response to the state indicator exceeding a threshold ([0060] – 414/416 generates the throttle signals; current control signal is mentioned in [0065] to control current; [0039][0040] – temperature control and enable power control operations according to power budgets; thus power budget generation (P-state) is a suggested response signal; [0063] mentions global power control operation includes what throttling operations to take on individual domains; therefore, suggested response signals are generated by 414 and 416; thresholds are mentioned in [0040][0041][0057] and various other places; thus the response signals are generated when threshold is exceeded).
For claim 19, Naveh et al teaches wherein the state indicators indicate two or more of a rate of change of current (di/dt), average power consumption of the plurality of logic circuits in a first time period, current provided to the plurality of logic circuits in a second time period, total power consumption of the plurality of logic circuits in a third time period, rate of temperature change, and temperature (temperature is mentioned in [0039] [0073]; [0081]- rate of temperature (i.e., temperature difference over a period represents the rate); [0097][0100] – current and power as these samples are averaged in [0068][0085] – the power and current values are average value over a period).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Naveh et al (US Patent Application Publication 2022/0413582).
For claims 8 and 20, Naveh teaches wherein the power management circuit is further configured to: compare a first state indicator of the state indicators to at least one threshold; and adjust a magnitude of at least one of the suggested response signals based on one or more of the state thresholds being compared with the first state indicator ([0069] mentions the dynamic adjustment of the loop control time of the hardware or firmware control loop when temperature has risen close to the maximum temperature). However, Naveh’s para [0069] embodiment does not mention exceeding any threshold. The embodiment in [0069] only mentions being close to the threshold. The further embodiment in Naveh teaches multiple thresholds where Tmax is the maximum threshold ([0077]). The first threshold is Tset and second threshold is Tth ([0077]). Thus, being close to Tmax can be determined by determining whether second threshold has been exceeded. It would have been obvious for one ordinary skill in the art before the effective filing date of the invention to compare with second threshold Tth in Naveh to determine whether being close to maximum temperature using the second embodiment described in [0077], since that way the crossing of maximum temperature can be prevented. That way, system can operate more safely.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Naveh et al (US Patent Application Publication 2022/0413582) in view of Karandikar et al (US Patent Application Publication 20230360166).
For claim 9, Naven teaches wherein the power management circuit further comprises
It would have been obvious for one ordinary skill in the art before the effective filing date of the invention to provide a voting circuit in the system of Naveh to determine the accepted response signal among the suggested signals, so that the system can determine the accepted response signal based on the majority voting. This provides better performance in the system for power control.
Conclusion
PTO-892 cites additional references that are not relied upon for rejection, but provides teachings related to the background of the invention.
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/FAHMIDA RAHMAN/Primary Examiner, Art Unit 2175
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