DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant' s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. JP2024-001843, filed on 01/10/2024.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/17/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Allowable Subject Matter
Claim 2-5, 7-11, 13-16, 18-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
REASONS FOR ALLOWANCE
For claim 2, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 2 depends.
For claim 3, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 3 depends. Additionally, claim 3 is allowable based on dependency from claim 2.
For claim 4, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 4 depends. Additionally, claim 4 is allowable based on dependency from claim 2.
For claim 5, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 5 depends. Additionally, claim 5 is allowable based on dependency from claim 4.
For claim 7, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 7 depends.
For claim 8, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 8 depends.
For claim 9, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 9 depends. Additionally, claim 9 is allowable based on dependency from claim 8.
For claim 10, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 10 depends.
For claim 11, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 11 depends.
For claim 13, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 13 depends.
For claim 14, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 4 depends. Additionally, claim 14 is allowable based on dependency from claim 13.
For claim 15, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 15 depends. Additionally, claim 15 is allowable based on dependency from claim 13.
For claim 16, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 16 depends. Additionally, claim 16 is allowable based on dependency from claim 15.
For claim 18, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 18 depends.
For claim 19, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 19 depends.
For claim 20, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 20 depends. Additionally, claim 20 is allowable based on dependency from claim 19.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 6, 12, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hashimoto (US 20160291872), in view of Kanno (US 20210064290).
Regarding Claim 1, Hashimoto teaches
A memory system that is connectable to a host, comprising: a nonvolatile memory that includes a plurality of blocks; and a controller that is electrically connected to the nonvolatile memory, and is configured to: manage a plurality of streams; (Hashimoto [0023] a storage device includes a non-volatile semiconductor memory device including a plurality of physical blocks, and a controller configured to associate one of the physical blocks with a stream ID)
allocate a first erased block for which a data erase operation has been completed among the plurality of blocks, as a general-purpose block into which data not associated with any of the plurality of streams and data associated with any of the plurality of streams (Hashimoto [0043] During a write operation… the flash memory 16 employs the 2 bit/cell write method, and the controller 14 controls the physical sector 35, recognizing that two pages, are allocated to the physical sector 35, as physical pages. A physical address comprises physical page addresses and a physical block address. [0048] When no data are stored in a block, then the controller 14 maps the block as a free block 43 and maps the free block 43 in the free block pool 430. Also, when all data in a block are invalid data, the controller 14 maps the block as a free block 43 and maps the free block 43 in the free block pool 430. That is, free blocks 43 in the free block pool 430 are physical blocks that do not store data and physical blocks that store only invalid data. When the block has a space in which write data are supposed to be written, then the controller 14 maps the block as an input block 44(45) and maps the input block 44(45) in the non-stream block pool 440 or the stream block pool 450.) (i.e., free blook 43 is general-purpose block that can be put in non-stream block pool as input block for writing data that is not associated with any stream and be put in stream block pool as input block for writing data that is associated with stream)
and in a case where use of a first stream among the plurality of streams is started, if two or more erased blocks for which the data erase operation has been completed are included in the plurality of blocks, allocate a second erased block as a write destination block corresponding to the first stream; (Hashimoto [0056] the data writing operation of the write data WD from the write buffer 20 to the physical block of the flash memory 16 is carried out according to a stream ID. …the write data WD are written into a physical block of the flash memory 16 that is mapped as an input block 45 associated with the stream ID in the write command CM2)
and if two or more erased blocks for which the data erase operation has been completed are not included in the plurality of blocks, set the first erased block as the write destination block corresponding to the first stream. (Hashimoto [0057] There are some circumstances where the physical blocks of the flash memory 16 are remapped as a different block. FIG. 12 schematically illustrates remapping of physical blocks. As shown by arrows 1210, when there is no available input block 45 associated with a stream ID in the flash memory 16, the controller 14 remaps (allocates) a free block 43 in the free block pool 430 as a new input block 45 associated with the stream ID.)
Hashimoto does not teach data associated with any of the plurality of streams are writable;
However, Kanno teaches data associated with any of the plurality of streams are writable; (Kanno [0107] these write data become writable to the write destination block BLK100 corresponding to the stream #n.)
Hashimoto and Kanno are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Hashimoto and Kanno to modify the Hashimoto‘s storage system of writing data on the basis of stream with Kanno’s teaching of write data become writable to the write destination block. The motivation for doing so would be (Kanno [0107]) write data become writable to the write destination block corresponding to the stream.
Regarding Claim 6, Hashimoto and Kanno teach
The memory system of claim 1, wherein the controller is further configured to change the second erased block allocated as the write destination block corresponding to the first stream to the general-purpose block in response to an end of the use of the first stream. (Hashimoto [0058] When a stream is no longer used, the stream can be closed. [0057] the controller 14 remaps the active blocks 46 from which valid data has been transferred, as free blocks 43)
Regarding Claim 12, Hashimoto teaches
A method of allocating a plurality of blocks of a nonvolatile memory according to a write request received from a host, the write request specifying one or none of a plurality of streams, said method comprising: (Hashimoto [0023] a storage device includes a non-volatile semiconductor memory device including a plurality of physical blocks, and a controller configured to associate one of the physical blocks with a stream ID)
allocating a first erased block for which a data erase operation has been completed among the plurality of blocks, as a general-purpose block into which data not associated with any of the plurality of streams and data associated with any of the plurality of streams (Hashimoto [0043] During a write operation… the flash memory 16 employs the 2 bit/cell write method, and the controller 14 controls the physical sector 35, recognizing that two pages, are allocated to the physical sector 35, as physical pages. A physical address comprises physical page addresses and a physical block address. [0048] When no data are stored in a block, then the controller 14 maps the block as a free block 43 and maps the free block 43 in the free block pool 430. Also, when all data in a block are invalid data, the controller 14 maps the block as a free block 43 and maps the free block 43 in the free block pool 430. That is, free blocks 43 in the free block pool 430 are physical blocks that do not store data and physical blocks that store only invalid data. When the block has a space in which write data are supposed to be written, then the controller 14 maps the block as an input block 44(45) and maps the input block 44(45) in the non-stream block pool 440 or the stream block pool 450.) (i.e., free blook 43 is general-purpose block that can be put in non-stream block pool as input block for writing data that is not associated with any stream and be put in stream block pool as input block for writing data that is associated with stream)
and in a case where use of a first stream among the plurality of streams is specified in the write request received from the host, if two or more erased blocks for which the data erase operation has been completed are included in the plurality of blocks, allocating a second erased block as a write destination block corresponding to the first stream; (Hashimoto [0056] the data writing operation of the write data WD from the write buffer 20 to the physical block of the flash memory 16 is carried out according to a stream ID. …the write data WD are written into a physical block of the flash memory 16 that is mapped as an input block 45 associated with the stream ID in the write command CM2)
and if two or more erased blocks for which the data erase operation has been completed are not included in the plurality of blocks, setting the first erased block as the write destination block corresponding to the first stream. (Hashimoto [0057] There are some circumstances where the physical blocks of the flash memory 16 are remapped as a different block. FIG. 12 schematically illustrates remapping of physical blocks. As shown by arrows 1210, when there is no available input block 45 associated with a stream ID in the flash memory 16, the controller 14 remaps (allocates) a free block 43 in the free block pool 430 as a new input block 45 associated with the stream ID.)
Hashimoto does not teach data associated with any of the plurality of streams are writable;
However, Kanno teaches data associated with any of the plurality of streams are writable; (Kanno [0107] these write data become writable to the write destination block BLK100 corresponding to the stream #n.)
Hashimoto and Kanno are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Hashimoto and Kanno to modify the Hashimoto‘s storage system of writing data on the basis of stream with Kanno’s teaching of write data become writable to the write destination block. The motivation for doing so would be (Kanno [0107]) write data become writable to the write destination block corresponding to the stream.
Regarding Claim 17, Hashimoto and Kanno teach
The method of claim 12, further comprising: changing the second erased block allocated as the write destination block corresponding to the first stream to the general-purpose block in response to an end of the use of the first stream. (Hashimoto [0058] When a stream is no longer used, the stream can be closed. [0057] the controller 14 remaps the active blocks 46 from which valid data has been transferred, as free blocks 43)
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Hashimoto (US-20160313943) teaches stockage device that secures a block for a stream
Gunda (US-20230367498) teaches stream oriented writing for improving sequential write and read performance.
Conclusion
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/WEI MA/Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135