DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Specie III (Figure 6) in the reply filed on 04/14/2016 is acknowledged.
Applicant indicates that claims 1-20 are readable on the elected Specie III (Figure 6). However, upon further consideration, only claims 1-4, 7-9, and 11-20 are readable on the elected Specie III (Figure 6). Note that claims 5-6 and 10 are not readable on the elected Specie III (Figure 6) because Figure 6 does not comprise “an input transistor coupled to the first tail node; and a tail transistor coupled to the second tail node and having a gate terminal coupled to a gate terminal of the input transistor” (as recited in claims 5-6), and “a first input transistor coupled to the first pair of mixer transistors at a first tail node; and a second input transistor coupled to the second pair of mixer transistors at a second tail node” (as recited in claim 10).
Claims 5-6 and 10 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Specie, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 04/14/26.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-4, 7-9 and 11-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,206,362 (the ‘362 patent, hereafter). Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-20 of the ‘362 patent encompassed all the limitations of claims 1-4, 7-9 and 11-20 and they are drawn to substantially the same embodiment of the invention. Note that, claims 1-20 of the ‘362 patent teaches a mixer comprising a first mixer transistor, a second transistor mixer transistor, a first bias transistor, a second bias transistor, a third mixer transistor, a fourth mixer transistor; and also teaches a transformer with a secondary coil and a primary coil etc. as in claims 1-4, 7-9 and 11-20 of the instant application.
Specification
The disclosure is objected to because of the following informalities: on page 1, lines 1-2 (the paragraph before paragraph [0001]), the issued patent information of Application 18/336,761 should be provided . Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
For claim 14, the recitation “a coil having a first terminal coupled to the first pair of mixer transistors and a second terminal coupled to the bias circuit” appears to be misdescriptive because it is inconsistent with the specification as the specification (paragraph [0055], lines 1-2) discloses that “coil 104s may have a first terminal coupled to first tail node Va, a second terminal coupled to second tail node Vb” (i.e., not “a second terminal coupled to the bias circuit” as recited in the claim). Clarification and/or appropriated correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 8-9, 11, and 14-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (US 2018/0159474).
For claim 1, Figure 5 of Yu et al. teaches a mixer circuitry comprising: a first mixer transistor (the very first most left-side transistor inside 315-b wherein the gate of the transistor receiving signal LO+ via 310-b) configured to receive a first oscillating signal (LO+) and coupled to a first tail node (the junction source node of the 2 left-side transistors in 315-b); a second mixer transistor (the second most left transistor inside 315-b wherein the gate of the transistor receiving signal LO- via a capacitor) configured to receive a second oscillating signal (LO-) different than the first oscillating signal (LO+) and coupled to the first tail node (the junction source node of the 2 left-side transistors in 315-b); and a first bias transistor (430-a) configured to receive the first oscillating signal (LO+) and coupled to a second tail node (either node 445-a or ground node) different than the first tail node.
For claim 2, Figure 5 of Yu et al. teaches a third mixer transistor (the right most transistor inside 315-b wherein the gate of the transistor receives LO+ via 310-b) configured to receive the first oscillating signal (LO+) and coupled to a third tail node (the junction source node of the 2 right-side transistors in 315-b) different than the first and second tail nodes; and a fourth mixer transistor transistor (the second most right transistor inside 315-b wherein the gate of the transistor receiving signal LO- via a capacitor) configured to receive the second oscillating signal (LO-) and coupled to the third tail node.
For claim 3, Figure 5 of Yu et al. teaches a second bias transistor (430-b) configured to receive the second oscillating signal (LO-) and coupled to the second tail node.
For claim 4, Figure 5 of Yu et al. teaches wherein the second bias transistor (430-b) is coupled in parallel with the first bias transistor (430-a).
For claim 8, Figure 5 of Yu et al. teaches a mixer circuitry comprising: a first pair of mixer transistors (the 2 left-side transistors inside 315-b) configured to receive an oscillating signal (LO+, LO-); and a bias circuit (305-b) configured to receive the oscillating signal (LO+, LO-) and to control an amount of current (by Vbias) flowing through the first pair of mixer transistors.
For claim 9, Figure 5 of Yu et al. teaches a second pair of mixer transistors (the 2 right-side transistors inside 315-b) configured to receive the oscillating signal (LO+, LO-), wherein the bias circuit (305-b) is further configured to control an amount of current (by Vbias) flowing through the second pair of mixer transistors.
For claim 11, Figure 5 of Yu et al. teaches wherein the bias circuit (305-b) further comprises: a pair of bias transistors (430-a, 430-b) coupled together in parallel and configured to receive the oscillating signal (LO+, LO-).
Insofar as understood in claim 14, Figure 5 of Yu et al. teaches a coil (secondary coil (i.e., second coil from the bottom) of the bottom transformer inside 315-b) having a first terminal coupled to the first pair of mixer transistors (the source node of the 2 left-side transistors inside 315-b) and a second terminal coupled a second terminal coupled to a second pair of mixer transistors (the source node of the 2 right-side transistors inside 315-b). Also, Figure 5 of Yu et al. also shows the coil (the secondary coil (i.e., second coil from the bottom)) is also coupled to the bias circuit (305-b) as the center-tap terminal of the coil coupled to common ground with the bias circuit (305-b).
For claim 15, Figure 5 of Yu et al. teaches a mixer circuitry comprising: a first pair of mixer transistors (the 2 left-side transistors inside 315-b) configured to receive an oscillating signal (LO+, LO-) and coupled to a first tail node (the source node of the 2 left-side transistors inside 315-b); a transformer (bottom transformer inside 315-b) coupled to the first tail node (the source node of the 2 left-side transistors inside 315-b); and a bias circuit (305-b) configured to receive the oscillating signal (LO+, LO-) and being coupled to the transformer (as the center-tap terminal of the secondary coil of the transformer coupled to common ground with the bias circuit (305-b).
For claim 16, Figure 5 of Yu et al. teaches a second pair of mixer transistors (the 2 right-side transistors inside 315-b) configured to receive the oscillating signal (LO+, LO-) and coupled to a second tail node (the source node of the 2 right-side transistors inside 315-b), wherein the second tail node (the source node of the 2 left-side transistors inside 315-b) is coupled to the transformer (bottom transformer inside 315-b).
For claim 17, Figure 5 of Yu et al. teaches wherein the transformer (bottom transformer inside 315-b) comprises: a primary coil (first coil from the bottom inside 315-b); and a secondary coil (second coil from the bottom inside 315-b) having a first terminal (left side of the secondary coil) coupled to the first tail node (the source node of the 2 left-side transistors inside 315-b), a second terminal (right side of the secondary coil) coupled to the second tail node (the source node of the 2 right-side transistors inside 315-b), and a center tap terminal (center tab of the secondary coil) coupled to the bias circuit (305-b, i.e., coupled to common ground).
For claim 18, Figure 5 of Yu et al. teaches the bias circuit (305-b) comprises: a first bias transistor (430-a); and a second bias transistor (430-b) coupled in parallel with the first bias transistor (430-a).
For claim 19, Figure 5 of Yu et al. teaches wherein the bias circuit (305-b) further comprises: operational amplifier (425-a) coupled between the transformer (bottom transformer inside 315-b) and a node (either node 445-a or ground node) disposed between the first and second bias transistors (430-a and 430-b).
For claim 20, Figure 5 of Yu et al. teaches a low pass filter (310-b and/or the combination of capacitor connected between output terminal and + terminal of 425-a and 430-a) coupled between the bias circuit (305-b) and the transformer (bottom transformer inside 315-b).
Allowable Subject Matter
Claims 7 and 12-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if a proper Terminal Disclaimer is filed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wang (US Patent 8,412,143) teaches in Figures 4 and 5 a double balanced mixer including a combination of transistors.
Any inquiry concerning this communication or earlier communications from the examiner should be directly to Examiner Long Nguyen whose telephone number is (571) 272-1753. The Examiner can normally be reached on Monday to Friday from 8:30am to 5:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch, can be reached at (571) 270-7101. The fax number for this group is (571) 273-8300.
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/Long Nguyen/
Primary Examiner
Art Unit 2836
Prosecution Insights