Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities:
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Appropriate correction is required.
Claim Objections
Claim 1 is objected to because of the following informalities:
The second “comprising:” after the limitation “a resistive memory”, it is not clear the limitations recited thereafter belong to the resistive memory or just “a storage region”. The rest appears to belong to “processing circuit” in the first “comprising” as reflected in Fig. 1 of the drawing.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7-16, 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by WO2017019097A1, “Buchanan”.
Regarding claim 1, Buchanan discloses:
A processing circuit (Fig. 1), comprising: an image-providing device configured to provide a target image (110i-110n “recording pixel bit cell”; also Fig. 2 for additional context); an adjustment device adjusting a scale of a template image to generate a sample image according to setting information (Fig. 1, 120; pars. 0028, 0030 e.g., 50% of recording pixel bit-cells); a resistive memory (Fig. 1, 114) comprising: a storage region storing the target image (inherent); a computation circuit computing the sample image and the target image to generate a plurality of computation results; and a control circuit finding a matching position that matches the sample image in the target image according to the computation results (pars. 0032-0033 “comparison operation” on captured images is read against claimed computation results and finding a match of pixel positions; this is executed by the controller 120 in Fig. 1).
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Regarding claim 2, The processing circuit as claimed in claim 1, wherein the image-providing device is an image sensor (Rejected as in claim 1; Fig. 1 “image sensor array system”).
Regarding claim 3, The processing circuit as claimed in claim 1, wherein the image-providing device is a memory (Rejected as in claim 1; Fig. 1, 110i-110n “recording pixel bit cell” comprises resistive memory 114).
Regarding claim 4, The processing circuit as claimed in claim 1, wherein the storage region comprises a plurality of resistor layers, the target image comprises a plurality of pixels, and a resistance of each resistor layer is related to a gray-level of each pixel (Rejected as in claim 1; pars. 0017 “passive two-terminal circuit element” reads on resistor layers; target image comprising plurality of pixels is depicted in Fig. 2; resistance of each resistor layer is related to a gray-level of each pixel – this is inherent in the functional activities of the resistive memory 114 of Fig. 1).
Regarding claim 5, The processing circuit as claimed in claim 1, wherein the computation circuit splits the storage region into a plurality of image regions according to the setting information and computes the sample image with images stored in the image regions to generate the computation results (Rejected as in claim 1; Fig. 2 depicts pixel array wherein “pixel regions” may be utilized for read/write as well as “image comparison operation” for successive captured images as noted in pars. 0032-0033 in claim 1 above).
Regarding claim 7, The processing circuit as claimed in claim 5, wherein the number of pixels in the image stored in each image region is the same as the number of pixels in the sample image (Rejected as in claim 1; par. 0033 best explains this claim e.g., the two successive images are of same size and pixels of same corresponding locations for comparison).
Regarding claim 8, The processing circuit as claimed in claim 5, wherein the storage region comprises a plurality of transmission lines and a plurality of resistor layers, and each resistor layer is coupled between two of the transmission lines (this is best depicted in Fig. 4).
Regarding claim 9, The processing circuit as claimed in claim 8, wherein the resistive memory comprises: a writing circuit setting resistances of the resistor layers according to gray-levels of pixels of the target image (Rejected as in claim 8; also pars. 0035-36 best explain write signal line 410 is set “commensurate” to light intensity (gray level intensity).
Regarding claim 10, The processing circuit as claimed in claim 9, wherein the computation circuit comprises: a sample-hold circuit coupled to the transmission lines and generating a plurality of sampling signals; an analog-to-digital convertor circuit converting the sampling signals to generate a plurality of digital signals; a processing circuit accumulating the digital signals to generate the computation results (Rejected as in claims 1, 5, 8 and 9; also par. 0038 best explains “sample and hold” pixel values through write signal line 410; pars. 0009-0011 discuss CCD and CMOS image sensors being utilized in the art, thus, A/D conversion could be within the sensor e.g., CMOS or off-load outside of the sensor e.g., CCD but A/D convertor circuit are present; see rejection in claim 1 above for “computation results”).
Regarding claim 11, The processing circuit as claimed in claim 10, wherein the number of digital signals is the same as the number of pixels in the sample image (Rejected as in claim 10; this is inherent since each pixel corresponds to a digital signal per conversion).
Regarding claim 12, The processing circuit as claimed in claim 10, further comprising: a digital-to-analog convertor circuit converting all gray-levels of the sample image to generate a plurality of analog signals and providing the analog signals to the storage region (Rejected as in claim 10; this claim is simply post processing to analog signals for storage - inherent).
Regarding claim 13, The processing circuit as claimed in claim 11, wherein the number of pixels in the target image is larger than the number of pixels in the sample image (Rejected as in claims 1, 10-11; Figs. 2-3 and pars. 0027-33 best explain this).
Regarding claim 14, A template matching method applied a resistive memory, comprising: adjusting scale of a template image to generate a sample image; storing a target image in a storage region of the resistive memory; splitting the target image to generate a plurality of sub-images; computing the sample image and the sub-images to generate a plurality of computation results; and finding a matching position that matches the sample image in the target image according to the computation results (Rejected as in claim 1 since this claim is a corresponding method claim for carrying out the steps of claim 1 when implemented).
Regarding claim 15, The template matching method as claimed in claim 14, further comprising: using an output of an image sensor as the target image (Rejected as in claim 1).
Regarding claim 16, The template matching method as claimed in claim 14, further comprising: reading a memory to obtain the target image (Rejected as in claim 1; par. 0022 best explains this).
Regarding claim 18, The template matching method as claimed in claim 14, wherein the number of pixels in each sub-image is the same as the number of pixels in the sample image (Rejected as in claim 7).
Regarding claim 19, The template matching method as claimed in claim 14, wherein the number of pixels in the target image is larger than the number of pixels in the sample image (Rejected as in claim 13).
Regarding claim 20, The template matching method as claimed in claim 14, wherein the step of storing the target image in the storage region of the resistive memory comprises: setting resistances of all resistor layers of the storage region according to gray-levels of all pixels of the target image (Rejected as in claim 9).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 6, 17 are rejected under 35 U.S.C. 103 as being unpatentable over WO2017019097A1, “Buchanan” in view of US20220222893A1, “Li”.
Regarding claim 6, the rejection of claim 5 is incorporated herein. Buchanan does not expressly disclose the further limitation of: The processing circuit as claimed in claim 5, wherein each image region overlaps adjacent image regions. Li makes well known target face image matching wherein “overlapping region” between regional face images is reduced (pars. 0010, 0067, 0120). Li further suggests that computer-readable storage medium maybe “a resistance random access memory (ReRAM) (par. 0314).
At the time of effective filing of the present invention, it would have been obvious to one of ordinary skill in the art to incorporate the teaching of Li into Buchanan to derive at claim 6. Doing so would benefit reducing overlapping image regions during target matching (par. 0010).
Regarding claim 17, The template matching method as claimed in claim 14, wherein each sub-image overlaps adjacent sub-images (Rejected as in claim 6; image region implies “sub-image”).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US-20210057644-A1
US-20220075815-A1
US-20220353411-A1
US-20240403619-A1
US-20090265287-A1
US-20150339530-A1
US-20240171845-A1
US-20220256076-A1
Digital image processing realized by memristor-based technologies, Wang et al, NPL
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VU LE whose telephone number is (571)272-7332. The examiner can normally be reached M-F 8:00 - 17:00.
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Vu Le can be reached at 2-7332. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VU LE/Supervisory Patent Examiner, Art Unit 2668
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