DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 8, and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (hereinafter “Liu”), US Pub. No. 2022/0238065.
Regarding claim 1, Liu teaches a pixel circuit (fig. 1, pixel driving circuit 10), comprising: a drive module (fig. 2, driving module 11), a first light emission control module (fig. 2, light emission control module 172), and a light-emitting module sequentially connected in series (fig. 2, light emitting element L1), wherein the drive module has a gate node (fig. 3, transistor T3), and the first light emission control module has a control node (fig. 3, transistor T6); a first data write module (fig. 2, data write-in module 13), which is coupled between a first global signal line (fig. 2, DI) and the drive module (fig. 2, driving module 11) and configured to, in response to an effective potential of a first control signal, write a global data voltage on the first global signal line to the gate node (fig. 2, gate control end GA); and a second data write module (fig. 3, data write-in module 18), which is coupled between a data line (fig. 2, DT) and the control node (fig. 3, control node of transistor T6) and configured to, in response to an effective potential of a second control signal, write a data control voltage on the data line to the control node to enable the control node to have a control potential (fig. 2, data end DT, gate control signal GB).
Regarding claim 2, Liu teaches wherein one display cycle of the pixel circuit comprises at least one write frame, and the second data write module is configured to, in response to the effective potential of the second control signal, write the data control voltage on the data line to the control node in the at least one write frame to enable the control node to have the control potential (figs. 4, 5, and accompanying text).
Regarding claim 3, Liu teaches wherein the first light emission control module is controlled by the data control voltage to be turned on or turned off ([0096]).
Regarding claim 4, Liu teaches wherein the first light emission control module comprises a first light emission control transistor (fig. 3, transistor T6), and a gate of the first light emission control transistor is electrically connected to the control node (fig. 3, E1); the data control voltage is configured to enable the first light emission control transistor to operate in a linear region when the first light emission control transistor is controlled to be turned on by the data control voltage (fig. 3, DI, DT, VDD).
Regarding claim 8, Liu teaches wherein when the display cycle comprises a plurality of write frames, the first data write module is configured to be coupled between the data line and the drive module and, in response to the effective potential of the first control signal, write a grayscale data voltage on the data line to the gate node (fig. 3, data write-in 13, grayscale adjustment module 12); and the second data write module is configured to be coupled between a second global signal line and the control node and, in response to the effective potential of the second control signal, write a global control voltage on the second global signal line to the control node to enable the control node to have the control potential (fig. 3, data write-in 18, grayscale adjustment module 12).
Regarding claim 10, Liu teaches wherein when the display cycle comprises a plurality of write frames, the first data write module is configured to be coupled between the first global signal line and the drive module and, in response to the effective potential of the first control signal, write the global data voltage to the gate node (fig. 3, data write-in 13); the second data write module is configured to be coupled between the data line and the control node and, in response to the effective potential of the second control signal, write the data control voltage to the control node to enable the control node to have the control potential (fig. 3, data write-in 18).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, 7, 9, 11-13, and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Liu (see above), in view of Gao, US Pub. No. 2025/0124861.
Regarding claim 6, Liu fails to explicitly teach wherein when the display cycle comprises one write frame and a plurality of retention frames, the effective potential of the first control signal is configured to be generated in the write frame and at least one of the plurality of retention frames, or, the first control signal is configured to be maintained at the effective potential in at least one of the plurality of retention frames; and the effective potential of the second control signal is configured to be generated in the write frame.
However, in the same field of endeavor, Gao teaches a pixel driving circuit including a data write frame and a retention frame that are dynamically adjusted by a control signal to maintain a potential (see [0149]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Liu to include the feature of Gao. As such, a person having ordinary skill in the art would appreciate the motivation for doing so would have been to compensate for electric leakage (Gao, [0149]).
Regarding claim 7, Gao teaches wherein the drive module has a source node, and when the effective potential of the first control signal is configured to be generated in the write frame and the at least one of the plurality of retention frames, the first data write module is coupled to the source node; or when the first control signal is configured to be maintained at the effective potential in the at least one of the plurality of retention frames, the first data write module is coupled to the gate node (fig. 21, [0149]).
Regarding claim 9, the combination of Liu and Gao teaches wherein the display cycle further comprises at least one retention frame, wherein: the effective potential of the first control signal is configured to be generated in each of the plurality of write frames and the at least one retention frame, and the effective potential of the second control signal are configured to be generated in each of the plurality of write frames (Gao, [0149]); the grayscale data voltage corresponds to a display grayscale, and voltage values of grayscale data voltages corresponding to different display grayscales of a same display brightness level are different (Liu, grayscale adjustment module 12); or when the display cycle comprises one write frame and a plurality of retention frames, the global data voltage corresponds to a display brightness level, voltage values of a global data voltage corresponding to a same display brightness level are the same, and voltage values of global data voltages corresponding to different display brightness levels are different; and the data control voltage has a first potential and a second potential, and the global control voltage has a third potential, wherein the first potential and the third potential are configured to enable the first light emission control module to be turned on, and the second potential is configured to enable the first light emission control module to be turned off (Liu, figs. 4, 5 and accompanying text; grayscale adjustment module 12; Gao, [0149]; fig. 21).
Regarding claim 11, the combination of Liu and Gao teaches wherein at least one of the following configurations is satisfied: the effective potential of the first control signal and the effective potential of the second control signal are configured to be generated in each of the plurality of write frames (fig. 3, GA, GB); or when one display cycle comprises a plurality of write frames or comprises one write frame and a plurality of retention frames, the global data voltage corresponds to a display brightness level, voltage values of the global data voltage corresponding to a same display brightness level are the same, and voltage values of global data voltages corresponding to different display brightness levels are different (Liu, grayscale adjustment module 12, Gao, [0049], fig. 21); and the data control voltage has a first potential and a second potential, wherein the first potential is configured to enable the first light emission control module to be turned on, and the second potential is configured to enable the first light emission control module to be turned off (fig. 3, VDD, VSS).
Regarding clam 12, the combination of Liu and Gao teaches a compensation module (Liu, compensation module 14; fig. 2) and a second light emission control module, wherein when the display cycle comprises one write frame and a plurality of retention frames (Liu, light-emission control module 171, fig. 2; Gao, [0149], fig. 21); and in the write frame, the compensation module is configured to write a threshold voltage of a drive transistor in the drive module to the gate node in a threshold compensation stage ([0092-0093]); the second data write module is configured to write the data control voltage to the control node in a control potential write stage to enable the control node to have the control potential; the second light emission control module is configured to be turned off in the threshold compensation stage and the control potential write stage and to be turned on in a light emission stage (fig. 2, data write-in 18, VDD, VSS).
Regarding claim 13, Liu teaches wherein at least one of the following configurations is satisfied: the threshold compensation stage does not overlap the control potential write stage; the threshold compensation stage precedes the control potential write stage; the first data write module is configured to write the global data voltage to the gate node in a data write stage; the first data write module is configured to write the global data voltage to the gate node in a data write stage, and the threshold compensation stage further comprises the data write stage; and an interval exists between the control potential write stage and the light emission stage (figs. 4, 5 and accompanying text).
Regarding claim 15, Liu teaches wherein the drive module further has a source node and a drain node, the drive module, the first light emission control module, and the light-emitting module are coupled between a first power voltage line and a second power voltage line (fig. 3, driving module 11), the second light emission control module comprises a first light emission control unit and a second light emission control unit, the first light emission control unit is coupled between the first power voltage line and the source node, the second light emission control unit is coupled between the drain node and the light-emitting module (fig. 3, light emitting control 171 and 172), and the light-emitting module is coupled between the second light emission control unit and the second power voltage line, the light-emitting module has an anode node (fig. 3, O1), the pixel circuit further comprises a first reset module, and the first reset module is coupled between a first reset signal line and the anode node, the first reset module is configured to write a first reset voltage on the first reset signal line to the anode node in a first reset stage (fig. 3, R1); wherein the first light emission control module is coupled between the first power voltage line and the first light emission control unit; or the first light emission control module is coupled between the first light emission control unit and the source node; or the first light emission control module is coupled between the drain node and the second light emission control unit; or the first light emission control module is coupled between the second light emission control unit and the light-emitting module (fig. 3, elements 171, 172, and O1).
Regarding claim 16, Gao teaches wherein at least one of the following configurations is satisfied: the threshold compensation stage further comprises the first reset stage (fig. 14, RST1); a working stage of the pixel circuit further comprises a power-on reset stage, and the power-on reset stage precedes a write frame of a first display cycle, wherein in the power-on reset stage, the compensation module and the second light emission control module are configured to be turned on, the first data write module is configured to write the global data voltage and the threshold voltage to the gate node through the drive module and the compensation module, and the second data write module is configured to turn on the first light emission control module ([0119,0120]); the pixel circuit further comprises a second reset module, the second reset module is coupled between a second reset signal line and the gate node, and when the display cycle comprises one write frame and a plurality of retention frames, in the write frame, the second reset module is configured to write a second reset voltage on the second reset signal line to the gate node in the second reset stage; the second reset stage does not overlap the threshold compensation stage, and the second reset stage precedes the threshold compensation stage; the first reset module is configured to, in response to an effective potential of a fourth control signal, write the first reset voltage on the first reset signal line to the anode node in the first reset stage; when the display cycle comprises one write frame and a plurality of retention frames, the second reset module is configured to, in response to an effective potential of a fifth control signal, write a second reset voltage on the second reset signal line to the gate node in the second reset stage; and the second reset module comprises a third dual-gate transistor.
Regarding claim 17, the combination of Liu and Gao teaches a display panel (Liu, fig. 6, display panel 100), wherein the plurality of pixel circuits are arranged in a plurality of columns ([0141]); and a plurality of first global signal lines and a plurality of data lines, wherein when one display cycle comprises one write frame and a plurality of retention frames (Gao, [0149]), first data write modules in pixel circuits of a same color are coupled to a same first global signal line, second data write modules in pixel circuits in a same column are coupled to a same data line, different first global signal lines are configured with global data voltages having different voltage values, different data lines are configured with corresponding data control voltages, and a data control voltage corresponds to a display image of the display panel (Liu, [0141]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Lui in view of Gao as applied to claim 12 above, and further in view of Guo et al. (hereinafter “Guo”), US Patent No. 12,165,589.
Regarding claim 14, Lui and Gao fail to explicitly teach the compensation module comprises a second dual-gate transistor; the compensation module is configured to, in response to an effective potential of a third control signal, write a threshold voltage of a drive transistor in the drive module to the gate node in the threshold compensation stage.
However, in the same field of endeavor, Guo teaches a pixel driving circuit including a compensation module that includes a dual gate transistor (see fig. 3, transistor 130; fig. 4, transistor 140).
Therefore, it would have been obvious to a person having ordinary skill in the art before the filing date of the effective claimed invention to modify Liu and Gao to include the feature of Guo. As such, a person having ordinary skill in the art would appreciate the motivation for doing so would have been to prevent substandard flicker at low frequency (col. 1, lines 36-37).
Allowable Subject Matter
Claims 5 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: None of the prior art, either singularly or in combination, teaches or fairly suggests the specific combination comprising the specific elements taught in the dependent claims above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Zheng et al. (US Pub. No. 2024/0078948) teaches a pixel driving circuit including first and second light emission circuits, first and second data write-in circuits, compensation circuit and a driving transistor.
Zhai et al. (US Pub. No. 2023/0316987) teaches a pixel driving circuit including first and second data write-in modules, a compensation module, driving module and first and second light emission circuits.
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/KENNETH B LEE JR/Primary Examiner, Art Unit 2625