DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 – 20 are pending.
Specification
The disclosure is objected to because of the following informalities. Appropriate correction is required.
¶[52] should be amended to “In [[order]] other words, the write staging buffer 34 forwards pending write requests in a manner so as to minimize bank conflicts at the write queue 38”. This is a typo.
Claim Objections
Claims 2, 9 – 12, 15, 17 and 20 are objected to because of the following informalities. Appropriate correction is required.
Claim 2 should be amended to “transfer a first pending write request to the write queue in response to the first pending write request being addressed to a memory tile that is not one of the respective tiles already addressed by i) the active write requests in the write queue or ii) the active read requests in the read queue”. There is no antecedence basis for “memory tiles”. Rather it is respective tiles that are being addresses by active write requests in claim 1. In addition, this amendment is so that it is clear what (addressed memory tiles or active write requests) corresponds to active read requests (see spec ¶[53]).
Claim 9 should be amended to “transfer one or more pending write requests to the write queue in response to [[the]] memory [[tiles]] tiles, being addressed by the one or more pending write requests, being [[being]] marked as idle or not busy”. This so that it is clear what (memory tiles or pending write requests) are being marked as idle. In addition, there is no antecedence basis for “the memory tiles”.
Claim 10 should be amended to “transfer one or more pending write requests to the write queue in response to [[the]] memory [[tiles]] tiles, being addressed by the one or more pending write requests, being [[being]] marked as idle or not busy”. This is the same issue as claim 9.
Claim 11 should be amended to “keep one or more pending write requests in the write staging buffer in response to [[the]] memory [[tiles]] tiles, being addressed by the one or more pending write requests, being [[being]] marked as busy”. This is the same issue as claim 9 but for busy status.
Claim 12 should be amended to “keep one or more pending write requests in the write staging buffer in response to the memory [[tiles]] tiles, being addressed by the one or more pending write requests, being [[being]] marked as busy”. This is the same issue as claim 11.
Claim 15 should be amended to “a bank tracker configured to track status of the plurality of tiles having read requests or write requests being sent to the memory device, the bank tracker identifying a memory tile as busy in response to a read or write request being sent to the memory device and identifying a memory tile as idle or not busy in response to (i) no request being sent or (ii) previously sent request being completed, wherein the write staging buffer obtains the status of the plurality of tiles from the bank tracker”. There is no antecedence for memory tiles. Also, tiles here should be the same tiles in claim 1 (see spec Fig. 4(b) and corresponding paragraphs). There is no support for tracking status of tiles that are not part of memory that received read/write requests.
Claim 17 should be amended to “each incoming write request comprises write data for a page of memory data in the plurality of tiles, the page comprising a plurality of bytes of data”. Tiles here should be same as tiles in claim 1 (see spec Fig. 3 and corresponding paragraphs). There is no support for writing to tiles that are not part of memory device.
Claim 20 should be amended to “a controller device formed in a semiconductor die i) separate from a semiconductor die on which the memory device is formed and ii) interconnected to the memory device through interconnect structures”. This is so that it is clear what (semiconductor die or memory device) corresponds to interconnection to memory device.
Claim Interpretation
Regarding claims 1 – 20, “tile(s)” is interpreted as referring to bank(s) of memory (see spec ¶[37]).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1 – 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 13 and 15 – 16 of U.S. Patent No. 12,210,749 in view of Iyer (US 20150339227).
Instant Application
Patent 12,210,749
1. A control circuit configured to interact with a memory device to perform read and write operation at the memory device, the memory device comprising memory transistors organized in a plurality of tiles, [[each tile being operated independently of other tiles in the memory device]],
the control circuit comprising:
a read queue configured to store active read requests for reading data from the memory device, [[each active read request being addressed to a respective tile in the plurality of tiles]];
a write queue configured to store active write requests for writing data to the memory device, [[each active write request being addressed to a respective tile in the plurality of tiles]]; and
a write staging buffer configured to store pending write requests received by the control circuit and to transfer the pending write requests to the write queue to maximize a number of the active write requests in the write queue that are addressed to different tiles of the memory device.
1. A memory system, comprising:
a memory device comprising an array of storage transistors for storing data, the storage transistors being organized in a plurality of memory banks, each memory bank including a plurality of memory pages;
a control circuit configured to interact with the memory device to perform read and write operations,
the control circuit comprising a read queue configured to store active read requests for reading data from the memory device,
a write queue configured to store active write requests for writing data to the memory device, and
a write staging buffer configured to store pending write requests received by the control circuit and to transfer the pending write requests to the write queue to maximize a number of the active write requests that are addressed to different memory banks of the memory device.
2. The control circuit of claim 1, wherein the write staging buffer is configured to transfer a first pending write request to the write queue in response to the first pending write request being addressed to a memory tile that is not one of the memory tiles already addressed by the active write requests in the write queue or the active read requests in the read queue.
2. The memory system of claim 1, wherein the write staging buffer is configured to transfer a first pending write request to the write queue in response to a memory bank associated with the first pending write request being (i) not one of the memory banks associated with the active write requests in the write queue or (ii) not one of the memory banks associated with the active read requests in the read queue.
3. The control circuit of claim 1, wherein the write staging buffer is configured to transfer a second pending write request to the write queue in response to the second pending write request being addressed to a memory tile having a bank status identified as idle or not busy.
3. The memory system of claim 1, wherein the write staging buffer is configured to transfer a second pending write request to the write queue in response to a memory bank, associated with the second pending write request, having a bank status identified as idle or not busy.
4. The control circuit of claim 3, wherein the write staging buffer is configured to transfer a third pending write request to the write queue in response to the third pending write request having remained in the write staging buffer for longer than a maximum time threshold, the third pending write request being transferred to the write queue regardless of whether the third pending write request is addressed to a memory tile having a bank status identified as idle or busy.
4. The memory system of claim 3, wherein the write staging buffer is configured to transfer a third pending write request to the write queue in response to the third pending write request having remained in the write staging buffer for longer than a maximum time threshold, the third pending write request being transferred to the write queue regardless of whether a memory bank, associated with the third pending write request, has a bank status identified as idle or busy.
5. The control circuit of claim 3, wherein the write staging buffer is configured to transfer a fourth pending write request to the write queue in response to a storage area in the write staging buffer having a storage capacity at or exceeding an occupancy threshold, the fourth pending write request being transferred to the write queue regardless of whether the fourth pending write request is addressed to a memory tile having a bank status identified as idle or busy.
5. The memory system of claim 3, wherein the write staging buffer is configured to transfer a fourth pending write request to the write queue in response to a storage area in the write staging buffer having a storage capacity at or exceeding an occupancy threshold, the fourth pending write request being transferred to the write queue regardless of whether a memory bank, associated with the fourth pending write request, has a bank status identified as idle or busy.
6. The control circuit of claim 1, wherein the control circuit further comprises:
a read ingress buffer configured to receive incoming read requests received by the control circuit and to transfer the incoming read requests to the read queue; and
a write ingress buffer configured to receive incoming write requests received by the control circuit and to transfer the incoming write requests to the write staging buffer to store as the pending write requests.
6. The memory system of claim 1, wherein the control circuit further comprises:
a read ingress buffer configured to receive incoming read requests received by the control circuit and to transfer the incoming read requests to the read queue; and
a write ingress buffer configured to receive incoming write requests received by the control circuit and to transfer the incoming write requests to the write staging buffer to store as the pending write requests.
7. The control circuit of claim 6, wherein the write staging buffer is configured to mark a memory tile as busy for a first duration in response to the memory tile being addressed by an incoming read request that is transferred to the read queue from the read ingress buffer, and
the write staging buffer is further configured to mark the memory tile as idle or not busy at an expiration of the first duration.
7. The memory system of claim 6, wherein in response to (i) an incoming read request being transferred to the read queue from the read ingress buffer or (ii) a pending write request being transferred to the write queue from the write staging buffer, the write staging buffer marks a memory bank, associated with the incoming read request or the pending write request, as busy for a first duration,
the memory bank being marked as idle or not busy at an expiration of the first duration.
8. The control circuit of claim 6, wherein the write staging buffer is configured to mark a memory tile as busy for a first duration in response to the memory tile being addressed by a pending write request being transferred to the write queue from the write staging buffer, and
the write staging buffer is further configured to mark the memory tile as idle or not busy at an expiration of the first duration.
7. The memory system of claim 6, wherein in response to (i) an incoming read request being transferred to the read queue from the read ingress buffer or (ii) a pending write request being transferred to the write queue from the write staging buffer, the write staging buffer marks a memory bank, associated with the incoming read request or the pending write request, as busy for a first duration,
the memory bank being marked as idle or not busy at an expiration of the first duration.
9. The control circuit of claim 7, wherein the write staging buffer is configured to transfer one or more pending write requests to the write queue in response to the memory tiles being addressed by the one or more pending write requests being marked as idle or not busy.
8. The memory system of claim 7, wherein the write staging buffer is configured to transfer one or more pending write requests to the write queue in response to the memory banks associated with the one or more pending write requests being marked as idle or not busy.
10. The control circuit of claim 8, wherein the write staging buffer is configured to transfer one or more pending write requests to the write queue in response to the memory tiles being addressed by the one or more pending write requests being marked as idle or not busy.
8. The control circuit of claim 8, wherein the write staging buffer is configured to transfer one or more pending write requests to the write queue in response to the memory tiles being addressed by the one or more pending write requests being marked as idle or not busy.
11. The control circuit of claim 7, wherein the write staging buffer is configured to keep one or more pending write requests in the write staging buffer in response to the memory tiles being addressed by the one or more pending write requests being marked as busy.
9. The memory system of claim 7, wherein the write staging buffer is configured to keep one or more pending write requests in the write staging buffer in response to the memory banks associated with the one or more pending write requests being marked as busy.
12. The control circuit of claim 8, wherein the write staging buffer is configured to keep one or more pending write requests in the write staging buffer in response to the memory tiles being addressed by the one or more pending write requests being marked as busy.
9. The memory system of claim 7, wherein the write staging buffer is configured to keep one or more pending write requests in the write staging buffer in response to the memory banks associated with the one or more pending write requests being marked as busy.
13. The control circuit of claim 7, wherein (i) the first duration has a first value in response to the incoming read request being transferred to the read queue and (ii) the first duration has a second value in response to the pending write request being transferred to the write queue, the second value being different from the first value.
10. The memory system of claim 7, wherein (i) the first duration has a first value in response to the incoming read request being transferred to the read queue and (ii) the first duration has a second value in response to the pending write request being transferred to the write queue, the second value being different from the first value.
14. The control circuit of claim 8, wherein (i) the first duration has a first value in response to the incoming read request being transferred to the read queue and (ii) the first duration has a second value in response to the pending write request being transferred to the write queue, the second value being different from the first value.
10. The memory system of claim 7, wherein (i) the first duration has a first value in response to the incoming read request being transferred to the read queue and (ii) the first duration has a second value in response to the pending write request being transferred to the write queue, the second value being different from the first value.
15. The control circuit of claim 3, further comprising:
a bank tracker configured to track status of the memory tiles having read requests or write requests being sent to the memory device, the bank tracker identifying a memory tile as busy in response to a read or write request being sent to the memory device and identifying a memory tile as idle or not busy in response to (i) no request being sent or (ii) previously sent request being completed, wherein the write staging buffer obtains the status of the memory tiles from the bank tracker.
11. The memory system of claim 3, wherein the control circuit further comprises
a bank tracker configured to track status of the memory banks having read requests or write requests being sent to the memory device, the bank tracker identifying a memory bank as busy in response to a read or write request being sent to the memory device and identifying a memory bank as idle or not busy in response to (i) no request being sent or (ii) previously sent request being completed, wherein the write staging buffer obtains the status of the memory banks from the bank tracker.
16. The control circuit of claim 6, wherein the read ingress buffer provides a memory address of a first incoming read request to the write staging buffer, the write staging buffer compares the memory address of the first incoming read request with memory addresses of the pending write requests stored in the write staging buffer; and in response to the memory address of the first incoming read request matching a first memory address of the memory addresses in the write staging buffer where the first memory address corresponding to a memory address of a first pending write request of the pending write requests, the write staging buffer transfers the first pending write request to the write queue and the read ingress buffer transfers the first incoming read request to the read queue, the read queue obtaining read data, for the first incoming read request, from the first pending write request in the write queue.
12. The memory system of claim 6, wherein the read ingress buffer provides a memory address of a first incoming read request to the write staging buffer, the write staging buffer compares the memory address of the first incoming read request with memory addresses of the pending write requests stored in the write staging buffer; and in response to the memory address of the first incoming read request matching one of the memory addresses, wherein the one of the memory addresses correspond to a memory address of a first pending write request of the pending write requests, the write staging buffer transfers the first pending write request to the write queue and the read ingress buffer transfers the first incoming read request to the read queue, the read queue obtaining read data, for the first incoming read request, from the first pending write request in the write queue.
17. The control circuit of claim 6, wherein:
each incoming write request comprises write data for a page of memory data in a memory tiles, the page comprising a plurality of bytes of data; and
the write ingress buffer receives a partial write request including a valid byte indicator, the partial write request comprising write data for a subset of bytes in a first page of memory data and the valid byte indicator identifies one or more bytes of memory data in the first page to be modified; and
in response to the write ingress buffer receiving the partial write request, the partial write request is stored in the write staging buffer, the write staging buffer compares a memory address of the partial write request with memory addresses of the pending write requests; and
in response to the memory address of the partial write request matching a first memory address of the memory addresses, the first memory address corresponding to a memory address of a first pending write request of the pending write requests, the write staging buffer transfers the first pending write request to the write queue and then transfers the partial write request to the write queue, the write queue modifies write data for the first pending write request using the write data of the partial write request and the valid byte indicator.
13. The memory system of claim 6, wherein:
each incoming write request comprises write data for a page of memory data in a memory bank, the page comprising a plurality of bytes of data; and
the write ingress buffer receives a partial write request including a valid byte indicator, the partial write request comprising write data for a subset of bytes in a first page of memory data and the valid byte indicator identifies one or more bytes of memory data in the first page to be modified; and
in response to the write ingress buffer receiving the partial write request, the partial write request is stored in the write staging buffer, the write staging buffer compares a memory address of the partial write request with memory addresses of the pending write requests; and
in response to the memory address of the partial write request matching one of the memory addresses, wherein the one of the memory addresses correspond to a memory address of a first pending write request of the pending write requests, the write staging buffer transfers the first pending write request to the write queue and then transfers the partial write request to the write queue, the write queue modifies write data for the first pending write request using the write data of the partial write request and the valid byte indicator.
18. The control circuit of claim 1, wherein the control circuit comprises control circuitry formed in a general purpose integrated circuit.
15. The memory system of claim 1, wherein the control circuit comprises control circuitry formed in a general purpose integrated circuit.
19. The control circuit of claim 1, wherein the control circuit comprises a controller device formed in a discrete semiconductor die.
16. The memory system of claim 1, wherein the control circuit comprises a controller device formed in a discrete semiconductor die.
Regarding claim 1, Patent ‘749 teaches active read and write requests to plurality of tiles but does not appear to explicitly teach i) said plurality of tiles, each operates independently of one another and ii) said active read and write requests, each address a respective tile in said plurality of tiles.
However, Iyer teaches i) different memory banks (plurality of tiles) operate independently of each other (see Iyer ¶[95]) and ii) handling all (each) virtualized memory access requests (active requests) by translating virtualized memory addresses to physical addresses that are identified (addressed) by letter of memory bank (respective tile) (see Iyer ¶[104], [110], Iyer claim 3) wherein said memory access requests (active read and write requests) includes read (read) and write (write) (see Iyer ¶[115]).
In view of Iyer, Patent ‘749 is modified such that said plurality of tiles operate independently of each other, and said active read and write requests, all (each), are translated to physical addresses that are identified (addressed) by letter of memory bank (respective tile).
Patent ‘749 and Iyer are analogous art to the claimed invention because they are in the same field of endeavor storage management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify Patent ‘749 in the manner described supra because it would allow for creation of high speed and high-bandwidth memory (Iyer, ¶[95])
Claim 20 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,210,749 in view of Iyer (US 20150339227), and further in view of Inbar (US 20210389879).
Regarding claim 20, Patent ‘749 in view of Yyer teach the control circuit of claim 1.
Modified Patent ‘749 teaches a control circuit with memory device (see claim 1). The claimed invention improves upon said control circuit by connecting said control circuit to said memory device in the following manner (see also limitation below).
wherein the control circuit comprises a controller device formed in a semiconductor die separate from a semiconductor die on which the memory device is formed and interconnected to the memory device through interconnect structures
This improvement to said base method is an application of known technique from Inbar – connecting control circuity to memory structure via electrical paths. In particular, Inbar teaches
wherein [the] control circuit comprises a controller device formed in a semiconductor die separate from a semiconductor die on which [the] memory device is formed and interconnected to the memory device through interconnect structures (Inbar teaches bonded die pair of control circuitry 310 (control circuit) formed on control die 608 (semiconductor die) and memory structure 326 formed (memory device) formed on memory die 610 (semiconductor die) wherein said control die 608 is connected to said memory structure 326 via electrical paths 614 and 612 (interconnect structures) (see Fig. 6A, ¶[49-50]). Inbar also teaches, for said bonded die pair, said control circuity includes (comprises) elements of memory controller (controller device) (see ¶[124]).)
One of ordinary skill in the art would recognize that this known technique of implementing control circuity and memory structure on dies can also be applied to implement modified Patent ‘749’s control circuit and memory device, and the result would have been predictable. In this instance, said control circuity would be formed on a control die that is connected, via electrical paths to said memory device that is formed on a memory die wherein said control circuitry also includes elements of memory controller. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Inbar’s known technique would have yielded i) predictable result of said control circuity would be formed on a control die (semiconductor die) that is connected, via electrical paths (interconnect structures) to said memory device that is formed on a memory die (semiconductor die) wherein said control circuitry also includes elements of memory controller (controller device), and ii) the improved claimed invention (see MPEP 2143(I)(D)).
Allowable Subject Matter
Claim 1 recites, at least, write staging buffer transferring pending write requests to write queue that store active write requests to plurality of tiles wherein said pending write requests are transferred to maximize number of said active write requests that are addressed to different tiles. This subject matter is reflected in the following limitations of claim 1.
a write queue configured to store active write requests for writing data to the memory device, each active write request being addressed to a respective tile in the plurality of tiles; and
a write staging buffer configured to store pending write requests received by the control circuit and to transfer the pending write requests to the write queue to maximize a number of the active write requests in the write queue that are addressed to different tiles of the memory device
Resnick (US 20090150624) teaches request queue 110 (write staging buffer) storing memory requests (pending write requests) (such as read (read) and write (write) operations (see Resnick ¶[4])) that are decoded and stored in one of bank queues 130 (write queue) (see Resnick Fig. 2, ¶[28-29]) wherein i) said bank queues 130 is separated into read queues (read queue) and write queues (write queue) to track writes (active write requests) relative to reads (active read requests) (see Resnick ¶[31]) and ii) if a bank is busy, request is selected from said bank queues 130 for a bank that is free (different tiles) (see Resnick ¶[42]). Resnick also teaches sending, from said request queue 110, said memory requests to said bank queues to allow for back-to-back (maximize) accesses to same page (see Resnick ¶[43]) within a bank (see Resnick ¶[3]). While Resnick teaches transmitting said memory requests (pending write requests) to said bank queues (write queue) for back-to-back (maximize) accesses to same page, said transmitting is to same bank and not to maximize accesses to different banks (tiles). In addition, absent hindsight reconstruction, it would not be obvious to move selection of request, from said bank queues 130 (write queue), to free bank onto transmitting of said memory requests from said request queue 110 (write staging buffer) to said bank queues 130 (write queue). Therefore, claim 1 is allowable over Resnick.
Claims, dependent upon independent claim 1, are also allowable for the same reasons as said independent claim.
Conclusion
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/CHIE YEW/ Primary Examiner, Art Unit 2139