DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 9-15, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lidman et al. (US Pub. No. 2020/0379923), hereinafter referred to as Lidman.
Referring to claim 1, Lidman discloses a control chip (NOTE: the Applicant’s Specification indicates that a machine/computer loaded with program code “becomes a control chip and a storage circuit for practicing the methods” of the claimed invention, which is broader than generally accepted definition of a “chip” in the art; therefore, in the examination, the limitation “chip” is not being interpreted according to the typical narrow definition of the term) comprising: a first processing circuit providing a learning procedure and learning data (one or more of the neural network models 102 may be provided to (e.g., stored on) the user device 110, [0024]); a second processing circuit configured to execute the learning procedure (the NPU 320 to execute a trusted neural network application, [0040]); and a storage circuit storing the learning procedure and the learning data (fig. 6, Memory 620), wherein: in response to an access request pointing to the learning procedure: the storage circuit determines whether the access request is a correct access request (MPU 610 may be configured to filter memory access transactions 602-606 intended for the memory 620, [0061]), in response to the access request being the correct access request, the storage circuit provides the learning procedure to the second processing circuit (first secure memory zone 622 may store one or more neural network models…selectively deny or allow transactions for the secure memory zones 622-628. For example, the first zone filter 612 may only allow the ACPU and/or NPU to access data stored in the first secure memory zone 622, [0060-0061]), in response to the access request pointing to the learning data: the storage circuit determines whether the access request is provided from the second processing circuit and decodes identification information to generate a decoded result (a memory access transaction 400 may include…a master identifier (ID) 440…a unique identifier assigned to a particular master or group of masters...the NPU 320 may have a unique master ID (Master_ID_NPU), [0047-0048]), in response to the access request being provided from the second processing circuit and the decoded result corresponding to the second processing circuit (each of the zone filters 612-618 may be configured to deny access to its respective secure memory zone 622-628 if the transaction does not include the proper master ID, [0062]), the storage circuit provides the learning data to the second processing circuit (the second secure memory zone 624 may store one or more intermediate inferences, the third secure memory zone 626 may store one or more inference results, and the fourth secure memory zone 628 may store user input data…the second and third zone filters 614 and 616 may only allow the NPU to access data stored in the second and third secure memory zones 624 and 626, respectively; and the fourth zone filter 618 may only allow the IPU or NPU to access data stored in the fourth secure memory zone 628, [0060-0061]).
As to claim 2, Lidman discloses in response to the access request pointing to the learning procedure, the storage circuit determines whether the access request is provided from the second processing circuit and whether the access request is an instruction fetch request, and responsive to determining that the access request is provided from the second processing circuit and the access request is an instruction fetch request, the storage circuit determines that the access request is the correct access request (first secure memory zone 622 may store one or more neural network models…selectively deny or allow transactions for the secure memory zones 622-628. For example, the first zone filter 612 may only allow the ACPU and/or NPU to access data stored in the first secure memory zone 622, [0060-0061]).
As to claim 3, Lidman discloses in response to the access request not being provided from the second processing circuit or the access request not being an instruction fetch request, the storage circuit does not provide the learning procedure to the second processing circuit (each of the zone filters 612-618 may be configured to deny access to its respective secure memory zone 622-628 if the transaction does not include the proper master ID, [0062]).
As to claim 4, Lidman discloses the storage circuit comprises: a memory (fig. 6, memory 620) comprising: a first region configured to store the learning procedure (fig. 6, secure zone 622 Neural Network Model); and a second region configured to store the learning data (fig. 6, secure zone 624/626/628); and a control circuit (fig. 6, MPU 610) accessing the first or second region according to the access request (selectively deny or allow transactions for the secure memory zones 622-628, [0061]).
As to claim 9, Lidman discloses the second processing circuit is a neural network operating accelerator (a neural network processing unit (NPU), [0005]) which performs a machine learning inference operation according to the learning procedure and the learning data (generate one or more inferences about the input data…generate the inferences based on the neural network models 102 provided by the deep learning environment 101, [0026]) and the memory is a read only memory (NOTE: Lidman teaches the memory may be implemented using various forms of volatile or non-volatile storage in paragraph [0058], and then demonstrates the anticipation of the specific non-volatile ROM memory in paragraph [0078]).
As to claim 10, Lidman discloses in response to the access request pointing to the learning data: in response to the access request not being provided from the second processing circuit or the access request not being an instruction fetch request, the storage circuit does not provide the learning data to the second processing circuit (each of the zone filters 612-618 may be configured to deny access to its respective secure memory zone 622-628 if the transaction does not include the proper master ID, [0062]).
Referring to claim 11, Lidman discloses a storage circuit (fig. 3, 6) comprising: a memory (fig. 6, memory 620) comprising: a first region storing a learning procedure (fig. 6, secure zone 622 Neural Network Model); and a second region storing learning data (fig. 6, secure zone 624/626/628); and a control circuit (fig. 6, MPU 610) determining whether to access the first or second region according to an access request (selectively deny or allow transactions for the secure memory zones 622-628, [0061]), wherein: in response to the access request pointing to the first region: the control circuit determines whether the access request is a correct access request (MPU 610 may be configured to filter memory access transactions 602-606 intended for the memory 620, [0061]), responsive to determining that the access request is a correct access request, the control circuit outputs the learning procedure stored in the first region (first secure memory zone 622 may store one or more neural network models…selectively deny or allow transactions for the secure memory zones 622-628. For example, the first zone filter 612 may only allow the ACPU and/or NPU to access data stored in the first secure memory zone 622, [0060-0061]), in response to the access request pointing to the second region: the control circuit determines whether the access request is provided by a specific circuit, the control circuit decodes identification information to generate a decoded result (a memory access transaction 400 may include…a master identifier (ID) 440…a unique identifier assigned to a particular master or group of masters...the NPU 320 may have a unique master ID (Master_ID_NPU), [0047-0048]), and responsive to determining that the access request is provided by the specific circuit, the control circuit outputs the learning data stored in the second region to the specific circuit (the second secure memory zone 624 may store one or more intermediate inferences, the third secure memory zone 626 may store one or more inference results, and the fourth secure memory zone 628 may store user input data…the second and third zone filters 614 and 616 may only allow the NPU to access data stored in the second and third secure memory zones 624 and 626, respectively; and the fourth zone filter 618 may only allow the IPU or NPU to access data stored in the fourth secure memory zone 628, [0060-0061]).
As to claim 12, Lidman discloses in response to the access request pointing to the first region: the control circuit determines whether the access request is provided by the specific circuit and whether the access request is an instruction fetch request, responsive to determining that the access request is provided by the specific circuit and the access request is an instruction fetch request, it is determined that the access request is the correct access request, and responsive to determining that the access request is a correct access request, the control circuit outputs the learning procedure to the specific circuit (first secure memory zone 622 may store one or more neural network models…selectively deny or allow transactions for the secure memory zones 622-628. For example, the first zone filter 612 may only allow the ACPU and/or NPU to access data stored in the first secure memory zone 622, [0060-0061]).
As to claim 13, Lidman discloses in response to the access request pointing to the first region: responsive to determining that the access request is not provided by the specific circuit or the access request is not an instruction fetch request, the control circuit does not access the first region (each of the zone filters 612-618 may be configured to deny access to its respective secure memory zone 622-628 if the transaction does not include the proper master ID, [0062]).
As to claim 14, Lidman discloses in response to the access request pointing to the second region: responsive to determining that the access request is not provided by the specific circuit or the decoded result does not correspond to the specific circuit, the control circuit does not access the second region (each of the zone filters 612-618 may be configured to deny access to its respective secure memory zone 622-628 if the transaction does not include the proper master ID, [0062]).
As to claim 15, Lidman discloses a first interface circuit configured to receive the identification information and the access request and provide the identification information and the access request to the control circuit (fig. 3, interface circuit between MPU and masters 310-330; [0045-0047]).
Referring to claim 20, Lidman discloses a protection method for a control chip (NOTE: the Applicant’s Specification indicates that a machine/computer loaded with program code “becomes a control chip and a storage circuit for practicing the methods” of the claimed invention, which is broader than generally accepted definition of a “chip” in the art; therefore, in the examination, the limitation “chip” is not being interpreted according to the typical narrow definition of the term), comprising: storing a learning procedure and learning data to a memory (fig. 6, Memory 620; one or more of the neural network models 102 may be provided to (e.g., stored on) the user device 110, [0024]); in response to an access request pointing to the learning procedure: determining whether the access request is provided from a specific circuit (MPU 610 may be configured to filter memory access transactions 602-606 intended for the memory 620, [0061]); determining whether the access request is an instruction fetch request; responsive to determining that the access request is provided from the specific circuit and the access request is an instruction fetch request, outputting the learning procedure to the specific circuit (first secure memory zone 622 may store one or more neural network models…selectively deny or allow transactions for the secure memory zones 622-628. For example, the first zone filter 612 may only allow the ACPU and/or NPU to access data stored in the first secure memory zone 622, [0060-0061]); in response to the access request pointing to the learning data: determining whether the access request is provided from the specific circuit, decoding identification information to generate a decoded result (a memory access transaction 400 may include…a master identifier (ID) 440…a unique identifier assigned to a particular master or group of masters...the NPU 320 may have a unique master ID (Master_ID_NPU), [0047-0048]), and responsive to determining that the access request is provided from the specific circuit and the decoded result corresponds to the specific circuit (each of the zone filters 612-618 may be configured to deny access to its respective secure memory zone 622-628 if the transaction does not include the proper master ID, [0062]), outputting the learning data to the specific circuit (the second secure memory zone 624 may store one or more intermediate inferences, the third secure memory zone 626 may store one or more inference results, and the fourth secure memory zone 628 may store user input data…the second and third zone filters 614 and 616 may only allow the NPU to access data stored in the second and third secure memory zones 624 and 626, respectively; and the fourth zone filter 618 may only allow the IPU or NPU to access data stored in the fourth secure memory zone 628, [0060-0061]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lidman in view of Lee et al. (US Pub. No. 2009/0164709), hereinafter referred to as Lee.
As to claim 5, while Lidman discloses the storage circuit further comprises: a third region configured to store setting data (fig. 6, Secure Zone 628, User Input Data) and the first and second regions, Lidman does not appear to explicitly disclose the control circuit sets a size of the region according to setting data.
However, in a similar endeavor of managing secure storage areas, Lee discloses user input such that the control circuit sets a size of the region according to setting data ([0036], [0047], [0051]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Lidman and Lee before him or her, to modify the secure storage system of Lidman to include the dynamic configuration of Lee because the dynamic configuration would allow secure storage to be adapted to the current needs.
The suggestion/motivation for doing so would have been to vary storage configuration based on user needs (Lee: [0036]).
Therefore, it would have been obvious to combine Lidman and Lee to obtain the invention as specified in the instant claim.
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Lidman in view Lee, as applied to claim 5 above, further in view of Watanabe et al. (US Pub. No. 2023/0024977), hereinafter referred to as Watanabe.
As to claim 6, while Lidman discloses the control circuit interacting with the learning procedure from the first region, the learning data from the second region, and the setting data from the third region, Lidman does not appear to explicitly disclose an erasure procedure for the first, second, and third regions.
However, Watanabe discloses an erasure procedure applicable to different regions (for each target processing layer, an area to store an input deletion bit (one bit) as an example of information indicating whether to delete data, and an area to store transfer determination bits (two bits) as an example of information indicating a forwarding destination. The input deletion bit holds information indicating whether to delete target uncompressed intermediate data input into the target processing layer from the SRAM 40, [0045]).
Lidman, Lee, and Watanabe are analogous art because they are from the same field of endeavor, managing data storage areas.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Lidman, Lee, and Watanabe before him or her, to modify the secure storage system of Lidman in view of Lee to include the erasure procedure of Lee because the deletion management features would efficiently manage memory capacity while preventing erroneous deletion of data.
The suggestion/motivation for doing so would have been to prevent data from being erroneously deleted (Watanabe: [0047]).
Therefore, it would have been obvious to combine Lidman, Lee, and Watanabe to obtain the invention as specified in the instant claim.
As to claim 7, Lidman discloses the storage circuit further comprises: a first interface circuit configured to receive the identification information and the access request and provide the identification information and the access request to the control circuit, wherein the control circuit determines whether to read the first and second regions according to the access request (fig. 3, interface circuit between MPU and masters 310-330; [0045-0047]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Lidman, Lee, and Watanabe, as applied to claims 6-7 above, further in view of Jeong et al. (US Pub. No. 2023/0244534) .
As to claim 8, Lidman discloses the storage circuit further comprises: a second interface circuit configured to receive data (input sources 112 may be configured to receive user inputs and/or collect data, [0025]), providing data to a register circuit (computer system memories or registers, [0017]) which is provisionally stored (input data captured by the input sources 112 and/or media content stored or buffered on the user device 110, [0026]; memory 116 may store the input data received via the input sources 112…memory 116 may buffer [0028]), and Lidman separately discusses moving the learning procedure to the first region and moving the learning data to the second region (one or more of the neural network models 102 may be provided to (e.g., stored on) the user device 110, [0024]; fig. 6, secure zone 622 Neural Network Model, secure zone 624/626/628 data). While Lidman teaches all of the claimed components, a second interface, a register circuit, the control circuit, and the memory containing the first and second regions, Lidman does not appear to apply a technique of moving received data from provisional storage to another memory.
However, Jeong teaches the technique of moving received data from provisional storage to another memory (buffer 121 may temporarily store data with respect to the neural network model…data stored in the buffer 121 may be transmitted to the memory 110, [0059-0062]).
Lidman, Lee, Watanabe, and Jeong are analogous art because they are from the same field of endeavor, storage management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Lidman, Lee, Watanabe, and Jeong before him or her, to improve the secure storage system of Lidman with the temporary data buffering technique of Jeong because Lidman demonstrated a “base” device upon which the claimed invention can be seen as an improvement for provisionally storing data, Jeong demonstrates a “comparable” device which has been improved to provisionally store data in buffer before moving data to memory, and one of ordinary skill in the art could have applied the known “improvement” technique of providing temporary buffering of data in the same way to the “base” device with the necessary components, and the result would have been a predictable temporary storage arrangement and functionality. The rationale to support a conclusion that the claim would have been obvious is that a method of enhancing a particular class of devices (methods, or products) has been made part of the ordinary capabilities of one skilled in the art based upon the teaching of such improvement in other situations (see MPEP 2143.I.C). Additionally, the “improvement” technique benefits capacity limitations between different storage elements, as suggested by teachings of Jeong in paragraphs [0059-0061], and therefore the recognized advantages provide further motivation to combine.
Therefore, it would have been obvious to combine Lidman, Lee, Watanabe, and Jeong to obtain the invention as specified in the instant claim.
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Lidman in view of Jeong.
As to claim 16, Lidman discloses a register circuit (computer system memories or registers, [0017]) and a second interface circuit configured to receive data (input sources 112 may be configured to receive user inputs and/or collect data, [0025]), providing the data to the register circuit, which is provisionally stored in the register circuit (input data captured by the input sources 112 and/or media content stored or buffered on the user device 110, [0026]; memory 116 may store the input data received via the input sources 112…memory 116 may buffer [0028]), and Lidman separately discusses moving the learning procedure to the first region and moving the learning data to the second region (one or more of the neural network models 102 may be provided to (e.g., stored on) the user device 110, [0024]; fig. 6, secure zone 622 Neural Network Model, secure zone 624/626/628 data). While Lidman teaches all of the claimed components, a register circuit, a second interface, the control circuit, the memory containing the first and second regions, Lidman does not appear to apply a technique of moving received data from provisional storage to another memory.
However, Jeong teaches the technique of moving received data from provisional storage to another memory (buffer 121 may temporarily store data with respect to the neural network model…data stored in the buffer 121 may be transmitted to the memory 110, [0059-0062]).
Lidman and Jeong are analogous art because they are from the same field of endeavor, storage management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Lidman and Jeong before him or her, to improve the secure storage system of Lidman with the temporary data buffering technique of Jeong because Lidman demonstrated a “base” device upon which the claimed invention can be seen as an improvement for provisionally storing data, Jeong demonstrates a “comparable” device which has been improved to provisionally store data in buffer before moving to memory, and one of ordinary skill in the art could have applied the known “improvement” technique of providing temporary buffering of data in the same way to the “base” device with the necessary components, and the result would have been a predictable temporary storage arrangement and functionality to one of ordinary skill in the art. The rationale to support a conclusion that the claim would have been obvious is that a method of enhancing a particular class of devices (methods, or products) has been made part of the ordinary capabilities of one skilled in the art based upon the teaching of such improvement in other situations (see MPEP 2143.I.C). Additionally, the “improvement” technique benefits capacity limitations between different storage elements, as suggested by teachings of Jeong in paragraphs [0059-0061], and therefore the recognized advantages provide further motivation to combine.
Therefore, it would have been obvious to combine Lidman and Jeong to obtain the invention as specified in the instant claim.
As to claim 17, Lidman discloses the memory is a read only memory (NOTE: Lidman teaches the memory may be implemented using various forms of volatile or non-volatile storage in paragraph [0058], and then demonstrates the anticipation of the specific non-volatile ROM memory in paragraph [0078]).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Lidman in view of Jeong, as applied to claims 16-17 above, further in view of Lee.
As to claim 18, while Lidman discloses the memory further comprises: a third region configured to store setting data (fig. 6, Secure Zone 628, User Input Data), and the first and second regions, Lidman does not appear to explicitly disclose the control circuit sets a size of the region according to setting data.
However, in a similar endeavor of managing secure storage areas, Lee discloses user input such that the control circuit sets a size of the region according to setting data ([0036], [0047], [0051]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Lidman, Jeong, and Lee before him or her, to modify the secure storage system of Lidman to include the dynamic configuration of Lee because the dynamic configuration would allow secure storage to be adapted to the current needs.
The suggestion/motivation for doing so would have been to vary storage configuration based on user needs (Lee: [0036]).
Therefore, it would have been obvious to combine Lidman, Jeong, and Lee to obtain the invention as specified in the instant claim.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Lidman, Jeong, and Lee, as applied to claim 18 above, further in view of Watanabe.
As to claim 19, while Lidman discloses the control circuit interacting with the learning procedure from the first region, the learning data from the second region, and the setting data from the third region, the combination of Lidman, Jeong, and Lee does not appear to explicitly disclose an erasure procedure for the first, second, and third regions.
However, Watanabe discloses an erasure procedure applicable to different regions (for each target processing layer, an area to store an input deletion bit (one bit) as an example of information indicating whether to delete data, and an area to store transfer determination bits (two bits) as an example of information indicating a forwarding destination. The input deletion bit holds information indicating whether to delete target uncompressed intermediate data input into the target processing layer from the SRAM 40, [0045]).
Lidman, Jeong, Lee, and Watanabe are analogous art because they are from the same field of endeavor, managing data storage areas.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Lidman, Jeong, Lee, and Watanabe before him or her, to modify the secure storage system of Lidman to include the erasure procedure of Lee because the deletion management features would efficiently manage memory capacity while preventing erroneous deletion of data.
The suggestion/motivation for doing so would have been to prevent data from being erroneously deleted (Watanabe: [0047]).
Therefore, it would have been obvious to combine Lidman, Jeong, Lee, and Watanabe to obtain the invention as specified in the instant claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The US Pub. No. 2020/0082279 of Arora et al. is pertinent to trusted execution environments for neural network applications. The US Pub. No. 2025/0173724 of Silver et al. is pertinent to distributed ledger technology to facilitate secure and transparent storage of neural network models and related data.
The examiner has cited particular column, line, and/or paragraph numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in its entirety as potentially teaching of all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111(c).
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC T OBERLY whose telephone number is (571)272-6991. The examiner can normally be reached on M-F 800am-430pm (MT).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on (571) 272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC T OBERLY/ Primary Examiner, Art Unit 2184
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