DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This office action is responsive to the application Nº 18/984,291 filed on December 17th, 2024 in which claims 1-14 are pending and ready for examination.
Information Disclosure Statement
3. Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS have been considered.
Priority
4. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Drawings
5. The examiner contends that the drawings submitted on 12/17/2024 are acceptable for examination proceedings.
Claim Rejections - 35 USC § 103
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claims 1-14 are rejected under 35 U.S.C. 103 as being unpatentable over Umeda et al. (US Pub. Nº 2017/0348979).
9. Regarding independent claim 1: Umeda et al. disclosed an element substrate ([0050], line 2; also see Fig. 4, reference 101), comprising:
a plurality of recording elements for discharging liquid ([0052], line 1; also see Fig. 4, references 102-i);
a plurality of first drive elements provided correspondingly to the plurality of recording elements, and driving the plurality of recording elements ([0051], line 2; also see Fig. 4, references 103);
a first control circuit for outputting first control signals for controlling the plurality of first drive elements ([0057], lines 5-6; also see Fig. 4, reference 204);
a plurality of circuits for delaying input of the first control signals such that the first control signals are input at different timings among the plurality of first drive elements ([0057], lines 6-8; also see Fig. 4, references 202 corresponding to each of the recording element groups 102-i);
a plurality of heat generating elements for heating the element substrate ([0053], lines 6-8; also see Fig. 4, references 115-I corresponding to respective recording element groups 102-i);
a plurality of second drive elements provided correspondingly to the plurality of heat generating elements, and driving the plurality of heat generating elements ([0053], line 8; also see Fig. 4, references 116-i);
a second control circuit for outputting second control signals for controlling the plurality of second drive elements ([0058], line 1; also see Fig. 4, reference 209); and
a plurality of flip-flop circuits ([0059], lines 4-6; also see Fig. 5B, reference 208) for delaying input of the second control signals such that the second control signals are input at different timings among the plurality of second drive elements ([0058], lines 2-5; also see Fig. 4, references 208).
Umeda et al. did not explicitly disclose that the circuits for delaying input of the first control signals consist of a plurality of inverter circuits.
However, in the embodiment of Fig. 5A, Umeda disclosed delay circuits consisting of a plurality of inverter circuits ([0059], lines 1-2; also see Fig. 5A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of the embodiment of Fig. 4 with those of the embodiment of Fig. 5A by using delay circuits consisting of a plurality of inverter circuits in order to use readily available technology and reduce production costs of the element substrate.
10. Regarding claim 2: Umeda et al. disclosed the element substrate according to claim 1, wherein the number of the plurality of flip-flop circuits is smaller than the number of the plurality of inverter circuits (see Figs. 4, 5 and 14; the number of flip-flop circuits 209 (1 for each heat generating element 115i) is less than the number of delay circuits corresponding to each of the control outputs HE-i (up to n for each group 102i)).
11. Regarding claim 3: Umeda et al. disclosed the element substrate according to claim 1, wherein the plurality of recording elements and the plurality of first drive elements are divided into a plurality of blocks ([0052], line 1; also see Fig. 4, references 102i), and wherein the inverter circuit is disposed in each of the plurality of blocks, and delays the first control signals such that the first control signals are input among the plurality of blocks at different timings (Fig. 4, respective control signal delay circuits 202 are provided for each block 102i, to delay the plurality of blocks at different timings).
12. Regarding claim 4: Umeda et al. disclosed the element substrate according to claim 3, wherein the heat generating element, the second drive element, and the flip-flop circuit are disposed in each of the plurality of blocks (Fig. 4, a respective heat generating element 115-i, the second drive element 116-i, and the flip-flop circuit 208 is provided for each of the plurality of blocks 102-i).
13. Regarding claim 5: Umeda et al. disclosed the element substrate according to claim 4, wherein the first control circuit receives a heat enable signal that determines a conduction time of the first drive element, and outputs, as the first control signal, recording data, a block selection signal, and a heat data signal that is logical AND of the heat enable signal ([0057], lines 4-9), and wherein the inverter circuit delays reception of the heat enable signal by the first control circuit ([0057], lines 6-8; also see the rejection of claim 1).
14. Regarding claim 6: Umeda et al. disclosed the element substrate according to claim 5, wherein the second control signal is a sub heat data signal output to the plurality of second drive elements in accordance with sub heat data that defines whether to drive the heat generating element in each of the plurality of blocks ([0058], lines 1-8), wherein the second control circuit outputs the sub heat data signal on the basis of reception of a latch signal, and wherein the flip-flop circuit delays the latch signal or the sub heat data signal ([0058], lines 6-8).
15. Regarding claim 7: Umeda et al. disclosed the element substrate according to claim 6, wherein a delay time of input of the first control signal by the inverter circuit is shorter than a delay time of input of the second control signal by the flip-flop circuit ([0062], lines 1-6. The driving time of the first drive elements is in the order of nanoseconds and the driving time of the heat generating elements is in the order of milliseconds).
16. Regarding claim 8: Umeda et al. disclosed the element substrate according to claim 1, wherein the flip-flop circuit is a D flip-flop circuit (see Fig. 5B).
17. Regarding claim 9: Umeda et al. disclosed the element substrate according to claim 1, wherein the plurality of inverter circuits is disposed in a nozzle row circuit corresponding to a nozzle row of a recording head to which the element substrate is mounted (see Fig. 4, each control signal delay circuit 202 corresponds to a nozzle row 102i of a recording head; also see the rejection on claim 1).
18. Regarding claim 10: Umeda et al. disclosed the element substrate according to claim 9, wherein the plurality of flip-flop circuits is disposed at an end portion circuit between an input/output portion for performing input and output from and to a recording apparatus, to which the recording head is mounted, and the nozzle row circuit (see Fig. 4).
19. Regarding claim 11: Umeda et al. disclosed the element substrate according to claim 1, wherein the plurality of recording elements and the plurality of heat generating elements are connected to common power source wiring ([0054], line 2-3).
20. Regarding claim 12: Umeda et al. disclosed the element substrate according to claim 1, wherein ground wiring of the plurality of recording element and ground wiring of the plurality of heat generating element are common ([0071], lines 3-4).
21. Regarding claim 13: Umeda et al. disclosed a recording head ([0050], lines 1-2; also see Fig. 3, reference 100), comprising the element substrate according to claim 1 (see the rejection of claim 1).
22. Regarding claim 14: Umeda et al. disclosed a recording apparatus ([0050], line 1; also see Fig. 1, reference 1) for causing ink to be ejected from the recording head according to claim 13 (see the rejection of claim 13) to a recording medium so as to implement recording (Fig. 1, reference P).
Conclusion
23. Any inquiry concerning this communication or earlier communications from the examiner should be directed to YAOVI M. AMEH whose telephone number is (571)272-4578. The examiner can normally be reached M-F: 9:00 AM - 6:00 PM.
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25. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, RICARDO MAGALLANES can be reached at (571)272-5960. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YAOVI M AMEH/Primary Examiner, Art Unit 2853
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