CTNF 18/984,322 CTNF 90564 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Note It is noted that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP § 2123. Information Disclosure Statement 06-52 An information disclosure statement (IDS) was submitted on 14 January 2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto- processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-34 AIA Claim s 1-2, 4-10, 12-17, 19-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1-20 of U.S. Patent No. 12210769 . Although the claims at issue are not identical, they are not patentably distinct from each other because they recite substantially similar subject matter and the limitations of the Patent/Copending Application would anticipate those of the current application as shown in the example claims in the table below . Instant Application U.S. Patent No. 12210769 1. A memory device, comprising: a memory array comprising a plurality of memory cells; and processing logic, operatively coupled to the memory array, to perform operations comprising: identifying, among the plurality of memory cells, a target memory cell and a set of memory cells adjacent to the target memory cell, wherein each memory cell of the set of memory cells is characterized by a respective memory cell state; determining, for each memory cell state, a respective interference value reflecting memory cell-to-memory cell interference; assigning, based on the respective interference value, each memory cell state to a respective bin of a set of state information bins; and determining a set of read level offsets for reading the target memory cell, wherein each read level offset of the set of read level offsets is associated with a respective bin of the set of state information bins. 1. A memory device comprising: a memory array; and control logic, operatively coupled with the memory array, to perform operations comprising: identifying, from the memory array, a target cell and a set of cells adjacent to the target cell, wherein each cell of the set of cells is associated with a respective adjacent cell state, and wherein each adjacent cell state reflects a logical level of the respective cell; determining, for each adjacent cell state, a respective interference value reflecting cell-to-cell interference on the target cell; assigning, based on the respective interference value, each adjacent cell state to a respective bin of a set of state information bins; determining whether each bin of the set of state information bins has at least one adjacent cell state assigned to it; and in response to determining that each bin of the set of state information bins has at least one adjacent cell state assigned to it, determining a set of read level offsets for reading the target cell, wherein each read level offset of the set of read level offsets is associated with a respective bin of the set of state information bins . 08-34 AIA Claim s 1-2, 4, 10, 17, and 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1-20 of U.S. Patent No. 12315574 or claims 1-20 of U.S. Patent No. 12266407 in view of Chilappagari (US 20130155776 A1) . Although the claims at issue are not identical, they are not patentably distinct from each other because they recite substantially similar subject matter and the claims of the issued Patent/Copending make obvious the claims of the current application as shown in the example claims in the table below. U.S. Patent No. 12315574 and/or U.S. Patent No. 12266407 do not explicitly disclose “determining, for each memory cell state, a respective interference value reflecting memory cell-to-memory cell interference; assigning, based on the respective interference value, each memory cell state to a respective bin of a set of state information bins” . Chilappagari teaches determining, for each memory cell state, a respective interference value reflecting memory cell-to-memory cell interference; ([Chilappagari 0020-0023, 0065, 0096-0099, Fig. 9B] The second information indicates a state of the second memory cell causing interference to the first memory cell. The system further includes a compensation module configured to compensate for the interference caused by the state of the second memory cell based on (i) the first information and (ii) the second information. Eight separate distributions corresponding to eight separate states are not observed since cells having some of the states cause similar inter-cell interference. For example, cells having states 1, 3, 5, and 7 cause similar inter-cell interference; cells having states 0, 4, and 6 cause similar inter-cell interference; and cells having state 2 cause similar inter-cell interference. Accordingly, while the cells can have eight possible states, only three threshold voltage distributions cause inter-cell interference. The inter-cell interference pattern is device-dependent. That is, the inter-cell interference pattern observed for a memory device is the same for all units of the memory device manufactured using the same process. Further, the inter-cell interference pattern (i.e., a pattern of aggressor cells causing inter-cell interference to victim cells) does not change throughout the life of the memory device although the memory device ages due to usage. The inter-cell interference pattern of a memory device is therefore a signature characteristic of the memory device.) assigning, based on the respective interference value, each memory cell state to a respective bin of a set of state information bins; ([Chilappagari 0101] The reference voltage module 112 generates reference voltages to read the memory cells. The binning module 114 divides threshold voltage distributions of the memory cells into a plurality of bins based on the reference voltages used to read the memory cells. The binning module 114 generates a bin index for each memory cell based on read operations performed on the memory cells using the reference voltages.) U.S. Patent No. 12315574 or U.S. Patent No. 12266407 and Chilappagari are analogous art because they are from the same field of endeavor in memory devices. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of U.S. Patent No. 12315574 / U.S. Patent No. 12266407 and Chilappagari before him or her to modify the memory device of U.S. Patent No. 12315574 or U.S. Patent No. 12266407 to include the inter-cell interference detection and compensation of Chilappagari, thereafter the memory device is connected to inter-cell interference detection and compensation. The suggestion and/or motivation for doing so would be obtaining the advantage of allowing the memory device to have more noise reduction and improved operability as suggested by Chilappagari. It is known to combine prior art elements according to known methods to yield predictable results. Therefore, it would have been obvious to combine U.S. Patent No. 12315574 or U.S. Patent No. 12266407 with Chilappagari to obtain the invention as specified in the instant application claims. Instant Application U.S. Patent No. 12315574 1. A memory device, comprising: a memory array comprising a plurality of memory cells; and processing logic, operatively coupled to the memory array, to perform operations comprising: identifying, among the plurality of memory cells, a target memory cell and a set of memory cells adjacent to the target memory cell, wherein each memory cell of the set of memory cells is characterized by a respective memory cell state; determining, for each memory cell state, a respective interference value reflecting memory cell-to-memory cell interference; assigning, based on the respective interference value, each memory cell state to a respective bin of a set of state information bins; and determining a set of read level offsets for reading the target memory cell, wherein each read level offset of the set of read level offsets is associated with a respective bin of the set of state information bins. 1. A memory device comprising: a memory array comprising: a set of target cells connected to a target wordline; at least one wordline adjacent to the target wordline; and for each target cell of the set of target cells, a respective group of adjacent cells adjacent to the target cell, wherein each group of adjacent cells comprises at least one cell connected to the at least one wordline; and control logic, operatively coupled with the memory array, to perform operations comprising: causing a read operation to be initiated with respect to the set of target cells; determining whether the read operation has failed; in response to determining that the read operation has failed, obtaining, for each group of adjacent cells, respective cell state information; assigning, based on the cell state information, each target cell of the set of target cells to a respective state information bin of a set of state information bins; determining whether to initiate auto-calibrated corrective read; in response to determining to initiate auto-calibrated corrective read, performing read level offset calibration to determine a set of calibrated read level offsets, wherein each calibrated read level offset of the set of calibrated read level offsets is associated with a respective state information bin of the set of state information bins; and causing the set of target cells to be read using the set of calibrated read level offsets. Instant Application U.S. Patent No. 12266407 1. A memory device, comprising: a memory array comprising a plurality of memory cells; and processing logic, operatively coupled to the memory array, to perform operations comprising: identifying, among the plurality of memory cells, a target memory cell and a set of memory cells adjacent to the target memory cell, wherein each memory cell of the set of memory cells is characterized by a respective memory cell state; determining, for each memory cell state, a respective interference value reflecting memory cell-to-memory cell interference; assigning, based on the respective interference value, each memory cell state to a respective bin of a set of state information bins; and determining a set of read level offsets for reading the target memory cell, wherein each read level offset of the set of read level offsets is associated with a respective bin of the set of state information bins. 1. A memory device comprising: a memory array comprising: a set of target cells connected to a target wordline; at least one wordline adjacent to the target wordline; and for each target cell of the set of target cells, a respective group of adjacent cells adjacent to the target cell, wherein each group of adjacent cells comprises at least one cell connected to the at least one wordline; and control logic, operatively coupled with the memory array, to perform operations comprising: causing a read operation to be initiated with respect to the set of target cells; obtaining, for each group of adjacent cells, respective cell state information; assigning, based on the respective cell state information, each target cell of the set of target cells to a respective state information bin of a set of state information bins, wherein each state information bin is associated with a respective group of target cells of the set of target cells; and determining a set of calibrated read level offsets, wherein each calibrated read level offset of the set of calibrated read level offsets is associated with a respective state information bin of the set of state information bins. A complete response to a nonstatutory double patenting (NSDP) rejection is either a reply by applicant showing that the claims subject to the rejection are patentably distinct from the reference claims or the filing of a terminal disclaimer in accordance with 37 CFR 1.321 in the pending application(s) with a reply to the Office action (see MPEP § 1490 for a discussion of terminal disclaimers). Such a response is required even when the nonstatutory double patenting rejection is provisional. As filing a terminal disclaimer, or filing a showing that the claims subject to the rejection are patentably distinct from the reference application’s claims, is necessary for further consideration of the rejection of the claims, such a filing should not be held in abeyance. Only objections or requirements as to form not necessary for further consideration of the claims may be held in abeyance until allowable subject matter is indicated. see MPEP § 804 Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1, 2, 4, 10, 17, and 19 is/are rejected under 35 U.S.C. 102 (a)(1)/(a)(2) as being anticipated by Chilappagari (US 20130155776 A1) . Referring to claims 1, 10, and 17, taking claim 1 as exemplary, Chilappagari teaches A memory device, comprising: a memory array comprising a plurality of memory cells; ([Chilappagari abstract, 0020, 0100, Figs. 6A, 9A] memory arrays include memory cells) and processing logic, operatively coupled to the memory array, to perform operations comprising: ([Chilappagari 0100, Figs. 6A, 9A] In FIG. 9A, the memory IC 100 includes the memory array 12, a WL/BL decoder module 102, and a control module 104. The control module 104 includes a read module 110, a reference voltage module 112, a binning module 114, an aggressor state determination module 116, an LLR module 118, a compensation module 120, a mapping module 122, and a decoder module 124.) identifying, among the plurality of memory cells, a target memory cell and a set of memory cells adjacent to the target memory cell, wherein each memory cell of the set of memory cells is characterized by a respective memory cell state; ([Chilappagari abstract, 0020, 0054, 0056, 0108] The read module is configured to generate second information about a second memory cell by reading the second memory cell. The second memory cell is located along (i) the first word line, (ii) a second word line that is adjacent to the first word line, or (iii) a second bit line that is adjacent to the first bit line. The second information indicates a state of the second memory cell causing interference to the first memory cell. The present disclosure relates to canceling the effects of inter-cell interference on data stored in memory cells along a word line by reading the memory cells along the word line and also reading memory cells in adjacent word lines. Information obtained by reading memory cells in the adjacent word lines is used to compensate effects of inter-cell interference on data stored in memory cells along the word line. Accordingly, data stored in memory cells along a word line is decoded using information obtained by reading the memory cells along the word line and by reading the memory cells along adjacent word lines.) determining, for each memory cell state, a respective interference value reflecting memory cell-to-memory cell interference; ([Chilappagari 0020-0023, 0065, 0096-0099, Fig. 9B] The second information indicates a state of the second memory cell causing interference to the first memory cell. The system further includes a compensation module configured to compensate for the interference caused by the state of the second memory cell based on (i) the first information and (ii) the second information. Eight separate distributions corresponding to eight separate states are not observed since cells having some of the states cause similar inter-cell interference. For example, cells having states 1, 3, 5, and 7 cause similar inter-cell interference; cells having states 0, 4, and 6 cause similar inter-cell interference; and cells having state 2 cause similar inter-cell interference. Accordingly, while the cells can have eight possible states, only three threshold voltage distributions cause inter-cell interference. The inter-cell interference pattern is device-dependent. That is, the inter-cell interference pattern observed for a memory device is the same for all units of the memory device manufactured using the same process. Further, the inter-cell interference pattern (i.e., a pattern of aggressor cells causing inter-cell interference to victim cells) does not change throughout the life of the memory device although the memory device ages due to usage. The inter-cell interference pattern of a memory device is therefore a signature characteristic of the memory device.) assigning, based on the respective interference value, each memory cell state to a respective bin of a set of state information bins; ([Chilappagari 0101] The reference voltage module 112 generates reference voltages to read the memory cells. The binning module 114 divides threshold voltage distributions of the memory cells into a plurality of bins based on the reference voltages used to read the memory cells. The binning module 114 generates a bin index for each memory cell based on read operations performed on the memory cells using the reference voltages.) and determining a set of read level offsets for reading the target memory cell, wherein each read level offset of the set of read level offsets is associated with a respective bin of the set of state information bins ([Chilappagari 0101, 0110-0112, 0129] The reference voltage module 112 generates reference voltages to read the memory cells. The binning module 114 divides threshold voltage distributions of the memory cells into a plurality of bins based on the reference voltages used to read the memory cells. The binning module 114 generates a bin index for each memory cell based on read operations performed on the memory cells using the reference voltages. The aggressor cells can be parameterized by word line number and bit line number of the aggressor cells. Specifically, for each victim cell, locations of corresponding aggressor cells can be specified in terms of offsets of word line numbers and bit line numbers. For example, in FIG. 7A, if a victim cell is located at word line i and bit line j, aggressor cells may be located at word line i+1 and bit line j-1, word line i and bit line j-1, and/or word line i+1 and bit line j. The parameters or offsets provide a spatial indication of where the aggressor cells are located with respect to a victim cell. Accordingly, an inter-cell interference pattern for a memory device can be specified in terms of offsets of word line numbers and bit line numbers of victim cells and corresponding aggressor cells. The read module 110 utilizes the inter-cell interference pattern to perform read operations and includes the offset information in the data generated from each read operation so that the soft information and aggressor state information can be properly updated. the aggressor cell can be on bit line j+k, where k is any integer. Accordingly, data from each read operation should include the value of k. For example, let the aggressor cell be at word line i+1 and bit line j+1. In this case, when a page in word line i+1 is read, a descriptor is programmed to indicate that data from the read operation includes aggressor state information with k=1. So the value for bit line m in a new read should go into the bin index memory for bit line m-1. Another aggressor cell can be at word line i+2 and bit line j-1. In this case, when a page in word line i+2 is read, the descriptor is programmed to indicate that data from the read operation includes aggressor state information with k=-1. In this case, the value for bit line m in the new read should go into the bin index memory for bit line m+1.) . With regards to the non-exemplary limitations of claims 10, Chilappagari teaches and causing a corrective read operation to be performed, using the set of read level offsets, with respect to the target memory cell ([Chilappagari 0055] To correct the effects of inter-cell interference on data stored in memory cells along a word line, the memory cells along the word line can be read repeatedly. Information obtained by repeatedly reading the memory cells along a word line is used to decode the data stored in the memory cells along the word line.) . With regards to the non-exemplary limitations of claims 17, Chilappagari teaches and responsive to determining that each bin of the set of state information bins has at least one memory cell state assigned to it, ([Chilappagari 0073-0078, 0101] By performing three reads, the threshold voltage of the cell can be binned into one of the four regions or bins. Cells having threshold voltages in bin 0 are more likely to have stored a -1, and cells having threshold voltages in bin 3 are more likely to have stored a 1. Cells having threshold voltages in bin 1 and bin 2, however, could have stored a -1 or a 1. The uncertainty about the states of the cells in bins 1 and 2 can be reduced by further increasing the number of reads. These probabilities are computed for each cell, and log-likelihood ratios (LLRs) are calculated from these probabilities. Specifically, when a threshold voltage of a cell lies in one of the bins (i.e., when Y is known), a LLR can be computed to determine whether the actual threshold voltage (i.e., X) of the cell is 1 or -1. The binning module 114 generates a bin index for each memory cell based on read operations performed on the memory cells using the reference voltages.) . As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above. Referring to claim 2, Chilappagari teaches The memory device of claim 1, wherein the operations further comprise: causing the target memory cell to be read using the set of read level offsets ([Chilappagari 0101, 0110-0112, 0129] Specifically, for each victim cell, locations of corresponding aggressor cells can be specified in terms of offsets of word line numbers and bit line numbers. For example, in FIG. 7A, if a victim cell is located at word line i and bit line j, aggressor cells may be located at word line i+1 and bit line j-1, word line i and bit line j-1, and/or word line i+1 and bit line j. The parameters or offsets provide a spatial indication of where the aggressor cells are located with respect to a victim cell. Accordingly, an inter-cell interference pattern for a memory device can be specified in terms of offsets of word line numbers and bit line numbers of victim cells and corresponding aggressor cells. The read module 110 utilizes the inter-cell interference pattern to perform read operations and includes the offset information in the data generated from each read operation so that the soft information and aggressor state information can be properly updated. the aggressor cell can be on bit line j+k, where k is any integer. Accordingly, data from each read operation should include the value of k. For example, let the aggressor cell be at word line i+1 and bit line j+1. In this case, when a page in word line i+1 is read, a descriptor is programmed to indicate that data from the read operation includes aggressor state information with k=1. So the value for bit line m in a new read should go into the bin index memory for bit line m-1. Another aggressor cell can be at word line i+2 and bit line j-1. In this case, when a page in word line i+2 is read, the descriptor is programmed to indicate that data from the read operation includes aggressor state information with k=-1. In this case, the value for bit line m in the new read should go into the bin index memory for bit line m+1.) . Referring to claims 4 and 19, taking claim 4 as exemplary, Chilappagari teaches The memory device of claim 1, wherein the operations further comprise: causing a corrective read operation to be performed using the set of read level offsets ([Chilappagari 0055] To correct the effects of inter-cell interference on data stored in memory cells along a word line, the memory cells along the word line can be read repeatedly. Information obtained by repeatedly reading the memory cells along a word line is used to decode the data stored in the memory cells along the word line.) . As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-22-aia AIA Claim (s) 3, 11, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chilappagari (US 20130155776 A1) as applied to claim s 1, 10, and 17 above, and further in view of Barndt (US 20180374550 A1) . Referring to claims 3, 11, and 18, taking claim 3 as exemplary, Chilappagari teaches The memory device of claim 1 (see above) ., Chilappagari does not explicitly teach wherein the plurality of memory cells comprises a plurality of quad-level memory cells (QLCs). Chilappagari does disclose memory cells may store one or more bits per cell and may be called single-level or multi-level memory cells, respectively ([Chilappagari 0059]) . Examiner notes quad level cells (QLC) are versions of multi-level memory cells (MLC). Barndt teaches wherein the plurality of memory cells comprises a plurality of quad-level memory cells (QLCs) ([Barndt 0028] the subject technology is not limited to this configuration and may be implemented in systems configured to store two bits of data per cell in a multi-level cell (MLC) configuration, four bits per cell in a quad-level cell (QLC) configuration, etc. Each of the non-volatile memory devices 130 may be implemented in respective chips or packages) . Chilappagari and Barndt are analogous art because they are from the same field of endeavor in memory devices. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Chilappagari and Barndt before him or her to modify the memory device of Chilappagari to include the multi-level memory of Barndt, thereafter the memory device is connected to multi-level memory. The suggestion and/or motivation for doing so would be obtaining the advantage of allowing the memory device to have more support for alternative memory cell configurations as suggested by Barndt. It is known to combine prior art elements according to known methods to yield predictable results. Therefore, it would have been obvious to combine Chilappagari with Barndt to obtain the invention as specified in the instant application claims. As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above. Allowable Subject Matter Claims 5-9, 12-16, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and double patenting rejections addressed. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRANCISCO A GRULLON whose telephone number is (571)272-8318. The examiner can normally be reached Monday - Friday, 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at (571)272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FRANCISCO A GRULLON/Primary Examiner, Art Unit 2132 Application/Control Number: 18/984,322 Page 2 Art Unit: 2132 Application/Control Number: 18/984,322 Page 3 Art Unit: 2132 Application/Control Number: 18/984,322 Page 4 Art Unit: 2132
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