DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/23/2026 has been entered.
Response to Amendment
The amendment filed on 03/23/2026 has been considered by Examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 9-11, 16, 21, and 23-28 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al (KR 2015-0078587 A) in view of Kim et al (KR 2015-0059005 A), Cao et al (US 12,067,920 B1), and Iwase et al (WO 2018163897 A1).
Claim 1, Kang (Fig. 1-5) discloses a gate driver (6; Fig. 6; Fig. 1) comprising:
a plurality of stages (ST1-STn+1; Fig. 1) including an nth stage (STn; Fig. 1), where n is an integer (Fig. 1; wherein n is greater than 3),
wherein the nth stage (STk; Fig. 3) comprises:
a pull-up transistor (Uc; Fig. 3) configured to control a flow of a current (See Page 5 of translation with respect to pull-up switching element Uc) between an output node (Voutk; Fig. 3) and an input terminal for an nth clock (CLKk; Fig. 3), based on a voltage of a Q node (Q; Fig. 3);
a pull-down transistor (Dc1; Fig. 3) configured to control a flow of a current (See Page 5 of translation with respect to first pull-down switching element Dc1) between the output node (Voutk; Fig. 3) and an input terminal of a first low power source (VSS; Fig. 3), based on a voltage of a QB node (QB1; Fig. 3); and
a QB node controller (Tr5, Tr6, Tr6, and Tr9; Fig. 3) configured to control the voltage of the QB node (QB1; Fig. 3), based on a voltage of a control power source (VDD_o; Fig. 3) and the voltage of the Q node (Q; Fig. 3), and
wherein the voltage of the control power source (VDD_o; Fig. 3 and 2) has an on level (vgh; Fig. 2) in a vertical active period of one frame (Frame; Fig. 2) and has an off level (vgl; Fig. 2) in a vertical blank period of the one frame (Blank; Fig. 2).
Kang does not expressly disclose a first reset transistor configured to connect the QB node to an input terminal of a second low power source, based on a reset signal; and
a second reset transistor configured to connect the output node to the input terminal of the first low power source, based on the reset signal.
Kim (Fig. 1-15) discloses a first reset transistor (W8N; Fig. 10) configured to connect the QB node (QB1; Fig. 10) to an input terminal of a second low power source (Vss1; Fig. 10), based on a reset signal (Vdd_R; Fig. 10); and
a second transistor (W7N; Fig. 10) configured to connect the output node (Vout4; Fig. 10) to the input terminal of the first low power source (Vss2; Fig. 10), based on the reset signal (Vdd_R; Fig. 10).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kang’s gate driver by applying a second low power source, as taught by Kim, so to use a gate driver with a second low power source for providing a gate driver which can improve the reliability of a circuit by supplying a low potential voltage in dual to reduce the stress of the transistors constituting the shift register, and a liquid crystal display using the same (Page 13 of translation).
Kang in view of Kim does not expressly disclose wherein the reset signal is input at an on level for a partial time of the vertical blank period of the one frame, and is input at an off level in the vertical active period and the other time of the vertical blank period of the one frame.
Cao (Fig. 1-6) discloses wherein the reset signal (CLR; Fig. 2 and 6) is input at an on level (Col. 11, Lines 34-49; wherein discloses “In the first time period t1 of the blank stage, the second clock signal CLR is configured to be at high potential”) for a partial time (t1; Fig. 6) of the vertical blank period (Blank Stage; Fig. 6) of the one frame (Fig. 6), and is input at an off level Col. 11, Lines 34-49; wherein discloses “in the second time period, the second clock signal CLR is configured to be at low potential”) in the vertical active period (Fig. 6; from Input stage to Reset stage) and the other time (t2; Fig. 6) of the vertical blank period (Blank Stage; Fig. 6) of the one frame (Fig. 6).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kang in view of Kim’s display device by applying a driving method, as taught by Cao, so to use a display device with a driving method for improving the low leakage current problem of the oxide thin film transistor (TFT) and reducing the retained charges (Col. 6, Lines 61-67).
Kang in view of Kim and Cao does not expressly disclose wherein the voltage of the control power source has an on level in a vertical active period of one frame and has only an off level in a vertical blank period of the one frame.
Iwase (Fig. 1-32) discloses wherein the voltage of the control power source (VDD2; Fig. 15 and 16) has an on level in a vertical active period (See Page 11 of translation; wherein discloses “Specifically, the control signal VDD2 becomes a high level voltage during the effective horizontal scanning period and becomes a low level voltage during the blanking period”) of one frame (Fig. 15) and has only an off level in a vertical blank period (See Page 11 of translation; wherein discloses “Specifically, the control signal VDD2 becomes a high level voltage during the effective horizontal scanning period and becomes a low level voltage during the blanking period”) of the one frame (Fig. 15).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kang in view of Kim and Cao’s display device by applying a voltage control method, as taught by Iwase, so to use a display device with a voltage control method for providing the gate driver 400 that can secure a sufficient charging time with low power consumption is realized (See Page 11 of translation).
Claim 10, Kang (Fig. 1-5) discloses a display apparatus (Fig. 5) comprising:
a display panel (2; Fig. 5) including a plurality of gate lines (GL1-GLn; Fig. 5); and
a gate driver (6; Fig. 5) including a plurality of stages (ST1-STn+1; Fig. 1) connected to the plurality of gate lines (GL1-GLn; Fig. 5),
wherein an nth stage (STn; Fig. 1) of the plurality of stages (ST1-STn+1; Fig. 1) comprises:
a pull-up transistor (Uc; Fig. 3) configured to control a flow of a current (See Page 5 of translation with respect to pull-up switching element Uc) between an output node (Voutk; Fig. 3) and an input terminal for an nth clock (CLKk; Fig. 3), based on a voltage of a Q node (Q; Fig. 3);
a pull-down transistor (Dc1; Fig. 3) configured to control a flow of a current (See Page 5 of translation with respect to first pull-down switching element Dc1) between the output node (Voutk; Fig. 3) and an input terminal of a first low power source (VSS; Fig. 3), based on a voltage of a QB node (QB1; Fig. 3); and
a QB node controller (Tr5, Tr6, Tr6, and Tr9; Fig. 3) configured to control the voltage of the QB node (QB1; Fig. 3), based on a voltage of a control power source (VDD_o; Fig. 3) and the voltage of the Q node (Q; Fig. 3), and
wherein the voltage of the control power source (VDD_o; Fig. 3 and 2) has an on level (vgh; Fig. 2) in a vertical active period of one frame (Frame; Fig. 2) and has an off level (vgl; Fig. 2) in a vertical blank period of the one frame (Blank; Fig. 2), where n is an integer (Fig. 1; wherein n is greater than 3).
Kang does not expressly disclose a first reset transistor configured to connect the QB node to an input terminal of a second low power source, based on a reset signal; and
a second reset transistor configured to connect the output node to the input terminal of the first low power source, based on the reset signal.
Kim (Fig. 1-15) discloses a first reset transistor (W8N; Fig. 10) configured to connect the QB node (QB1; Fig. 10) to an input terminal of a second low power source (Vss1; Fig. 10), based on a reset signal (Vdd_R; Fig. 10); and
a second transistor (W7N; Fig. 10) configured to connect the output node (Vout4; Fig. 10) to the input terminal of the first low power source (Vss2; Fig. 10), based on the reset signal (Vdd_R; Fig. 10).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kang’s gate driver by applying a second low power source, as taught by Kim, so to use a gate driver with a second low power source for providing a gate driver which can improve the reliability of a circuit by supplying a low potential voltage in dual to reduce the stress of the transistors constituting the shift register, and a liquid crystal display using the same (Page 13 of translation).
Kang in view of Kim does not expressly disclose wherein the reset signal is input at an on level for a partial time of the vertical blank period of the one frame, and is input at an off level in the vertical active period and the other time of the vertical blank period of the one frame.
Cao (Fig. 1-6) discloses wherein the reset signal (CLR; Fig. 2 and 6) is input at an on level (Col. 11, Lines 34-49; wherein discloses “In the first time period t1 of the blank stage, the second clock signal CLR is configured to be at high potential”) for a partial time (t1; Fig. 6) of the vertical blank period (Blank Stage; Fig. 6) of the one frame (Fig. 6), and is input at an off level Col. 11, Lines 34-49; wherein discloses “in the second time period, the second clock signal CLR is configured to be at low potential”) in the vertical active period (Fig. 6; from Input stage to Reset stage) and the other time (t2; Fig. 6) of the vertical blank period (Blank Stage; Fig. 6) of the one frame (Fig. 6).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kang in view of Kim’s display device by applying a driving method, as taught by Cao, so to use a display device with a driving method for improving the low leakage current problem of the oxide thin film transistor (TFT) and reducing the retained charges (Col. 6, Lines 61-67).
Kang in view of Kim and Cao does not expressly disclose wherein the voltage of the control power source has an on level in a vertical active period of one frame and has only an off level in a vertical blank period of the one frame.
Iwase (Fig. 1-32) discloses wherein the voltage of the control power source (VDD2; Fig. 15 and 16) has an on level in a vertical active period (See Page 11 of translation; wherein discloses “Specifically, the control signal VDD2 becomes a high level voltage during the effective horizontal scanning period and becomes a low level voltage during the blanking period”) of one frame (Fig. 15) and has only an off level in a vertical blank period (See Page 11 of translation; wherein discloses “Specifically, the control signal VDD2 becomes a high level voltage during the effective horizontal scanning period and becomes a low level voltage during the blanking period”) of the one frame (Fig. 15).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kang in view of Kim and Cao’s display device by applying a voltage control method, as taught by Iwase, so to use a display device with a voltage control method for providing the gate driver 400 that can secure a sufficient charging time with low power consumption is realized (See Page 11 of translation).
Claim 2, Kang (Fig. 1-5) discloses wherein the QB node controller (Tr5, Tr6, Tr6, and Tr9; Fig. 3) comprises:
a fourth transistor (Tr5; Fig. 3) connected to an input terminal of the control power source (VDD_o; Fig. 3) and a first control node (CN1; Fig. 3);
a fifth transistor (Tr7; Fig. 3) configured to connect the first control node (CN1; Fig. 3) to an input terminal of a low power source (VSS; Fig. 3), based on the voltage of the Q node (Q; Fig. 3);
a sixth transistor (Tr6; Fig. 3) configured to apply the voltage of the control power source (VDD_o; Fig. 3) to the QB node (QB1; Fig. 3), based on the voltage of the first control node (CN1; Fig. 3); and
a seventh transistor (Tr9; Fig. 3) configured to connect the QB node (QB1; Fig. 3) to the input terminal of the low power source (VSS; Fig. 3), based on the voltage of the Q node (Q; Fig. 3).
Kim (Fig. 1-15) discloses a fifth transistor (W2N; Fig. 10) configured to connect the first control node (Fig. 10; wherein figure shows electrode of transistor W2N connected to transistors W2A and W2) to an input terminal of a second low power source (Vss1; Fig. 10), based on the voltage of the Q node (Q1; Fig. 10); and
a seventh transistor (W8; Fig. 10) configured to connect the QB node (QB1; Fig. 10) to the input terminal of the second low power source (Vss1; Fig. 10), based on the voltage of the Q node (Q1; Fig. 10).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kang’s gate driver by applying a second low power source, as taught by Kim, so to use a gate driver with a second low power source for providing a gate driver which can improve the reliability of a circuit by supplying a low potential voltage in dual to reduce the stress of the transistors constituting the shift register, and a liquid crystal display using the same (Page 13 of translation).
Claim 3, Kim (Fig. 1-15) discloses wherein a voltage of the first low power source (Vss2; Fig. 10) is greater than (Fig. 10; -V6 is greater than -8V) a voltage of the second low power source (Vss1; Fig. 10).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kang’s gate driver by applying a second low power source, as taught by Kim, so to use a gate driver with a second low power source for providing a gate driver which can improve the reliability of a circuit by supplying a low potential voltage in dual to reduce the stress of the transistors constituting the shift register, and a liquid crystal display using the same (Page 13 of translation).
Claims 4 and 11, Kang (Fig. 1-5) discloses further comprising a Q node controller (Tr1, Tr2, and Tr3; Fig. 3) configured to control the voltage of the Q node (Q; Fig. 3), based on a carry signal (Voutk-2 and Voutk+2; Fig. 3) and the voltage of the QB node (QB1; Fig. 3).
Claim 9, Kim (Fig. 1-15) discloses wherein a voltage of the first low power source (Vss2; Fig. 10) is greater than (Fig. 10; -V6 is greater than -8V) a voltage of the second low power source (Vss1; Fig. 10).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kang’s gate driver by applying a second low power source, as taught by Kim, so to use a gate driver with a second low power source for providing a gate driver which can improve the reliability of a circuit by supplying a low potential voltage in dual to reduce the stress of the transistors constituting the shift register, and a liquid crystal display using the same (Page 13 of translation).
Claims 16 and 21, Kim (Fig. 1-15) discloses wherein the nth stage (STG N; Fig. 7) includes no more than 11 transistors (Fig. 9; wherein figure shows stage N comprised of W1, W3N, W9, W8, W5, W8N, W2, W2R, W7N, W6, and W7 which is equal to the required 11 transistors).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kang’s gate driver by applying a second low power source, as taught by Kim, so to use a gate driver with a second low power source for providing a gate driver which can improve the reliability of a circuit by supplying a low potential voltage in dual to reduce the stress of the transistors constituting the shift register, and a liquid crystal display using the same (Page 13 of translation).
Claims 23 and 26, Kim (Fig. 1-15) discloses wherein a gate terminal of a third transistor (W9; Fig. 9) and a gate terminal of the pull-down transistor (W7; Fig. 9) are commonly connected to the QB node (QB1; Fig. 9), and wherein the first reset transistor (W8N; Fig. 9) is configured to directly apply the voltage of the second low power source (VSS1; Fig. 9) to the commonly connected gate terminals of the third transistor (W9; Fig. 9) and the pull-down transistor (W7; Fig. 9) during a reset period to turn off the third transistor and the pull-down transistor (See Page 6 of translation; wherein discloses “The sixth transistor W8N serves to maintain the QB1 node QB1 at the first low potential voltage corresponding to the voltage of the first high potential voltage terminal Vdd_R”).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kang’s gate driver by applying a second low power source, as taught by Kim, so to use a gate driver with a second low power source for providing a gate driver which can improve the reliability of a circuit by supplying a low potential voltage in dual to reduce the stress of the transistors constituting the shift register, and a liquid crystal display using the same (Page 13 of translation).
Claims 24 and 27, Kim (Fig. 1-15) discloses wherein the control power source (Vdd; Fig. 9) is configured to be maintained at the off level (Fig. 8; wherein figure shows rst signal and clock signal at different time then Vdd_reset; therefore the enabling signals to transistors W2 and W2R prevent control voltage Vdd from being supplied to node QB1) during a reset period (Vdd_reset; Fig. 9) of the QB node (QB1; Fig. 9) to turn off a sixth transistor (W2 or W2R; Fig. 9) of the QB node controller (W2, W2R, W5, and W8; Fig. 9) while the first reset transistor is turned on (W8N; Fig. 9), to prevent the control power source (Vdd; Fig. 9) from interfering with the second low power source (Vss1; Fig. 9) at the QB node (QB1; Fig. 9).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kang’s gate driver by applying a second low power source, as taught by Kim, so to use a gate driver with a second low power source for providing a gate driver which can improve the reliability of a circuit by supplying a low potential voltage in dual to reduce the stress of the transistors constituting the shift register, and a liquid crystal display using the same (Page 13 of translation).
Claims 25 and 28, Cao (Fig. 1-6) discloses wherein the pull-up transistor (M6; Fig. 2) is configured to electrically isolate (Col. 12, Lines 47-63; wherein discloses “In the reset stage” … “the sixth transistor M6 are unconducted”) the output node (Output1; Fig. 2) from the Q node (PU; Fig. 2) during a reset period (CLR; Fig. 2; S40; Fig. 5; reset stage; Fig. 6) of the QB node (PD; Fig. 2), and wherein the second reset transistor (M10; Fig. 2) is configured to maintain the output node (Output1; Fig. 2) at the voltage of the first low power source (VSS; Fig. 2) while the pull-down transistor (M6; Fig. 2) is turned off (Col. 12, Lines 47-63; wherein discloses “In the reset stage” … “the sixth transistor
M6 are unconducted”).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kang in view of Kim’s display device by applying a driving method, as taught by Cao, so to use a display device with a driving method for improving the low leakage current problem of the oxide thin film transistor (TFT) and reducing the retained charges (Col. 6, Lines 61-67).
Claims 5, 6, 13, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al (KR 2015-0078587 A) in view of Kim et al (KR 2015-0059005 A), Cao et al (US 12,067,920 B1), and Iwase et al (WO 2018163897 A1) as applied to claim 4 and 10 above, and further in view of So et al (US 2015/0371598 A1).
Claims 5 and 17, Kim (Fig. 1-15) discloses wherein the Q node controller (W1, W3N, and W9; Fig. 10) comprises: w
a first transistor (W1; Fig. 10) connected to the Q node (Q1; Fig. 10) and an input terminal for a previous carry signal input from a previous stage (Vout#N-3); Fig. 10);
a second transistor (W3N; Fig. 10) configured to connect the Q node (Q1; Fig. 10) to an input terminal of a second low power source (Vss1; Fig. 10), based on a next carry signal input from a next stage (Vout#N+3; Fig. 10); and
a third transistor (W9; Fig. 10) configured to connect the Q node (Q1; Fig. 10) to the input terminal of the second low power source (Vss1; Fig. 10), based on the voltage of the QB node (QB1; Fig. 10).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kang’s gate driver by applying a second low power source, as taught by Kim, so to use a gate driver with a second low power source for providing a gate driver which can improve the reliability of a circuit by supplying a low potential voltage in dual to reduce the stress of the transistors constituting the shift register, and a liquid crystal display using the same (Page 13 of translation).
Kang in view of Kim, Cao, and Iwase does not expressly disclose a first transistor connected to the Q node and an input terminal for a previous carry signal input from an (n-4)th stage; and
a second transistor configured to connect the Q node to an input terminal of a low power source, based on a next carry signal input from an (n+6)th stage.
So (Fig. 14) discloses a first transistor (T1; Fig. 14) connected to the Q node (Q; Fig. 14) and an input terminal for a previous carry signal input from an (n-4)th stage (Carry(N-4); Fig. 14); and
a second transistor (T3N; Fig. 14) configured to connect the Q node (Q; Fig. 14) to an input terminal of a second power source (VSS1; Fig. 14), based on a next carry signal input from an (n+6)th stage (Carry(N+6); Fig. 14).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kang in view of Kim, Cao, and Iwase’s a gate driver by applying specific input connections, as taught by So, so to use a gate driver with specific input connections for providing a display device including a scan driver with improved picture quality (Paragraph [0012]).
Claim 6, Kim (Fig. 1-15) discloses wherein a voltage of the first low power source (Vss2; Fig. 10) is greater than (Fig. 10; -V6 is greater than -8V) a voltage of the second low power source (Vss1; Fig. 10).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kang’s gate driver by applying a second low power source, as taught by Kim, so to use a gate driver with a second low power source for providing a gate driver which can improve the reliability of a circuit by supplying a low potential voltage in dual to reduce the stress of the transistors constituting the shift register, and a liquid crystal display using the same (Page 13 of translation).
Claims 13 and 18, Kang (Fig. 1-5) discloses wherein the QB node controller (Tr5, Tr6, Tr6, and Tr9; Fig. 3) comprises:
a fourth transistor (Tr5; Fig. 3) connected to an input terminal of the control power source (VDD_o; Fig. 3) and a first control node (CN1; Fig. 3);
a fifth transistor (Tr7; Fig. 3) configured to connect the first control node (CN1; Fig. 3) to an input terminal of a low power source (VSS; Fig. 3), based on the voltage of the Q node (Q; Fig. 3);
a sixth transistor (Tr6; Fig. 3) configured to apply the voltage of the control power source (VDD_o; Fig. 3) to the QB node (QB1; Fig. 3), based on the voltage of the first control node (CN1; Fig. 3); and
a seventh transistor (Tr9; Fig. 3) configured to connect the QB node (QB1; Fig. 3) to the input terminal of the low power source (VSS; Fig. 3), based on the voltage of the Q node (Q; Fig. 3).
Kim (Fig. 1-15) discloses a fifth transistor (W2N; Fig. 10) configured to connect the first control node (Fig. 10; wherein figure shows electrode of transistor W2N connected to transistors W2A and W2) to an input terminal of a second low power source (Vss1; Fig. 10), based on the voltage of the Q node (Q1; Fig. 10); and
a seventh transistor (W8; Fig. 10) configured to connect the QB node (QB1; Fig. 10) to the input terminal of the second low power source (Vss1; Fig. 10), based on the voltage of the Q node (Q1; Fig. 10).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kang’s gate driver by applying a second low power source, as taught by Kim, so to use a gate driver with a second low power source for providing a gate driver which can improve the reliability of a circuit by supplying a low potential voltage in dual to reduce the stress of the transistors constituting the shift register, and a liquid crystal display using the same (Page 13 of translation).
Claims 12 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al (KR 2015-0078587 A) in view of Kim et al (KR 2015-0059005 A), Cao et al (US 12,067,920 B1), and Iwase et al (WO 2018163897 A1) as applied to claim 1 and 10 above, and further in view of Jeoung et al (US 2016/0155409 A1).
Claims 12 and 22, Kang in view of Kim, Cao, and Iwase discloses the gate driver of claim 1 and the display apparatus of claim 10.
Kang in view of Kim, Cao, and Iwase does not expressly disclose wherein the control power source is an alternating current voltage.
Jeoung (Fig. 1-12) discloses wherein the control power source is an alternating current voltage (VAC1; Fig. 12; Paragraph [0101]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kang in view of Kim, Cao, and Iwase’s gate driver by applying an alternating current voltage, as taught by Jeoung, so to use a gate driver with an alternating current voltage for providing a display panel and a method of driving the same capable of stably driving a scan driver and increasing lifespan and reliability of transistors constituting the scan driver (Paragraph [0009]).
Claims 14 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al (KR 2015-0078587 A) in view of Kim et al (KR 2015-0059005 A), Cao et al (US 12,067,920 B1), Iwase et al (WO 2018163897 A1), and So et al (US 2015/0371598 A1) as applied to claim 13 and 18 above, and further in view of Jeoung et al (US 2016/0155409 A1).
Claims 14 and 19, Kang in view of Kim, Cao, Iwase, and So discloses the gate driver of claims 13 and the display apparatus of claim 18.
Kang in view of Kim, Cao, Iwase, and So does not expressly disclose wherein the pull-down transistor and the third transistor are turned on during a discharge period of the Q node, and the fifth transistor and the seventh transistor of the QB node controller are turned off.
Jeoung (Fig. 1-12) discloses wherein the pull-down transistor (Tpd1; Fig. 12) and the third transistor (T11; Fig. 12) are turned on (Paragraph [0110]) during a discharge period of the Q node (Q(N1); Fig. 12; Paragraph [0111]), and the fifth transistor (T16; Fig. 12) and the seventh transistor (T13; Fig. 12) of the QB node controller (T13, T14, T15, and T16; Fig. 12) are turned off (Paragraph [0108]; wherein discloses T13 and T16 turned off when low voltage applied to node Q).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kang in view of Kim, Cao, Iwase, and So’s gate driver by applying a driving method, as taught by Jeoung, so to use a gate driver with a driving method for providing a display panel and a method of driving the same capable of stably driving a scan driver and increasing lifespan and reliability of transistors constituting the scan driver (Paragraph [0009]).
Response to Arguments
Applicant's arguments with respect to claims 1-6, 9-14, 16-20, and 21-28 have been considered but are moot in view of the new ground(s) of rejection.
In view of arguments, the references of Kang et al (KR 2015-0078587 A), Kim et al (KR 2015-0059005 A), Cao et al (US 12,067,920 B1), Iwase et al (WO 2018163897 A1), So et al (US 2015/0371598 A1), and Jeoung et al (US 2016/0155409 A1) have been used for new ground rejection.
Claims 1 and 10 are rejected in view of newly discovered reference(s) to Iwase et al (WO 2018163897 A1).
Conclusion
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/Adam J Snyder/Primary Examiner, Art Unit 2623 03/26/2026