DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 06/30/2026 has been considered by Examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 10-12, 16, and 21-28 are rejected under 35 U.S.C. 103 as being unpatentable over Jo (US 2015/0002504 A1) in view of Kim et al (KR 2015-0059005 A), Cao et al (US 12,067,920 B1), and Zhang et al (CN 110010097 A).
Claim 1, Jo (Fig. 1-6) discloses a gate driver (Fig. 2; Paragraph [0008]; wherein discloses a gate driver) comprising:
a plurality of stages (STn-3 through STn+4; Fig. 2) including an nth stage (STn; Fig. 2), where n is an integer (Fig. 2; wherein figure shows nth stage as the fourth stage),
wherein the nth stage (STn; Fig. 2; Fig. 4) comprises:
a pull-up transistor (Us; Fig. 4; Paragraph [0107]; wherein discloses a scan pull-up switching element) configured to control a flow of a current (Paragraph [0107]) between an output node (SOT or SPn; Fig. 4) and an input terminal for an nth clock (CL5 or CLK5; Fig. 4), based on a voltage of a Q node (Q; Fig. 5);
a pull-down transistor (Ds1; Fig. 5; Paragraph [0108]; wherein discloses a frost scan pull-down switching element) configured to control a flow of a current (Paragraph [0108]) between the output node (SOT or SPn; Fig. 4) and an input terminal of a first low power source (VSL2 or VSS2; Fig. 4), based on a voltage of a QB node (QB1; Fig. 4);
a QB node controller (Tr3, Tr4, Tr5, and Tr6; Fig. 4) configured to control the voltage of the QB node (QB1; Fig. 4; Paragraph [0086-0087]), based on a voltage of a control power source (ACL1 or Vac1; Fig. 4; Paragraph [0084]) and the voltage of the Q node (Q; Fig. 4; Paragraph [0085 and 0087]);
wherein the QB node controller (Tr3, Tr4, Tr5, and Tr6; Fig. 4) comprises:
a fourth transistor (Tr3; Fig. 4; Paragraph [0084]) having gate and drain terminals connected to an input terminal of the control power source (ACL1 or Vac1; Fig. 4) and a source terminal connected to a first control node (QB1; Fig. 4);
a fifth transistor (Tr4; Fig. 4; Paragraph 0085]) configured to connect the first control node (CN1; Fig. 4) to an input terminal of the second low power source (VSL1 or VSS1; Fig. 4), based on the voltage of the Q node (Q; Fig. 4);
a sixth transistor (Tr5; Fig. 4; Paragraph [0086]) configured to apply the voltage of the control power source (ACL1 or Vac1; Fig. 4) to the QB node (QB1; Fig. 4), based on the voltage of the first control node (CN1; Fig. 4); and
a seventh transistor (Tr6; Fig. 4; Paragraph [0087]) configured to connect the QB node (QB1; Fig. 4) to the input terminal of the second low power source (VSL1 or VSS1; Fig. 4), based on the voltage of the Q node (Q; Fig. 4),
wherein a voltage of the first low power source (VSS2; Fig. 4) is greater than (Paragraph [0061]; wherein discloses “For example, the charge voltage VDD may be set to 28V, the first discharge voltage VSS1 may be set to -10V, and the second discharge voltage VSS2 may be set to -5V ) a voltage of the second low power source (VSS1; Fig. 4).
Jo does not expressly disclose a first reset transistor configured to connect the QB node to an input terminal of a second low power source, based on a reset signal; and
a second reset transistor configured to connect the output node to the input terminal of the first low power source, based on the reset signal.
Kim (Fig. 1-15) discloses a first reset transistor (W8N; Fig. 10) configured to connect the QB node (QB1; Fig. 10) to an input terminal of a second low power source (Vss1; Fig. 10), based on a reset signal (Vdd_R; Fig. 10); and
a second transistor (W7N; Fig. 10) configured to connect the output node (Vout4; Fig. 10) to the input terminal of the first low power source (Vss2; Fig. 10), based on the reset signal (Vdd_R; Fig. 10).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Jo’s gate driver by applying a second low power source, as taught by Kim, so to use a gate driver with a second low power source for providing a gate driver which can improve the reliability of a circuit by supplying a low potential voltage in dual to reduce the stress of the transistors constituting the shift register, and a liquid crystal display using the same (Page 13 of translation).
Jo in view of Kim does not expressly disclose wherein the reset signal is input at an on level for a partial time of the vertical blank period of the one frame, and is input at an off level in the vertical active period and the other time of the vertical blank period of the one frame.
Cao (Fig. 1-6) discloses wherein the reset signal (CLR; Fig. 2 and 6) is input at an on level (Col. 11, Lines 34-49; wherein discloses “In the first time period t1 of the blank stage, the second clock signal CLR is configured to be at high potential”) for a partial time (t1; Fig. 6) of the vertical blank period (Blank Stage; Fig. 6) of the one frame (Fig. 6), and is input at an off level Col. 11, Lines 34-49; wherein discloses “in the second time period, the second clock signal CLR is configured to be at low potential”) in the vertical active period (Fig. 6; from Input stage to Reset stage) and the other time (t2; Fig. 6) of the vertical blank period (Blank Stage; Fig. 6) of the one frame (Fig. 6).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Jo in view of Kim’s gate driver by applying a driving method, as taught by Cao, so to use a gate driver with a driving method for improving the low leakage current problem of the oxide thin film transistor (TFT) and reducing the retained charges (Col. 6, Lines 61-67).
Jo in view of Kim and Cao does not expressly disclose wherein the voltage of the control power source has an on level in a vertical active period of one frame and has only an off level in a vertical blank period of the one frame, and
wherein the reset signal has a phase opposite to that of the control power source.
Zhang (Fig. 1-9) discloses wherein the voltage of the control power source (GCH; Fig. 4) has an on level in a vertical active period (Display period; Fig. 8; wherein figure shows the first voltage terminal GCH at a high potential) of one frame (1F; Fig. 8) and has only an off level in a vertical blank period (Blank; Fig. 8 wherein figure shows the first voltage terminal GCH at a low potential) of the one frame (1F; Fig. 8), and
wherein the reset signal (GCL; Fig. 4; wherein figure shows signal controlling at least transistor M4 which is connected to output terminal) has a phase opposite (Fig. 8; wherein figure shows signal GCL having a phase opposite to GCH) to that of the control power source (GCH; Fig. 4).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Jo in view of Kim and Cao’s gate driver by applying a driving method, as taught by Zhang, so to use a gate driver with a driving method for providing a shift register and driving method thereof, a gate driving circuit and a display device, which can reduce the appearance probability multi-output shift register (Summary of Invention).
Claim 10, Jo (Fig. 1-6) discloses a display apparatus (Paragraph [0058]; wherein discloses a “display apparatus”) comprising:
a display panel (Paragraph [0058]; wherein discloses a liquid crystal display panel) including a plurality of gate lines (Paragraph [0006]; wherein discloses a plurality of gate lines); and
a gate driver (Paragraph [0008]; wherein discloses a gate driver) including a plurality of stages (STn-3 through STn+4; Fig. 2) connected to the plurality of gate lines (Paragraph [0048]),
wherein an nth stage (STn; Fig. 2) of the plurality of stages (STn-3 through STn+4; Fig. 2) comprises:
a pull-up transistor (Us; Fig. 4; Paragraph [0107]; wherein discloses a scan pull-up switching element) configured to control a flow of a current (Paragraph [0107]) between an output node (SOT or SPn; Fig. 4) and an input terminal for an nth clock (CL5 or CLK5; Fig. 4), based on a voltage of a Q node (Q; Fig. 5);
a pull-down transistor (Ds1; Fig. 5; Paragraph [0108]; wherein discloses a frost scan pull-down switching element) configured to control a flow of a current (Paragraph [0108]) between the output node (SOT or SPn; Fig. 4) and an input terminal of a first low power source (VSL2 or VSS2; Fig. 4), based on a voltage of a QB node (QB1; Fig. 4);
a QB node controller (Tr3, Tr4, Tr5, and Tr6; Fig. 4) configured to control the voltage of the QB node (QB1; Fig. 4; Paragraph [0086-0087]), based on a voltage of a control power source (ACL1 or Vac1; Fig. 4; Paragraph [0084]) and the voltage of the Q node (Q; Fig. 4; Paragraph [0085 and 0087]);
wherein the QB node controller (Tr3, Tr4, Tr5, and Tr6; Fig. 4) comprises:
a fourth transistor (Tr3; Fig. 4; Paragraph [0084]) having gate and drain terminals connected to an input terminal of the control power source (ACL1 or Vac1; Fig. 4) and a source terminal connected to a first control node (QB1; Fig. 4);
a fifth transistor (Tr4; Fig. 4; Paragraph 0085]) configured to connect the first control node (CN1; Fig. 4) to an input terminal of the second low power source (VSL1 or VSS1; Fig. 4), based on the voltage of the Q node (Q; Fig. 4);
a sixth transistor (Tr5; Fig. 4; Paragraph [0086]) configured to apply the voltage of the control power source (ACL1 or Vac1; Fig. 4) to the QB node (QB1; Fig. 4), based on the voltage of the first control node (CN1; Fig. 4); and
a seventh transistor (Tr6; Fig. 4; Paragraph [0087]) configured to connect the QB node (QB1; Fig. 4) to the input terminal of the second low power source (VSL1 or VSS1; Fig. 4), based on the voltage of the Q node (Q; Fig. 4),
where n is an integer (Fig. 2; wherein figure shows nth stage as the fourth stage),
wherein a voltage of the first low power source (VSS2; Fig. 4) is greater than (Paragraph [0061]; wherein discloses “For example, the charge voltage VDD may be set to 28V, the first discharge voltage VSS1 may be set to -10V, and the second discharge voltage VSS2 may be set to -5V ) a voltage of the second low power source (VSS1; Fig. 4).
Jo does not expressly disclose a first reset transistor configured to connect the QB node to an input terminal of a second low power source, based on a reset signal; and
a second reset transistor configured to connect the output node to the input terminal of the first low power source, based on the reset signal.
Kim (Fig. 1-15) discloses a first reset transistor (W8N; Fig. 10) configured to connect the QB node (QB1; Fig. 10) to an input terminal of a second low power source (Vss1; Fig. 10), based on a reset signal (Vdd_R; Fig. 10); and
a second transistor (W7N; Fig. 10) configured to connect the output node (Vout4; Fig. 10) to the input terminal of the first low power source (Vss2; Fig. 10), based on the reset signal (Vdd_R; Fig. 10).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Jo’s gate driver by applying a second low power source, as taught by Kim, so to use a gate driver with a second low power source for providing a gate driver which can improve the reliability of a circuit by supplying a low potential voltage in dual to reduce the stress of the transistors constituting the shift register, and a liquid crystal display using the same (Page 13 of translation).
Jo in view of Kim does not expressly disclose wherein the reset signal is input at an on level for a partial time of the vertical blank period of the one frame, and is input at an off level in the vertical active period and the other time of the vertical blank period of the one frame.
Cao (Fig. 1-6) discloses wherein the reset signal (CLR; Fig. 2 and 6) is input at an on level (Col. 11, Lines 34-49; wherein discloses “In the first time period t1 of the blank stage, the second clock signal CLR is configured to be at high potential”) for a partial time (t1; Fig. 6) of the vertical blank period (Blank Stage; Fig. 6) of the one frame (Fig. 6), and is input at an off level Col. 11, Lines 34-49; wherein discloses “in the second time period, the second clock signal CLR is configured to be at low potential”) in the vertical active period (Fig. 6; from Input stage to Reset stage) and the other time (t2; Fig. 6) of the vertical blank period (Blank Stage; Fig. 6) of the one frame (Fig. 6).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Jo in view of Kim’s gate driver by applying a driving method, as taught by Cao, so to use a gate driver with a driving method for improving the low leakage current problem of the oxide thin film transistor (TFT) and reducing the retained charges (Col. 6, Lines 61-67).
Jo in view of Kim and Cao does not expressly disclose wherein the voltage of the control power source has an on level in a vertical active period of one frame and has only an off level in a vertical blank period of the one frame, and
wherein the reset signal has a phase opposite to that of the control power source.
Zhang (Fig. 1-9) discloses wherein the voltage of the control power source (GCH; Fig. 4) has an on level in a vertical active period (Display period; Fig. 8; wherein figure shows the first voltage terminal GCH at a high potential) of one frame (1F; Fig. 8) and has only an off level in a vertical blank period (Blank; Fig. 8 wherein figure shows the first voltage terminal GCH at a low potential) of the one frame (1F; Fig. 8), and
wherein the reset signal (GCL; Fig. 4; wherein figure shows signal controlling at least transistor M4 which is connected to output terminal) has a phase opposite (Fig. 8; wherein figure shows signal GCL having a phase opposite to GCH) to that of the control power source (GCH; Fig. 4).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Jo in view of Kim and Cao’s gate driver by applying a driving method, as taught by Zhang, so to use a gate driver with a driving method for providing a shift register and driving method thereof, a gate driving circuit and a display device, which can reduce the appearance probability multi-output shift register (Summary of Invention).
Claims 4 and 11, Jo (Fig. 1-6) discloses further comprising a Q node controller (Tr1 and Tr13; Fig. 4) configured to control the voltage (Paragraph [0079] and [0096]) of the Q node (Q; Fig. 4), based on a carry signal (CPn-3; Fig. 4) and the voltage of the QB node (QB1; Fig. 4).
Claims 12 and 22, Jo (Fig. 1-6) discloses wherein the control power source (ACL1; Fig. 4) is an alternating current voltage (Vac1; Fig. 4; Paragraph [0062]).
Claims 16 and 21, Kim (Fig. 1-15) discloses wherein the nth stage (STG N; Fig. 7) includes no more than 11 transistors (Fig. 9; wherein figure shows stage N comprised of W1, W3N, W9, W8, W5, W8N, W2, W2R, W7N, W6, and W7 which is equal to the required 11 transistors).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Jo’s gate driver by applying a second low power source, as taught by Kim, so to use a gate driver with a second low power source for providing a gate driver which can improve the reliability of a circuit by supplying a low potential voltage in dual to reduce the stress of the transistors constituting the shift register, and a liquid crystal display using the same (Page 13 of translation).
Claims 23 and 26, Kim (Fig. 1-15) discloses wherein a gate terminal of a third transistor (W9; Fig. 9) and a gate terminal of the pull-down transistor (W7; Fig. 9) are commonly connected to the QB node (QB1; Fig. 9), and wherein the first reset transistor (W8N; Fig. 9) is configured to directly apply the voltage of the second low power source (VSS1; Fig. 9) to the commonly connected gate terminals of the third transistor (W9; Fig. 9) and the pull-down transistor (W7; Fig. 9) during a reset period to turn off the third transistor and the pull-down transistor (See Page 6 of translation; wherein discloses “The sixth transistor W8N serves to maintain the QB1 node QB1 at the first low potential voltage corresponding to the voltage of the first high potential voltage terminal Vdd_R”).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Jo’s gate driver by applying a second low power source, as taught by Kim, so to use a gate driver with a second low power source for providing a gate driver which can improve the reliability of a circuit by supplying a low potential voltage in dual to reduce the stress of the transistors constituting the shift register, and a liquid crystal display using the same (Page 13 of translation).
Claims 24 and 27, Kim (Fig. 1-15) discloses wherein the control power source (Vdd; Fig. 9) is configured to be maintained at the off level (Fig. 8; wherein figure shows rst signal and clock signal at different time then Vdd_reset; therefore the enabling signals to transistors W2 and W2R prevent control voltage Vdd from being supplied to node QB1) during a reset period (Vdd_reset; Fig. 9) of the QB node (QB1; Fig. 9) to turn off the sixth transistor (W2 or W2R; Fig. 9) of the QB node controller (W2, W2R, W5, and W8; Fig. 9) while the first reset transistor is turned on (W8N; Fig. 9), to prevent the control power source (Vdd; Fig. 9) from interfering with the second low power source (Vss1; Fig. 9) at the QB node (QB1; Fig. 9).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Jo’s gate driver by applying a second low power source, as taught by Kim, so to use a gate driver with a second low power source for providing a gate driver which can improve the reliability of a circuit by supplying a low potential voltage in dual to reduce the stress of the transistors constituting the shift register, and a liquid crystal display using the same (Page 13 of translation).
Claims 25 and 28, Cao (Fig. 1-6) discloses wherein the pull-up transistor (M6; Fig. 2) is configured to electrically isolate (Col. 12, Lines 47-63; wherein discloses “In the reset stage” … “the sixth transistor M6 are unconducted”) the output node (Output1; Fig. 2) from the Q node (PU; Fig. 2) during a reset period (CLR; Fig. 2; S40; Fig. 5; reset stage; Fig. 6) of the QB node (PD; Fig. 2), and wherein the second reset transistor (M10; Fig. 2) is configured to maintain the output node (Output1; Fig. 2) at the voltage of the first low power source (VSS; Fig. 2) while the pull-down transistor (M6; Fig. 2) is turned off (Col. 12, Lines 47-63; wherein discloses “In the reset stage” … “the sixth transistor M6 are unconducted”).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Jo in view of Kim’s gate driver by applying a driving method, as taught by Cao, so to use a gate driver with a driving method for improving the low leakage current problem of the oxide thin film transistor (TFT) and reducing the retained charges (Col. 6, Lines 61-67).
Claims 5 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Jo (US 2015/0002504 A1) in view of Kim et al (KR 2015-0059005 A), Cao et al (US 12,067,920 B1), and Zhang et al (CN 110010097 A) as applied to claim 4 and 11 above, and further in view of So et al (US 2015/0371598 A1).
Claims 5 and 17, Kim (Fig. 1-15) discloses wherein the Q node controller (W1, W3N, and W9; Fig. 10) comprises:
a first transistor (W1; Fig. 10) connected to the Q node (Q1; Fig. 10) and an input terminal for a previous carry signal input from a previous stage (Vout#N-3); Fig. 10);
a second transistor (W3N; Fig. 10) configured to connect the Q node (Q1; Fig. 10) to an input terminal of the second low power source (Vss1; Fig. 10), based on a next carry signal input from a next stage (Vout#N+3; Fig. 10); and
a third transistor (W9; Fig. 10) configured to connect the Q node (Q1; Fig. 10) to the input terminal of the second low power source (Vss1; Fig. 10), based on the voltage of the QB node (QB1; Fig. 10).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Jo’s gate driver by applying a second low power source, as taught by Kim, so to use a gate driver with a second low power source for providing a gate driver which can improve the reliability of a circuit by supplying a low potential voltage in dual to reduce the stress of the transistors constituting the shift register, and a liquid crystal display using the same (Page 13 of translation).
Jo in view of Kim, Cao, and Zhang does not expressly disclose a first transistor connected to the Q node and an input terminal for a previous carry signal input from an (n-4)th stage; and
a second transistor configured to connect the Q node to an input terminal of a low power source, based on a next carry signal input from an (n+6)th stage.
So (Fig. 14) discloses a first transistor (T1; Fig. 14) connected to the Q node (Q; Fig. 14) and an input terminal for a previous carry signal input from an (n-4)th stage (Carry(N-4); Fig. 14); and
a second transistor (T3N; Fig. 14) configured to connect the Q node (Q; Fig. 14) to an input terminal of a second power source (VSS1; Fig. 14), based on a next carry signal input from an (n+6)th stage (Carry(N+6); Fig. 14).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Jo in view of Kim, Cao, and Zhang’s a gate driver by applying specific input connections, as taught by So, so to use a gate driver with specific input connections for providing a display device including a scan driver with improved picture quality (Paragraph [0012]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Jo (US 2015/0002504 A1) in view of Kim et al (KR 2015-0059005 A), Cao et al (US 12,067,920 B1), Zhang et al (CN 110010097 A), and So et al (US 2015/0371598 A1) as applied to claim 17 above, and further in view of Jeoung et al (US 2016/0155409 A1).
Claim 19, Jo in view of Kim, Cao, Zhang, and So discloses the display apparatus of claim 17.
Jo in view of Kim, Cao, Zhang, and So does not expressly disclose wherein the pull-down transistor and the third transistor are turned on during a discharge period of the Q node, and the fifth transistor and the seventh transistor of the QB node controller are turned off.
Jeoung (Fig. 1-12) discloses wherein the pull-down transistor (Tpd1; Fig. 12) and the third transistor (T11; Fig. 12) are turned on (Paragraph [0110]) during a discharge period of the Q node (Q(N1); Fig. 12; Paragraph [0111]), and the fifth transistor (T16; Fig. 12) and the seventh transistor (T13; Fig. 12) of the QB node controller (T13, T14, T15, and T16; Fig. 12) are turned off (Paragraph [0108]; wherein discloses T13 and T16 turned off when low voltage applied to node Q).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Jo in view of Kim, Cao, Zhang, and So’s gate driver by applying a driving method, as taught by Jeoung, so to use a gate driver with a driving method for providing a display panel and a method of driving the same capable of stably driving a scan driver and increasing lifespan and reliability of transistors constituting the scan driver (Paragraph [0009]).
Response to Arguments
Applicant's arguments with respect to claims 1, 4-5, 10-12, 16-17, and 21-28 have been considered but are moot in view of the new ground(s) of rejection.
In view of arguments, the references of Jo (US 2015/0002504 A1), Kim et al (KR 2015-0059005 A), Cao et al (US 12,067,920 B1), Zhang et al (CN 110010097 A), So et al (US 2015/0371598 A1), and Jeoung et al (US 2016/0155409 A1) have been used for new ground rejection.
Claims 1 and 10 are rejected in view of newly discovered reference(s) to Jo (US 2015/0002504 A1) and Zhang et al (CN 110010097 A).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM J SNYDER whose telephone number is (571)270-3460. The examiner can normally be reached Monday-Friday 8am-4:30pm.
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/Adam J Snyder/Primary Examiner, Art Unit 2623 08/25/2026
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