Prosecution Insights
Last updated: July 17, 2026
Application No. 18/984,407

MULTILAYER CERAMIC CAPACITOR, PACKAGE, AND CIRCUIT BOARD

Non-Final OA §102§103
Filed
Dec 17, 2024
Priority
Jul 05, 2022 — JP 2022-108417 +1 more
Examiner
THOMAS, ERIC W
Art Unit
Tech Center
Assignee
Taiyo Yuden Co., Ltd.
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
8m
Est. Remaining
80%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
1042 granted / 1264 resolved
+22.4% vs TC avg
Minimal -2% lift
Without
With
+-2.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
38 currently pending
Career history
1293
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
76.7%
+36.7% vs TC avg
§102
9.4%
-30.6% vs TC avg
§112
4.8%
-35.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1264 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 3-4, 6-7, 10, and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 2014/0311783). PNG media_image1.png 524 596 media_image1.png Greyscale PNG media_image2.png 426 412 media_image2.png Greyscale Regarding claim 1, Lee et al. disclose a multilayer ceramic capacitor that has a dimension in a first direction along a first axis (T) equal to or greater than 1.5 times a dimension in a second direction along a second axis (W) orthogonal to the first axis (T) [0013], and is configured to be mounted on a mounting surface perpendicular to the first axis (T) [0098], the multilayer ceramic capacitor comprising: a ceramic body (100) having a pair of main surfaces (top, bottom) perpendicular to the first axis (T), an end surface (left, right) perpendicular to a third axis (L) orthogonal to the first axis (T) and the second axis (W), and a plurality of internal electrodes (121, 122) that contain Ni as a main component [0042], are stacked in the second direction (W), and are led out to respective connection ends on the end surface (left, right); and an external electrode (131, 132) that contains Cu as a main component [0049] and covers the end surface (left-right), wherein the plurality of internal electrodes (121, 122) include outer-side internal electrodes (left-right – fig. 4, front-back fig. 3) located in both outer sides in the second direction (W) and inner-side internal electrodes (121, 122) located in an inner side in the second direction (W), and wherein respective distances from the pair of main surfaces (top, bottom) at the connection end of each of the outer-side internal electrodes (left-right) are larger than respective distances from the pair of main surfaces in a central portion in a third direction along the third axis (L) of the inner-side internal electrode. Regarding claim 3, Lee et al. disclose the respective distances from the pair of main surfaces of each of the outer-side internal electrodes (see Fig. 4) are larger than those in the central portion (see Fig. 4) in the third direction (L) of each of the inner-side internal electrodes throughout each of the outer-side internal electrodes in the third direction (L). Regarding claim 4, Lee et al. disclose the respective distances from the pair of main surfaces at the connection end of each of the outer-side internal electrodes (121, 122 – left, right) are larger than respective distances from the pair of main surfaces at the connection end of each of the inner-side internal electrodes (121, 122 – see Fig. 3, 4). Regarding claim 6, Lee et al. disclose a circuit board (210) comprising: the multilayer ceramic capacitor according to claim 1; and a mounting substrate (210) having a mounting surface perpendicular to the first axis (T), and a connection electrode (221, 222) provided on the mounting surface and connected to the external electrode (131, 132) of the multilayer ceramic capacitor through solder (230). Regarding claim 7, Lee et al. disclose a multilayer ceramic capacitor (100) that has a dimension in a first direction (T) along a first axis (T) equal to or greater than 1.3 times a dimension in a second direction (W) along a second axis (W) orthogonal to the first axis (T), and is configured to be mounted on a mounting surface (bottom) perpendicular to the first axis (T), the multilayer ceramic capacitor comprising: a ceramic body (110) having a pair of main surfaces (top-bottom) perpendicular to the first axis (T), an end surface (left-right) perpendicular to a third axis (L) orthogonal to the first axis (T) and the second axis (W), and a plurality of internal electrodes (121, 122) that contain Ni as a main component [0042], are stacked in the second direction (W), and are led out to respective connection ends on the end surface (left-right); and an external electrode (131, 132) that contains Cu as a main component [0049] and covers the end surface (left-right), wherein the plurality of internal electrodes (121, 122) include outer-side internal electrodes (left-right – Fig. 3, 4) located in both outer sides in the second direction (W) and inner-side internal electrodes (central – Fig. 3, 4) located in an inner side in the second direction (W), and wherein respective distances from the pair of main surfaces (top-bottom) at the connection end of each of the outer-side internal electrodes (left-right – Fig. 3, 4) are larger than respective distances from the pair of main surfaces in a central portion (center – see Fig. 3) in a third direction (Y) along the third axis (Y) of each of the inner-side internal electrodes (see fig. 3). Regarding claim 9, Lee et al. disclose the respective distances from the pair of main surfaces of each of the outer-side internal electrodes (see Fig. 4) are larger than those in the central portion (see Fig. 4) in the third direction (L) of each of the inner-side internal electrodes throughout each of the outer-side internal electrodes in the third direction (L). Regarding claim 10, Lee et al. disclose the respective distances from the pair of main surfaces at the connection end of each of the outer-side internal electrodes (121, 122) are larger than respective distances from the pair of main surfaces at the connection end of each of the inner-side internal electrodes (121, 122 – see Fig. 3-4). Regarding claim 12, Lee et al. disclose a circuit board comprising: the multilayer ceramic capacitor according to claim 7; and a mounting substrate (210) having a mounting surface perpendicular to the first axis (T), and a connection electrode (211, 222) provided on the mounting surface and connected to the external electrode (131, 132) of the multilayer ceramic capacitor through solder( 230). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 2 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2014/0311783) in view of Lee et al. (US 2013/0141837). Regarding claims 2 and 8, Lee et al. disclose the claimed invention except for each of the internal electrodes has larger distances from the pair of main surfaces at the connection end than in a central portion in the third direction thereof. Lee et al. (‘837) disclose in Fig. 7, a multilayer ceramic capacitor comprising internal electrodes (22), each of the internal electrodes (22) has larger distances from the pair of main surfaces (top-bottom) at the connection end (@WLl) than in a central portion (@WLa) in a third direction (left-right) thereof. It would have been obvious to a person of ordinary skill in the internal electrode art to form the capacitor of Lee et al. so that each of the internal electrodes has larger distances from the pair of main surfaces at the connection end than in a central portion in the third direction thereof, since such a modification would produce a highly-reliable capacitor where internal stress and cracking are prevented. Claim(s) 5 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2014/0311783) in view of Teraoka (US 2016/0227650). Regarding claims 5 and 11, Lee et al. disclose the claimed invention except for a package comprising: the multilayer ceramic capacitor according to claim 1; a carrier tape having a sealing surface perpendicular to the first axis, and a recess that is recessed from the sealing surface in the first direction and accommodates the multilayer ceramic capacitor; and a top tape that is attached to the sealing surface and covers the recess. Teraoka discloses in fig. 9A-9B, a package comprising: a multilayer ceramic capacitor (100) a carrier tape (60) having a sealing surface (@ 61) perpendicular to a first axis, and a recess (60a) that is recessed from the sealing surface (@61) in the first direction (top-bottom) and accommodates the multilayer ceramic capacitor (100); and a top tape (61) that is attached to the sealing surface (@61) and covers the recess. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to form the multilayer ceramic capacitor of Lee et al. in a package, wherein the package includes a carrier tape having a sealing surface perpendicular to the first axis, and a recess that is recessed from the sealing surface in the first direction and accommodates the multilayer ceramic capacitor; and a top tape that is attached to the sealing surface and covers the recess, since such a modification would provide a carrier for multiple capacitors with high-capacitance having excellent reliability. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2016/0005539 A1 -- A multilayer ceramic capacitor having internal electrodes. The capacitor is mounted so that the internal electrodes are perpendicular to a substrate. US 2015/0287533 A1 -- A multilayer ceramic capacitor having internal electrodes. The capacitor is mounted so that the internal electrodes are perpendicular to a substrate Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC THOMAS whose telephone number is (571)272-1985. The examiner can normally be reached Monday-Friday, 6:00 AM-2:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at (571)272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERIC W THOMAS/Primary Examiner, Art Unit 2847 ERIC THOMAS Primary Examiner Art Unit 2847
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Prosecution Timeline

Dec 17, 2024
Application Filed
Jul 08, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
80%
With Interview (-2.1%)
2y 3m (~8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1264 resolved cases by this examiner. Grant probability derived from career allowance rate.

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