DETAILED ACTION
1. This Office Action is responsive to claims filed for No. 18/984,511 on December 2, 2025. Please note Claims 1-15 are pending and have been examined.
America Invents Act
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Restriction Requirement
3. Applicant’s election without traverse of Species 1, Figures 7A-7C and Claims 1-10 in the reply filed on December 2, 2025 is acknowledged. Please note the withdrawal of Claims 11-15.
Information Disclosure Statement
4. The information disclosure statements (IDS) submitted on December 17, 2024 and November 4, 2025 were filed. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Allowable Subject Matter
5. Claims 8-10 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 8 recites aspects of the width of first and second power lines, as well as disposing on opposing sides. This level of detail is not taught by the prior art.
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
8. Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Sang et al.
( US 2015/0379947 A1 ) in view of Oh et al. ( US 2023/0061191 ). Please note the Oh reference was provided in an Information Disclosure Statement.
Sang teaches in Claim 1:
A display panel ( Figure 1, [0053] discloses a display panel 100 ) comprising:
a first pixel and a second pixel arranged in an n-th row and disposed adjacent to each other in a first direction ( Figure 5, [0095] shows a first row L1. For purposes of interpretation, please note W11 and R11, which are connected to S1, as a first pixel. Furthermore, please note G12 and B12, which are connected to S2, as a second pixel. Please note these are arranged in a horizontal/first direction ); and
a first pixel and a second pixel arranged in an (n+1)-st row and disposed adjacent to each other in the first direction, wherein the n-th row and the (n+1)-st row are arranged in a second direction intersecting the first direction, where n is a real number ( Figure 5, [0095] discloses a second row L1. For purposes of interpretation, please note G21 and B21, which are connected to S1, as a first pixel. Furthermore, please note W22 and R22, which are connected to S2, as a second pixel. Note L1 and L2 are arranged in a vertical/second direction ),
wherein each of the first pixel and the second pixel in each of the n-th row and the (n+1)-st row includes first to fourth sub-pixels configured to respectively emit light of different colors ( Figure 5 shows a pixel comprising W11, R11, G21 and B21 and another pixel comprising G12, B12, W22 and R22. Please note these four sub-pixels of different emitted lights spread over L1 and L2 ),
wherein both an n-th gate line and an (n+1)-st gate line are disposed between the first and second pixels of the n-th row and the first and second pixels of the (n+1)-st row ( Figure 5, [0102] discloses G1 and G3 disposed between L1 and L2 and between subpixels of the interpreted first and second pixels ); but
Sang does not explicitly teach “wherein the n-th gate line and the (n+1)-st gate line intersect each other in a pixel border area between the first pixel and the second pixel.”
However, in the same field of endeavor, display panels with pixel layouts, Oh teaches of first pixel blocks 110 and second pixel blocks 120, ( Oh, Figure 1, [0060] ). Notably, please note scan lines N and N+1 and how these intersect in unit area 210, between adjacent pixel blocks 110 and adjacent pixel blocks 120. As combined with Sang, the intersection of lines G1 and G3 can also be done between the interpreted first and second pixel blocks of four subpixels.
Therefore, it would have been obvious to one of ordinary skill in the art, at the effective filed date of the invention, to implement the intersections and in general, the unit layouts, as taught by Oh, with the motivation that crosstalk or smear may be reduced, ( Oh, [0011] ).
Sang and Oh teach in Claim 2:
The display panel of claim 1, wherein the n-th gate line and the (n+1)-st gate line are disposed in different layers. ( Respectfully, gate lines being arranged one different layers is common when the layout of the gate lines is of particular importance. Please note Oh, Figure 7, [0125] which discloses layouts of the unit 210 being connected to different rows and columns. Likewise, Sang teaches in Figures 4-8 of various wiring/layouts. It is well known to have to gate lines arranged/disposed in different layers to help with the wiring, especially when overlapping. Examiner asserts Official Notice to this being well known )
Sang teaches in Claim 3:
The display panel of claim 1, wherein the n-th gate line is electrically connected to each of the first pixel and the second pixel arranged in the n-th row ( Figure 5 shows the gate line G1 connected to W11, R11 (first pixel) and G12/B12 (second pixel) in the L1 row ), and
wherein the (n+1)-st gate line is electrically connected to each of the first pixel and the second pixel arranged in the (n+1)-st row. ( Figure 5 shows the gate line G3 connected to G21 (first pixel) and R22 (second pixel) in the L2 row )
Oh teaches in Claim 4:
The display panel of claim 1, wherein each of the n-th gate line and the (n+1)-st gate line overlaps a second power line in the pixel border area between the first pixels and the second pixels, and wherein the second power line receives a reference voltage applied thereto and extends along the second direction. ( Oh, Figure 14, [0218] discloses a driving voltage line VDD, as well as Vini, which are disposed between the pixels. Please overlap this with Figure 7 which shows units 210 and it is clear the gate line lines overlap these power lines applied in the vertical/second direction )
Sang teaches in Claim 5:
The display panel of claim 1, wherein the first pixel and the second pixel share a white sub-pixel ( Figure 5 shows each of the interpreted first and second pixels each having a white subpixel ),
wherein each of the first sub-pixels includes a first pixel circuit and a first light-emitting area connected to the first pixel circuit ( Figure 5 shows four sub-pixels for each of the interpreted first and second pixels. It is clear these have pixel circuits ),
wherein each of the second sub-pixels includes a second pixel circuit and a second light-emitting area connected to the second pixel circuit, wherein each of the third sub-pixels includes a third pixel circuit and a third light-emitting area connected to the third pixel circuit, and wherein each of the white sub-pixels includes a fourth pixel circuit and a fourth light-emitting area connected to the fourth pixel circuit. ( The same reasoning applied above is applicable to the second, third and white sub-pixels as well. It is clear each of the shown subpixels has a circuit for emitting said color )
Sang teaches in Claim 6:
The display panel of claim 5, wherein the first to third light-emitting areas of the first pixel and the first to third light-emitting areas of the second pixel in each of the n-th row and the (n+1)-st row are arranged in a mirror symmetry manner with each other, and wherein the fourth light-emitting area is arranged between the third light-emitting area of the first pixel and the third light-emitting area of the second pixel in the first direction. ( Figure 5 shows the square layout of the interpreted first and second pixels, having the four subpixels. Please note this symmetry for the first and second pixels. Furthermore, please note the arrangement of the interpreted first to fourth light emitting elements noted in Claim 5 )
Oh teaches in Claim 7:
The display panel of claim 5, wherein the display panel further comprises power lines configured to supply a constant voltage to the pixel circuits, and wherein the power lines extend along the second direction so as to overlap the first light-emitting area, the second light-emitting area, and the third light-emitting area. ( Oh, Figure 14, [0218] discloses a driving voltage line VDD, as well as Vini, which are disposed between the pixels. Please overlap this with Figure 7 which shows units 210 and it is clear the gate line lines overlap these power lines applied in the vertical/second direction )
Conclusion
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DENNIS P JOSEPH whose telephone number is (571)270-1459. The examiner can normally be reached Monday - Friday 5:30 - 3:30 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amr Awad can be reached at 571-272-7764. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DENNIS P JOSEPH/Primary Examiner, Art Unit 2621