DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 6, 14, and 16 have been amended as per Applicant’s amendment filed on February 18, 2026. No claims have been canceled. Claims 1-20 are pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 3, 4, 5 are rejected under 35 U.S.C. 103 as being unpatentable over Ueno (US 2019/0371880 A1, Published December 5, 2019) in view of Wang (US 2022/0199737 A1, Published June 23, 2022).
As to claim 1, Ueno disclose a display apparatus, comprising:
a substrate including an active area in which a plurality of pixels is disposed and a non-active area (Ueno at Fig. 4, DA and NDA; ¶ [0079]);
a plurality of gate drivers each having gate driving transistors distributed throughout the active area and adjacent to the plurality of pixels, the plurality of gate drivers being configured to output a gate signal (Ueno at Fig. 8, gate drivers 56. While Ueno );
a flexible substrate connected to one side of the non-active area (Ueno at Figs. 2, 4, in particular, flexible circuit board 33; ¶ [0102]);
a plurality of first gate link lines which is connected to the flexible substrate and a first gate driver, among the plurality of gate drivers, and extends in a first direction (Ueno at Fig. 8, vertical portions of wiring lines 14L1); and
a plurality of second gate link lines which is disposed in the active area, extends in a second direction which is different from the first direction, is connected to the plurality of first gate link lines, and is connected to a first gate driver and a second gate driver, among the plurality of gate drivers (Ueno at Fig. 8, horizontal portions of wiring lines 14L1).1
Ueno strongly implies but does not explicitly state that its gate drivers have a plurality of transistors (Ueno at Fig. 8, gate drivers 56). Ueno also strongly implies but does not explicitly state that its gate drivers are adjacent to the plurality of pixels (Ueno at Fig. 8).
However, Wang does disclose that the gate drivers have a plurality of transistors (Wang at Fig. 12, in particular; ¶ [0014], in particular, discloses “ In some embodiments, the first gate driving sub-circuit comprises a first group of transistors and a second capacitor, and the second gate driving sub-circuit comprises a second group of transistors”).
Wang also discloses that the its gate drivers are adjacent to the plurality of pixels (Wang at Fig. 2, in particular, gate driving units 211 are adjacent to sub-pixels 12).
Ueno discloses a base display device upon which the claimed invention is an improvement. Wang discloses a comparable display device which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to Ueno the teachings of Wang for the predictable result of providing a wearable display with greater screen to body ratios (Wang at ¶ [0003]).
As to claim 2, Ueno discloses the display apparatus according to claim 1, wherein the active area includes: a plurality of pixel blocks disposed in the second direction (Ueno at Fig. 2, in particular, display units 1u in a horizontal row).
Ueno does not expressly a plurality of gate blocks which includes the plurality of gate drivers divided to be disposed and is disposed to be parallel to the plurality of pixel blocks.
However, Wang does disclose a plurality of gate blocks which includes the plurality of gate drivers divided to be disposed and is disposed to be parallel to the plurality of pixel blocks (Wang at Fig. 2, 3A, in particular, multistage gate driving units 211 and sub-pixels 12).
Ueno discloses a base display device upon which the claimed invention is an improvement. Wang discloses a comparable display device which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to Ueno the teachings of Wang for the predictable result of providing a wearable display with greater screen to body ratios (Wang at ¶ [0003]).
As to claim 3, the combination of Ueno and Wang discloses the display apparatus according to claim 2, wherein the plurality of gate blocks is disposed between the plurality of pixel blocks (Wang at Figs. 2, 3, in particular).
Ueno discloses a base display device upon which the claimed invention is an improvement. Wang discloses a comparable display device which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to Ueno the teachings of Wang for the predictable result of providing a wearable display with greater screen to body ratios (Wang at ¶ [0003]).
As to claim 4, the combination of Ueno and Wang discloses the display apparatus according to claim 2, wherein the active area further includes a line block which is disposed to be parallel to the plurality of pixel blocks and is disposed between the plurality of pixel blocks (Wang at Figs. 2, 3A, 4, in particular. Examiner regards the a column of gate drivers 211 as analogous to a line block).
Ueno discloses a base display device upon which the claimed invention is an improvement. Wang discloses a comparable display device which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to Ueno the teachings of Wang for the predictable result of providing a wearable display with greater screen to body ratios (Wang at ¶ [0003]).
As to claim 5, the combination of Ueno and Wang discloses the display apparatus according to claim 2, wherein the plurality of first gate link lines includes: \
a first gate high signal line (Wang at Fig. 4C, 10C, VGH),
a first gate low signal line (Wang at Fig. 4C, 10C, VGL), and
a first clock line (Wang at Fig. 4C, 10C, CK), and
wherein the plurality of second gate link lines includes:
a second gate high signal line connected to the first gate high signal line (Wang at Fig. 4C, 10C, VGH’),
a second gate low signal line connected to the first gate low signal line (Wang at Fig. 4C, 10C, VGL’), and
a second clock line connected to the first clock line (Wang at Fig. 4C, 10Cm CK’).
Ueno discloses a base display device upon which the claimed invention is an improvement. Wang discloses a comparable display device which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to Ueno the teachings of Wang for the predictable result of providing a wearable display with greater screen to body ratios (Wang at ¶ [0003]).
Claims 9, 11 are rejected under 35 U.S.C. 103 as obvious over Ueno and Wang as applied to claim 1 above, and in further view of Yao (US 2024/0373701 A1, Filed on January 31, 2023).
As to claim 9, the combination of Ueno and Wang discloses the display apparatus according to claim 1.
The combination does not disclose a plurality of constant voltage lines which extends in the second direction in the active area, wherein the plurality of second gate link lines is disposed so as to overlap the plurality of constant voltage lines.
However, Yao does disclose a plurality of constant voltage lines which extends in the second direction in the active area, wherein the plurality of second gate link lines is disposed so as to overlap the plurality of constant voltage lines (Yao at Fig. 5A; ¶ [0189] discloses “As shown in FIG. 5A, the orthographic projection of the second clock signal line CK2 on the base substrate partially overlaps the orthographic projection of the first voltage line VGH on the base substrate”).
The combination of Ueno and Wang discloses a base display device upon which the claimed invention is an improvement. Yao discloses a comparable display device which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to Yao the teachings of the combination of Ueno and Wang for the predictable result of solving the problem that related display products cannot achieve narrow bezels while achieving high resolutions (Yao at ¶ [0004]).
As to claim 11, the combination of Ueno, Wang, and Yao discloses the display apparatus according to claim 9, wherein the plurality of second gate link lines (Wang at Fig. 4C) is disposed below the constant voltage lines (Yao at Fig. 5A; ¶ [0189] discloses “As shown in FIG. 5A, the orthographic projection of the second clock signal line CK2 on the base substrate partially overlaps the orthographic projection of the first voltage line VGH on the base substrate”).
The combination of Ueno and Wang discloses a base display device upon which the claimed invention is an improvement. Yao discloses a comparable display device which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to Yao the teachings of the combination of Ueno and Wang for the predictable result of solving the problem that related display products cannot achieve narrow bezels while achieving high resolutions (Yao at ¶ [0004]).
Claims 14, 15 are rejected under 35 U.S.C. 103 as obvious over Wang (US 2022/0199737 A1, Published June 23, 2022) in view of Yoshida (US 2016/0210923 A1, Published Julye 21, 2016).
As to claim 14, Wang discloses a display apparatus, comprising: a substrate including an active area in which a plurality of pixels is disposed and a non-active area adjacent to the active area (Wang at Fig. 1-4, substrate 11 with sub-pixels 12 and including display area 111 and peripheral area 112; ¶ [0089]);
a plurality of gate blocks disposed in the active area in which a plurality of gate drivers which supplies a gate signal to the plurality of pixels is divided to be disposed (Wang at Figs. 2, 4A, gate driving circuit 21 including cascaded multistage gate driving units 211 (gate driving subcircuits 211A1, 211A2) and gate lines 13 supply gate signal to sub-pixels P1 (See Fig 1B, sub-pixel 12); ¶ [0095]-[0096]),
the plurality of gate drivers each having gate driving transistors distributed throughout the active area and adjacent to the plurality of pixels (Wang at Figs 2, 12; ¶ [0014]);
a plurality of first gate link lines which is connected to some of the plurality of gate blocks and extends in a first direction (Wang at Fig. 4C, CB, CK, VGL, and VGH are analogous to a plurality of gate link lines and extend in a vertical direction, and are connected to some of the plurality of gate blocks, i.e. those connected only to gate driving sub-circuits 211A1; ¶ [0110]).
While Wang does disclose a plurality of second gate link lines connected to the plurality of first gate link lines… and is connected to the plurality of gate blocks (Wang at Fig. 4C, CB’, CK’, VGH’ connected to gate driving sub circuits 211A2; ¶ [0110] discloses “In some embodiments, referring to FIG. 4C, the first gate driving sub-circuit 211A1 further comprises a first clock signal line CK configured to receive a first clock signal, and a second clock signal line CB configured to receive a second clock signal, a first power line VGL configured to receive a first power voltage, and a second power line VGH configured to receive a second power voltage. The second gate driving sub-circuit 211A2 further comprises a third clock signal line CK′ configured to receive the first clock signal, a fourth clock signal line CB′ configured to receive the second clock signal, and a fourth power line VGH′ configured to receive the second power voltage.”), Wang does not expressly disclose that the second gate link lines extend in a second direction which is different from the fist direction.
However, Yoshida does disclose that the second gate link lines are connected to the plurality of first gate link lines and extend in a second direction which is different from the fist direction (Yoshida at Fig. 4B, portion of lines 15L1 extending horizontally and connected to gate driver groups 11B (or 11C)).
Wang discloses a base display device upon which the claimed invention is an improvement. Yoshida discloses a comparable display device which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to Wang the teachings of Yoshida for the predictable result of reducing display irregularities in a display region (Yoshida at ¶ [0004]).
As to claim 15, the combination of Wang and Yoshida discloses the display apparatus according to claim 14, wherein the plurality of first gate link lines includes:
a first gate high signal line (Wang at Fig. 4C, 10C, VGH),
a first gate low signal line (Wang at Fig. 4C, 10C, VGL), and
a first clock line (Wang at Fig. 4C, 10C, CK), and
wherein the plurality of second gate link lines includes:
a second gate high signal line connected to the first gate high signal line (Wang at Fig. 4C, 10C, VGH’),
a second gate low signal line connected to the first gate low signal line (Wang at Fig. 4C, 10C, VGL’), and
a second clock line connected to the first clock line (Wang at Fig. 4C, 10Cm CK’).
Wang discloses a base display device upon which the claimed invention is an improvement. Yoshida discloses a comparable display device which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to Wang the teachings of Yoshida for the predictable result of reducing display irregularities in a display region (Yoshida at ¶ [0004]).
Response to Arguments
Applicant's arguments filed claims 1-5, 9, 13, 16-20 have been fully considered but they are not persuasive.
As discussed in the substantive rejection of claims above, Wang affirmatively discloses the newly added claim aspects.
Allowable Subject Matter
Claims 6-8, 10, 12, 13, 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all limitations of the objected to claim, and all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 6, Wang discloses the gate driving transistors include transistors disposed in the plurality of gate blocks (Wang at Fig. 2; ¶ [0014]). However, none of the prior art found by the Examiner discloses the claimed aspect(s) of: wherein… the plurality of gate blocks includes: a first gate block including a 1-3-th transistor which is connected between the second clock line and a QB node and has a gate electrode connected to the second clock line through a 1-1-th capacitor and a 1-2-th transistor which is connected between the gate electrode of the 1-3-th transistor and the first gate high signal line and has a gate electrode connected to a start signal line; and a second gate block including a 1-1-th transistor which is connected between the start signal line and a Q2 node and has a gate electrode connected to the first clock line, a 1-4-th transistor which is connected between the second gate high signal line and the QB node and has a gate electrode connected to the Q2 node, a 1-7-th transistor which is connected between a gate line from which the gate signal is output and the second gate high signal line and has a gate electrode connected to the QB node, and a 1-2-th capacitor connected between the QB node and the 1-7-th transistor; and a third gate block including a 1-5-th transistor which is connected between the Q2 node and the Q node and has a gate electrode connected to the first gate low signal line, a 1-6-th transistor which is connected between the first gate low signal line and the gate line and has a gate electrode connected to the Q node, and a 1-3-th capacitor which is connected between the gate electrode of the 1-6-th transistor and the gate line.
As to claim 10, none of the prior art found by the Examiner discloses the claimed aspect(s) of: wherein either an on-bias stress voltage or a reset voltage is applied to the plurality of constant voltage lines.
As to claim 12, none of the prior art found by the Examiner discloses the claimed aspect(s) of: further comprising: a plurality of transistors disposed on the substrate; and a lower protection metal layer disposed between the substrate and active layers of the plurality of transistors, wherein the plurality of second gate link lines is disposed on the same layer as the lower protection metal layer.
As to claim 13, none of the prior art found by the Examiner discloses the claimed aspect(s) of: wherein the plurality of second gate link lines include a plurality of 2-1-th gate link lines which connects the first gate driver and a plurality of 2-2-th gate link lines which connects the second gate driver, wherein the plurality of 2-1-th gate link lines include a 2-1-th gate high signal line, a 2-1-th gate low signal line, and a 2-1-th clock line, wherein the plurality of 2-2-th gate link lines include a 2-2-th gate high signal line, a 2-2-th gate low signal line, and a 2-2-th clock line, wherein each gate block corresponds to four pixel lines, and wherein the 2-1-th gate high signal line, the 2-1-th gate low signal line, the 2-1-th clock line, the 2-2-th gate high signal line, the 2-2-th gate low signal line, and the 2-2-th clock line are disposed so as to correspond to different pixel lines.
As to claim 16, Wang discloses the gate driving transistors include transistors disposed in the plurality of gate blocks (Wang at Fig. 2; ¶ [0014]). However, none of the prior art found by the Examiner discloses the claimed aspect(s) of: wherein the plurality of gate blocks includes: a first gate block including a 1-3-th transistor which is connected between the second clock line and a QB node and has a gate electrode connected to the second clock line through a 1-1-th capacitor and a 1-2-th transistor which is connected between the gate electrode of the 1-3-th transistor and the first gate high signal line and has a gate electrode connected to a start signal line; a second gate block including a 1-1-th transistor which is connected between the start signal line and a Q2 node and has a gate electrode connected to the first clock line, a 1-4-th transistor which is connected between the second gate high signal line and the QB node and has a gate electrode connected to the Q2 node, a 1-7-th transistor which is connected between a gate line from which the gate signal is output and the second gate high signal line and has a gate electrode connected to the QB node, and a 1-2-th capacitor connected between the QB node and the 1-7-th transistor; and a third gate block including a 1-5-th transistor which is connected between the Q2 node and a Q node and has a gate electrode connected to the first gate low signal line, a 1-6-th transistor which is connected between the first gate low signal line and the gate line and has a gate electrode connected to the Q node, and a 1-3-th capacitor which is connected between the gate electrode of the 1-6-th transistor and the gate line.
As to claim 17, none of the prior art found by the Examiner discloses the claimed aspect(s) of: wherein the gate block further includes a fourth gate block which is connected to the third gate block, and the fourth gate block includes: a 1-8-th transistor which is connected between the Q2 node and a Q3 node and has a gate electrode connected to the second gate low signal line; a 1-9-th transistor which is connected between the second gate low signal line and the gate line and has a gate electrode connected to the Q3 node; and a 1-4-th capacitor which is connected between the gate electrode of the 1-9-th transistor and the gate line.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Sanjiv D Patel whose telephone number is (571)270-5731. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm.
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/Sanjiv D. Patel/Primary Examiner, Art Unit 2625
03/05/2026
1 See also Yoshida at Fig. 4B.