Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
Papers submitted under 35 U.S.C. 119(a)-(d) have been placed of record in the file.
2. Claims 1-20 are presented for examination.
Double Patenting
3. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. See In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970);and, In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent is shown to be commonly owned with this application. See 37 CFR 1.130(b).
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to
www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
4. Claims 1-20 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-8 of U.S. Patent No. 12211586. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 1-6 of the examined application are anticipated and the same scope of invention by claims 1-8 of the reference such as a device, comprising: a first logic element configured to output a first control signal for controlling a first bit line; a second logic element configured to receive a first clock signal and a second clock signal, an output terminal of the second logic element being coupled to an input terminal of the first logic element; and a first tracking wiring configured to receive the first clock signal to generate the second clock signal.
Claims 7 and 8 are rejected due to the rejection of its parent claim.
Claims 9-14 of the examined application are anticipated and the same scope of invention by claims 1-8 of the reference such as a device, comprising: a first modulation circuit configured to control a first bit line according to a first control signal; a second modulation circuit configured to control a second bit line according to a second control signal; a first logic element configured to generate the first control signal; a second logic element configured to generate the second control signal; and a first tracking wiring, a first terminal of the first tracking wiring being coupled to a first input terminal of the first logic element, and a second terminal of the first tracking wiring being coupled to each of a second input terminal of the first logic element and a first input terminal of the second logic element.
The claim 12 of examined application are obvious over the claim 1 of reference because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites a word line decoder configured to provide word line signals to each of the first word line and the second word line according to a control signal while in the reference claimed the first and second memory arrays. However, the decoder for selecting the word lines is inherent in the memory array. Also see the claim 6, 14 or 17 or the patent 12469531 reference.
Claims 15 and 16 are rejected due to the rejection of its parent claim.
Claims 17-19 of the examined application are anticipated and the same scope of invention by claims 1-8 of the reference such as a device, comprising: a plurality of bit lines configured to operate according to a first control signal and a second control signal; a control signal generator configured to generate the first control signal according to a first clock signal and a second clock signal, and generate the second control signal according to a third clock signal and the second clock signal; a first logic element configured to output the first clock signal; a first tracking wiring configured to receive the first clock signal to generate the second clock signal; a second tracking wiring configured to generate the third clock signal; and a second logic element coupled between an input terminal of the first logic element and the second tracking wiring.
The claim 19 of examined application are obvious over the claim 1 of reference because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites a word line decoder configured to provide word line signals to each of the first word line and the second word line according to a control signal while in the reference claimed the first and second memory arrays. However, the decoder for selecting the word lines is inherent in the memory array. Also see the claim 6, 14 or 17 or the patent 12469531 reference.
Claim 20 is rejected due to the rejection of its parent claim.
5. When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
6. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the date of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOAI V HO whose telephone number is (571) 272-1777. The examiner can normally be reached 7:00 AM -- 5:30 PM from Thursday and Friday of the first week of a bi-week and Tuesday and Wednesday of the second week.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is (571)-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/HOAI V HO/Primary Examiner, Art Unit 2827
