DETAILED ACTION
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claim 20 is/are rejected under 35 U.S.C. 101 as claiming the same invention as that of claim 20 of prior U.S. Patent No. 12216176. This is a statutory double patenting rejection. See the side by side comparison in the chart below the following non-statutory double patenting rejection.
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-2, 4, 6-8 and 10-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, 4-8, 10-11, 15-16 and 18-20 of U.S. Patent No. 12216176. Although the claims at issue are not identical, they are not patentably distinct from each other because the patent claims anticipate or render obvious the application claims. A side by side comparison is presented below for applicant’s convenience.
Application claim
Patent Claim
1. A battery management system comprising:
a first analog front end (AFE) circuit,
the first AFE circuit
comprising: a first pulse-width modulation (PWM) controller, configured to at least one of enable or power on a first sensor,
the first sensor configured to measure a first value of a first group of one or more cells in a battery system, while a first PWM signal from the first PWM controller is in a first state, and configured to at least one of disable or power off the first sensor while the first PWM signal is in a second state; and a first storage register, configured to receive a representation of the first value measured while the first sensor is on and enabled, and configured to store the received first value at least while the first sensor is at least one of disabled or powered off and until another representation of the first value is received.
1. A battery management system comprising: a host microcontroller, operated in accordance with a first clock signal; a first sensor, configured to measure a first value of a first group of one or more cells in a battery system;
a first analog front end (AFE) circuit, wherein the first AFE circuit is operated in accordance with a second clock signal that is unsynchronized with the first clock signal, the first AFE circuit comprising: a first pulse-width modulation (PWM) controller, configured to at least one of enable or power on the first sensor
while a first PWM signal from the first PWM controller is in a first state, and configured to at least one of disable or power off the first sensor while the first PWM signal is in a second state; a first storage register,
configured to receive a representation of the first value measured while the first sensor is on and enabled, and configured to store the received first value
until another representation of the first value is received; and wherein the first AFE circuit transfers a representation of a value in the first storage register to the host microcontroller in response to a request from the host microcontroller.
2. The battery management system of claim 1, wherein the first AFE circuit transfers a representation of a value in the first storage register to a host microcontroller in response to a request from the host microcontroller.
[from claim 1]
wherein the first AFE circuit transfers a representation of a value in the first storage register to the host microcontroller in response to a request from the host microcontroller.
4. The battery management system of claim 2, further comprising:
a second analog front end (AFE) circuit,
the second AFE circuit comprising: a second pulse-width modulation (PWM) controller, configured to at least one of enable or power on a second sensor, the second sensor configured to measure a second value of a second group of one or more cells in the battery system, while a second PWM signal from the second PWM controller is in a first state, and configured to at least one of disable or power off the second sensor while the second PWM signal is in a second state; a second storage register, configured to receive a representation of the second value measured while the second sensor is on and enabled, and configured to store the received second value until another representation of the second value is received; and wherein the second AFE circuit transfers a representation of a value in the second storage register to the host microcontroller in response to a request from the host microcontroller.
2. The battery management system of claim 1, further comprising: a second sensor, configured to measure a second value of a second group of one or more cells in the battery system;
a second analog front end (AFE) circuit, wherein the second AFE circuit is operated in accordance with a third clock signal that is unsynchronized with the first clock signal,
the second AFE circuit comprising: a second pulse-width modulation (PWM) controller, configured to at least one of enable or power on the second sensor
while a second PWM signal from the second PWM controller is in a first state, and configured to at least one of disable or power off the second sensor while the second PWM signal is in a second state; a second storage register, configured to receive a representation of the second value measured while the second sensor is on and enabled, and configured to store the received second value until another representation of the second value is received; and wherein the second AFE circuit transfers a representation of a value in the second storage register to the host microcontroller in response to a request from the host microcontroller.
6. The battery management system of claim 2, further comprising the first sensor and the host microcontroller.
[from claim 1]
a host microcontroller, operated in accordance with a first clock signal; a first sensor,
7. The battery management system of claim 1, wherein the first sensor includes at least one of a temperature sensor, an impedance sensor, a battery state-of-charge sensor, or a pressure sensor.
4. The battery management system of claim 1, wherein the first sensor includes at least one of a temperature sensor, an impedance sensor, a battery state-of-charge sensor, or a pressure sensor.
8. The battery management system of claim 1, wherein the first AFE circuit comprises:
a third pulse-width modulation (PWM) controller, configured to at least one of enable or power on a third sensor, the third sensor configured to measure a third value of the first group of one or more cells, while a third PWM signal from the third PWM controller is in a first state, and configured to at least one of disable or power off the third sensor while the third PWM signal is in a second state; and a third storage register, configured to receive a representation of the third value measured while the third sensor is on and enabled, and configured to store the received third value until another representation of the third value is received.
5. The battery management system of claim 1, further comprising: a third sensor, configured to measure a third value of the first group of one or more cells; and wherein the first AFE circuit further comprises: a third pulse-width modulation (PWM) controller, configured to at least one of enable or power on the third sensor
while a third PWM signal from the third PWM controller is in a first state, and configured to at least one of disable or power off the third sensor while the third PWM signal is in a second state; a third storage register, configured to receive a representation of the third value measured while the third sensor is on and enabled, and configured to store the received third value until another representation of the third value is received; and wherein the first AFE circuit transfers a representation of a value in the third storage register to the host microcontroller in response to a request from the host microcontroller.
10. The battery management system of claim 8, wherein the third sensor includes a different type of sensor than the first sensor.
6. The battery management system of claim 5, wherein the third sensor includes a different type of sensor than the first sensor.
11. The battery management system of claim 8, wherein the third PWM controller and the first PWM controller comprise the same PWM controller.
7. The battery management system of claim 5, wherein the third PWM controller and the first PWM controller comprise the same PWM controller.
12. The battery management system of claim 1, wherein the first PWM controller has configurable settings for a frequency and a duty cycle of the first PWM controller.
8. The battery management system of claim 1, wherein the first PWM controller has configurable settings for a frequency and a duty cycle of the first PWM controller.
13. The battery management system of claim 1, wherein the first storage register is controlled by a first storage register controller, wherein the first storage register controller is configured to allow a representation of the first value measured while the first sensor is powered on and enabled to be stored in the first storage register, and is configured to prevent a representation of the first value measured while the first sensor is not powered on and enabled from being stored in the first storage register.
10. The battery management system of claim 9, wherein the first storage register is controlled by a first storage register controller, wherein the first storage register controller is configured to allow a representation of the first value measured while the first sensor is powered on and enabled to be stored in the first storage register, and is configured to prevent a representation of the first value measured while the first sensor is not powered on and enabled from being stored in the first storage register.
14. The battery management system of claim 13, wherein the first storage register controller has a configurable setting for a delay time, wherein the delay time corresponds to a period of time between a time that the first sensor is powered on and enabled and a time that a representation of the first value is allowed to be stored in the first storage register.
11. The battery management system of claim 10, wherein the first storage register controller has a configurable setting for a delay time, wherein the delay time corresponds to a period of time between a time that the first sensor is powered on and enabled and a time that a representation of the first value is allowed to be stored in the first storage register.
15. A method of operating a battery management system, the method comprising: at least one of powering on or enabling a first sensor coupled to an analog front end (AFE) circuit; receiving, from the first sensor, a first value corresponding to a first group of one or more cells in a battery system, wherein the first value is measured while the first sensor is powered on and enabled; storing, at the AFE circuit, a representation of the first value; and then at least one of powering off or disabling the first sensor.
15. A method of operating a battery management system, the method comprising: at least one of powering on or enabling a first sensor coupled to an analog front end (AFE) circuit; receiving, from the first sensor, a first value corresponding to a first group of one or more cells in a battery system, wherein the first value is measured while the first sensor is powered on and enabled; storing, at the AFE circuit, a representation of the first value; at least one of powering off or disabling the first sensor; transferring, from the AFE circuit to a host microcontroller, a representation of the stored first value.
16. The method of claim 15, further comprising controlling the first sensor using a pulse-width modulation (PWM) signal generated within the AFE circuit, including at least one of enabling or powering on the first sensor while the PWM signal is in a first state, and at least one of disabling or powering off the first sensor while the PWM signal is in a second state.
16. The method of claim 15, further comprising controlling the first sensor using a pulse-width modulation (PWM) signal generated within the AFE circuit, including at least one of enabling or powering on the first sensor while the PWM signal is in a first state, and at least one of disabling or powering off the first sensor while the PWM signal is in a second state.
17. The method of claim 15, wherein the receiving the first value from the first sensor includes receiving the first value wherein the first value is measured following a delay time after the first sensor is powered on and enabled.
18. The method of claim 15, wherein the receiving the first value from the first sensor includes receiving the first value wherein the first value is measured following a delay time after the first sensor is powered on and enabled.
18. The method of claim 15, wherein the transferring a representation of the stored first value occurs over a DC-isolated bus.
19. The method of claim 15, wherein the transferring a representation of the stored first value occurs over a DC-isolated bus.
19. An interface circuit for use in a battery management system, the interface circuit comprising:
a first analog front end (AFE) circuit comprising: a first pulse-width modulation (PWM) controller, configured to at least one of enable or power on a first sensor,
configured to measure a first value of a first group of one or more cells in a battery system, while a first PWM signal from the first PWM controller is in a first state, and configured to at least one of disable or power off the first sensor while the first PWM signal is in a second state; and a first storage register, configured to receive a representation of the first value measured while the first sensor is on and enabled, and configured to store the received first value until another representation of the first value is received.
20. An interface circuit for use in a battery management system, the interface circuit comprising: a first sensor, configured to measure a first value of a first group of one or more cells in a battery system; and
a first analog front end (AFE) circuit comprising: a first pulse-width modulation (PWM) controller, configured to at least one of enable or power on the first sensor
while a first PWM signal from the first PWM controller is in a first state, and configured to at least one of disable or power off the first sensor while the first PWM signal is in a second state; a first storage register, configured to receive a representation of the first value measured
while the first sensor is on and enabled, and configured to store the received first value until another representation of the first value is received; and wherein the first AFE circuit transfers a representation of a value in the first storage register to a host microcontroller, wherein the transfer occurs over a DC-isolated bus.
20. The interface circuit of claim 19, wherein the first AFE circuit transfers a representation of a value in the first storage register to a host microcontroller, wherein the transfer occurs over a DC-isolated bus.
[from claim 20] wherein the first AFE circuit transfers a representation of a value in the first storage register to a host microcontroller, wherein the transfer occurs over a DC-isolated bus.
Claims 3 and 5 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2 of U.S. Patent No. 12216176 in view of Li (U.S. Patent No. 8227944) or Matsura (U.S. Patent No. 8574735). U.S. Patent No. 12216176 recite the salient features of the claimed invention except for the first AFE circuit operates at a different reference voltage level than the host microcontroller. Li teaches in col. 10, lines 1-9 and 54-62 while Matsura teaches in col. 2, lines 32-56 and col. 3, lines 25-32 that it was known to operate the AFE and the host microcontroller at a different reference voltage levels. It would have been obvious to one of ordinary skill in the art at the time the invention was filed to utilize the features of Li or Matsura for the purpose of versatility in battery use and monitoring.
Allowable Subject Matter
Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER E MAHONEY whose telephone number is (571)272-2122. The examiner can normally be reached 9-5:30.
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/CHRISTOPHER E MAHONEY/Primary Examiner, Art Unit 2852
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