DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Other References: Kim (US 20220246201) - receiving a refresh command, performing a refresh operation on a target row of a bank memory array, and providing status information to a memory controller.
Bains (US 20170169880) – Self refresh mode.
Response to Arguments
Applicant's arguments filed 4/17/2026 have been fully considered but they are not persuasive.
For claims 1, and 19, Applicant argues that that the cited references do not disclose the amended limitations. The Office disagrees.
In the present OA, the updated combination of references render the amended limitations as obvious.
Specifically, Marino in view of Kim does not disclose, but Saifuddin discloses
based at least in part on the mode register being set to the first value for at least a threshold time (eg., 0052 - A time duration referred to as “tXSR” represents a number of clock cycles needed for exiting the self-refresh state, and the time duration “tXSR_abort” refers to a number of clock cycles needed for aborting an ongoing operation and exiting the self-refresh state; 0062 - A threshold number can be programmed into the registers such that if DRAM controller 280 receives a number of requests (e.g., from processor 270 for access to DRAM system 260) within a window of time which is less than the threshold, then the traffic may be determined to be light, causing DRAM controller 280 to direct DRAM system 260 to remain in the self-refresh state to service selected bank active commands).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the self-refresh of a memory system as disclosed by Marino, with Kim, with Saifuddin, providing the benefit of external command sequence can be executed between two consecutive internal refresh operations (see Saifuddin, 0053) designed to determine that a DRAM bank of the DRAM system is in a self-refresh state and allow one or more commands to access the DRAM … based on clock frequency (0010).
For Claims 11 and 22, Applicant’s arguments are not persuasive.
Applicant argues that the cited references do not disclose the limitations related to poll a mode register of the memory system, wherein a value of the mode register indicates a status of the self-refresh operation at the memory system. The Office disagrees.
The Office submits that the combination of Marino, Boenapalli and Kim render this limitation as obvious.
Specifically, Kim discloses:
0021 - memory device 104 may make the determination of whether the self-refresh operation is currently being performed in response to receiving the command to exit the self-refresh mode.
0029 - The memory device 104 can transmit the signal using, for example, an output data bus (e.g., one or more output DQ pins, a data mask inversion (DMI) pin, or a dedicated pin… including host device 102.
0035 - registers 212 as one or more registers that can be used to store information that can be used by the control circuitry 210.
0039 - control circuitry 210 provides determining an operational status (or a self-refresh operational status) of the memory device 202 and providing the operational status to one or more other devices,.. DQ pins, DMI pin, dedicated pin.. in response to SRX command… in response to the memory device 202 detecting a change in an operating mode (e.g., a beginning or ending of an operating mode, such as a self-refresh mode), a register setting, or an environmental condition.
0049 - Upon receiving the SR EXIT CMD 404, the memory device 104 can determine a self-refresh operational status (e.g., whether the memory device 104 is performing an ABR or a PBR operation).
0043 - the memory device 104 then receives a command 304 to exit the self-refresh mode (SR EXIT CMD 304), which can correspond to the SRX command. Upon receiving the SR EXIT CMD 304, the memory device 104 can determine an operational status (e.g., whether the memory device 104 is currently performing or undergoing an ABR or a PBR operation). FIG. 3, the memory device 104 determines that the ABR/PBR operation is being performed. In response to the determination, the memory device 104 can transmit a self-refresh operational status signal (SRO status signal) 306 to the host device 102 (e.g., the self-refresh-operation-in-progress signal described with reference to FIG. 1). The SRO status signal 306 indicates that the memory device is performing the ABR/PBR operation and cannot process data read/write requests, even though the host device has transmitted the self-refresh exit command.
0050 - FIG. 4, the memory device 104 determines that the ABR/PBR operation is not being performed. In response to the determination, the memory device 104 can transmit a self-refresh operational status signal (SRO status signal) 406 to the host device 102 (e.g., the no-self-refresh-operation signal described with reference to FIG. 1). the SRO status signal 406 may be realized using a signal with multiple voltages, such as a low or a high voltage level that toggles when the memory device 104 determines whether the ABR/PBR operation is being performed (e.g., low for a no-self-refresh-operation signal and high for self-refresh-operation-in-progress signal, or vice versa). Additionally or alternatively, when the memory device 104 determines no ABR/PBR operation is being performed, the memory device 104 may wait or consume another time duration (not shown) before transmitting the SRO status signal 406 to account for internal operations and other latencies, as described with reference to FIG. 3.
0055 - determine and indicate the self-refresh status, the SRO status signal 506-1 is asserted (e.g., the voltage level is driven high on the one or more pins or other electronic communication mechanism) to indicate that the memory device 104 is performing the self-refresh operation 502-1.
0063 - the memory device 104 or 202 transmits the no-self-refresh-operation signal, as described with reference to FIG. 1, to the host device 102 or the processors 206 of FIG. 1 and FIG. 2.
In combination with Kim, Boenapalli discloses
0035 - The host controller 112 is configured to initiate a host write monitoring mode.
0039 - the host device 102 determines a command queue status 146 to detect the idle condition based on one or more operative command queues being empty, and may send the command 148 during the idle condition to prevent the selective refresh operation 180 from interfering .
0045 - which the host controller 112 can use to check the status and determine whether all possible dies 166 in the flash memory device 104 are effectively utilized or not.
0049 - A register, referred to herein as “bWriteMonitoring” (e.g., an 8-bit register), can be set to the value 00h (where “h” indicates hexadecimal) to indicate that write monitoring mode is disabled, 01h to indicate flash device mode, or 02h to indicate host mode. A default mode can be set to 01h (device mode) or to the last operating mode when enabled. In some implementations, the host mode can be enabled when the command queue is empty, and the device mode can be enabled when the flash memory device 104 decides to address its own wear-leveling activities.
The combination of Boenapalli with Kim would have provided the benefit of The host controller 112 is thus configured to evaluate, at the operation 620, whether the trigger condition 132 is satisfied (Boenapalli, 0087) to prevent the selective refresh operation 180 from interfering with execution of pending commands (e.g., read or write commands) (0039), in combination with Kim’s advantage of the benefits of interactive memory self-refresh control (0014) interactive memory self-refresh control can be implemented with a host device or a memory device (0042, 0047).
Applicant’s arguments for dependent claims 2-10, 12-18, 20, 21, 23, 24 are based on their respective base independent claims, which are addressed above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 9, 10, 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over Marino (US 11561739 B1) and in view of Kim (US 20220139448 A1) and further in view of Saifuddin (US 20170316818)
Claim 1. Marino discloses A memory system (eg., col 4:20-25 Fig. 2 - hybrid memory unit 202 ), comprising:
one or more memory devices (eg., col 4:20-27 Fig. 2 - volatile memory 212 to the non-volatile memory 208); and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to: (eg., col 4:30-35 Fig. 2 - controller 204 can operate the hybrid memory unit 202)
initiate a self-refresh operation for a memory die of the memory system (eg., col 9:54-57 - The hybrid memory unit 302 can put the volatile memory 304 into the self-refresh mode by issuing a self-refresh entry command 348. );
set a mode register to a first value based at least in part on initiating the self-refresh operation, wherein the first value of the mode register indicates that the self-refresh operation is being executed (eg., col 9:15-20 Fig 3 - the health register 342 can include a self-refresh mode value 344, such as a DRAM_NOT_SELF_REFRESH bit. The self-refresh mode value 344 can indicate if the SDRAM of the hybrid memory unit 302 is operating in a self-refresh mode.); and
Marino does not disclose, but Kim discloses
determine whether to reset the mode register to a second value based at least in part on a status of the self-refresh operation, wherein the second value of the mode register indicates that the self-refresh operation is complete (eg., 0015 - in response to a self-refresh exit (SRX) command, the memory device can output a signal to the memory controller that indicates whether the memory device is currently performing an internal self-refresh operation (also referred to as a self-refresh operation… signal indicates the self-refresh operation is complete)).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the self-refresh of a memory system as disclosed by Marino, with Kim, providing the benefit of improve system performance, including data rate and latency, by reducing the amount of time that read and write requests are paused while self-refresh operations are performed as a memory device exits a self-refresh mode. Sharing the status of the self-refresh operation may also improve queue management for the memory controller while maintaining memory reliability through accurate refresh operations (see Kim, 0015).
Marino in view of Kim does not disclose, but Saifuddin discloses
based at least in part on the mode register being set to the first value for at least a threshold time (eg., 0052 - A time duration referred to as “tXSR” represents a number of clock cycles needed for exiting the self-refresh state, and the time duration “tXSR_abort” refers to a number of clock cycles needed for aborting an ongoing operation and exiting the self-refresh state; 0062 - A threshold number can be programmed into the registers such that if DRAM controller 280 receives a number of requests (e.g., from processor 270 for access to DRAM system 260) within a window of time which is less than the threshold, then the traffic may be determined to be light, causing DRAM controller 280 to direct DRAM system 260 to remain in the self-refresh state to service selected bank active commands).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the self-refresh of a memory system as disclosed by Marino, with Kim, with Saifuddin, providing the benefit of external command sequence can be executed between two consecutive internal refresh operations (see Saifuddin, 0053) designed to determine that a DRAM bank of the DRAM system is in a self-refresh state and allow one or more commands to access the DRAM … based on clock frequency (0010).
Claim 2. Marino does not disclose, but Kim discloses
wherein the processing circuitry is further configured to cause the memory system to: complete the self-refresh operation for the memory die; and reset the mode register to the second value based at least in part on completing the self-refresh operation, wherein determining whether to reset the mode register to the second value comprises determining to reset the mode register to the second value based at least in part on completing the self-refresh operation (eg., 0015 - in response to a self-refresh exit (SRX) command, the memory device can output a signal to the memory controller that indicates whether the memory device is currently performing an internal self-refresh operation (also referred to as a self-refresh operation… signal indicates the self-refresh operation is complete)).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the self-refresh of a memory system as disclosed by Marino, with Kim, providing the benefit of improve system performance, including data rate and latency, by reducing the amount of time that read and write requests are paused while self-refresh operations are performed as a memory device exits a self-refresh mode. Sharing the status of the self-refresh operation may also improve queue management for the memory controller while maintaining memory reliability through accurate refresh operations (see Kim, 0015).
Claim 3. Marino does not disclose, but Kim discloses
wherein the processing circuitry is further configured to cause the memory system to: receive a self-refresh exit command; exit the self-refresh operation prior to completion based at least in part on the self-refresh exit command; and reset the mode register to the second value based at least in part on exiting the self-refresh operation, wherein determining whether to reset the mode register to the second value comprises determining to reset the mode register to the second value based at least in part on exiting the self-refresh operation (eg., 0015 - in response to a self-refresh exit (SRX) command, the memory device can output a signal to the memory controller that indicates whether the memory device is currently performing an internal self-refresh operation (also referred to as a self-refresh operation… signal indicates the self-refresh operation is complete)).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the self-refresh of a memory system as disclosed by Marino, with Kim, providing the benefit of improve system performance, including data rate and latency, by reducing the amount of time that read and write requests are paused while self-refresh operations are performed as a memory device exits a self-refresh mode. Sharing the status of the self-refresh operation may also improve queue management for the memory controller while maintaining memory reliability through accurate refresh operations (see Kim, 0015).
Claim 4. Marino does not disclose, but Kim discloses
wherein receiving the self-refresh exit command is based at least in part on the mode register being set to the first value for at least a threshold time (eg., 0012 - memory controller issues a command to end a self-refresh operation or exit a self-refresh mode (e.g., a self-refresh exit command), the memory controller may be “required” to wait for another interval after issuing the command to allow the memory device to complete any in-process self-refresh operations).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the self-refresh of a memory system as disclosed by Marino, with Kim, providing the benefit of improve system performance, including data rate and latency, by reducing the amount of time that read and write requests are paused while self-refresh operations are performed as a memory device exits a self-refresh mode. Sharing the status of the self-refresh operation may also improve queue management for the memory controller while maintaining memory reliability through accurate refresh operations (see Kim, 0015).
Claim 5. Marino does not disclose, but Kim discloses
wherein the processing circuitry is further configured to cause the memory system to: reset the mode register to the second value based at least in part on exiting the self-refresh operation or completing the self-refresh operation; and receive one or more access commands based at least in part on resetting the mode register to the second value, the one or more access commands comprising a read command, a write command, or both (eg., 0015 - If a self-refresh operation is being performed, the memory controller can wait until the signal indicates the self-refresh operation is complete and then begin sending data read and write requests. The memory device can output the signal to the host device using, for example, an output data bus).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the self-refresh of a memory system as disclosed by Marino, with Kim, providing the benefit of improve system performance, including data rate and latency, by reducing the amount of time that read and write requests are paused while self-refresh operations are performed as a memory device exits a self-refresh mode. Sharing the status of the self-refresh operation may also improve queue management for the memory controller while maintaining memory reliability through accurate refresh operations (see Kim, 0015).
Claim 9. Marino does not disclose, but Kim discloses
wherein the processing circuitry is further configured to cause the memory system to: complete the self-refresh operation for the memory die; and transmit, via a pin, a signal that indicates the self-refresh operation is complete (eg., 0015 - in response to a self-refresh exit (SRX) command, the memory device can output a signal to the memory controller that indicates whether the memory device is currently performing an internal self-refresh operation (also referred to as a self-refresh operation… signal indicates the self-refresh operation is complete)).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the self-refresh of a memory system as disclosed by Marino, with Kim, providing the benefit of improve system performance, including data rate and latency, by reducing the amount of time that read and write requests are paused while self-refresh operations are performed as a memory device exits a self-refresh mode. Sharing the status of the self-refresh operation may also improve queue management for the memory controller while maintaining memory reliability through accurate refresh operations (see Kim, 0015).
Claim 10. Marino does not disclose, but Kim discloses
wherein the processing circuitry is further configured to cause the memory system to: set the mode register to the second value based at least in part on completing the self-refresh operation, wherein transmitting the signal is based at least in part on the second value of the mode register (eg., 0015 - in response to a self-refresh exit (SRX) command, the memory device can output a signal to the memory controller that indicates whether the memory device is currently performing an internal self-refresh operation (also referred to as a self-refresh operation… signal indicates the self-refresh operation is complete)).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the self-refresh of a memory system as disclosed by Marino, with Kim, providing the benefit of improve system performance, including data rate and latency, by reducing the amount of time that read and write requests are paused while self-refresh operations are performed as a memory device exits a self-refresh mode. Sharing the status of the self-refresh operation may also improve queue management for the memory controller while maintaining memory reliability through accurate refresh operations (see Kim, 0015).
Claim 19. Marino discloses A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to (eg., col 4:20-25 Fig. 2 - hybrid memory unit 202 ; col 4:30-35 Fig. 2 - controller 204 can operate the hybrid memory unit 202)
initiate a self-refresh operation for a memory die of the memory system (eg., col 9:54-57 - The hybrid memory unit 302 can put the volatile memory 304 into the self-refresh mode by issuing a self-refresh entry command 348. );
set a mode register to a first value based at least in part on initiating the self-refresh operation, wherein the first value of the mode register indicates that the self-refresh operation is being executed (eg., col 9:15-20 Fig 3 - the health register 342 can include a self-refresh mode value 344, such as a DRAM_NOT_SELF_REFRESH bit. The self-refresh mode value 344 can indicate if the SDRAM of the hybrid memory unit 302 is operating in a self-refresh mode.); and
Marino does not disclose, but Kim discloses
determine whether to reset the mode register to a second value based at least in part on a status of the self-refresh operation, wherein the second value of the mode register indicates that the self-refresh operation is complete (eg., 0015 - in response to a self-refresh exit (SRX) command, the memory device can output a signal to the memory controller that indicates whether the memory device is currently performing an internal self-refresh operation (also referred to as a self-refresh operation… signal indicates the self-refresh operation is complete)).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the self-refresh of a memory system as disclosed by Marino, with Kim, providing the benefit of improve system performance, including data rate and latency, by reducing the amount of time that read and write requests are paused while self-refresh operations are performed as a memory device exits a self-refresh mode. Sharing the status of the self-refresh operation may also improve queue management for the memory controller while maintaining memory reliability through accurate refresh operations (see Kim, 0015).
Marino in view of Kim does not disclose, but Saifuddin discloses
based at least in part on the mode register being set to the first value for at least a threshold time (eg., 0052 - A time duration referred to as “tXSR” represents a number of clock cycles needed for exiting the self-refresh state, and the time duration “tXSR_abort” refers to a number of clock cycles needed for aborting an ongoing operation and exiting the self-refresh state; 0062 - A threshold number can be programmed into the registers such that if DRAM controller 280 receives a number of requests (e.g., from processor 270 for access to DRAM system 260) within a window of time which is less than the threshold, then the traffic may be determined to be light, causing DRAM controller 280 to direct DRAM system 260 to remain in the self-refresh state to service selected bank active commands).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the self-refresh of a memory system as disclosed by Marino, with Kim, with Saifuddin, providing the benefit of external command sequence can be executed between two consecutive internal refresh operations (see Saifuddin, 0053) designed to determine that a DRAM bank of the DRAM system is in a self-refresh state and allow one or more commands to access the DRAM … based on clock frequency (0010).
Claim 20 is rejected for reasons similar to Claim 2 above.
Claim 21 is rejected for reasons similar to Claim 3 above.
Claims 11-18, 22-24 are rejected under 35 U.S.C. 103 as being unpatentable over Marino (US 11561739 B1) and in view of Boenapalli (US 20250103232 A1) and further in view of Kim (US 20220139448 A1)
Claim 11. Marino discloses A host system (eg., col 5:40-45 Fig. 2 - host system 230), comprising:
one or more interfaces comprising one or more signal paths operable for communications with one or more memory systems (eg., col 5:45-46 Fig. 2 - memory bus connector 234 is an electromechanical element for attaching the memory to the host system 230); and
processing circuitry coupled with the one or more interfaces and configured to cause the host system to: (eg., col 5:35-39 Fig. 2 - The host system 230 can include a host processor 238. )
Marino does not disclose, but Boenapalli discloses
transmit, from the host system, a self-refresh initiation command, wherein the self-refresh initiation command is for triggering a self-refresh operation for at least a memory die of a memory system (eg., 0047 - enabling the selective refresh mechanism as initiated by the host device 102.);
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the host system as disclosed by Manino with Boenapalli, providing the benefit of improvement in write throughput to a flash memory device (eg., Boenapalli, 0021).
Marino in view of Boenapalli does not disclose, but Kim discloses
poll a mode register of the memory system, wherein a value of the mode register indicates a status of the self-refresh operation at the memory system (eg., 0015 - in response to a self-refresh exit (SRX) command, the memory device can output a signal to the memory controller that indicates whether the memory device is currently performing an internal self-refresh operation (also referred to as a self-refresh operation… signal indicates the self-refresh operation is complete)); and
determine, based at least in part on the value of the mode register, whether to issue a command to the memory system (eg., 0015 - If a self-refresh operation is being performed, the memory controller can wait until the signal indicates the self-refresh operation is complete and then begin sending data read and write requests. The memory device can output the signal to the host device using, for example, an output data bus).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the self-refresh of a memory system as disclosed by Marino, with Boenapalli, with Kim, providing the benefit of improve system performance, including data rate and latency, by reducing the amount of time that read and write requests are paused while self-refresh operations are performed as a memory device exits a self-refresh mode. Sharing the status of the self-refresh operation may also improve queue management for the memory controller while maintaining memory reliability through accurate refresh operations (see Kim, 0015).
Further for Claim 11, Kim discloses: 0021 - memory device 104 may make the determination of whether the self-refresh operation is currently being performed in response to receiving the command to exit the self-refresh mode. 0029 - The memory device 104 can transmit the signal using, for example, an output data bus (e.g., one or more output DQ pins, a data mask inversion (DMI) pin, or a dedicated pin… including host device 102. 0035 - registers 212 may be implemented, for example, as one or more registers that can be used to store information that can be used by the control circuitry 210. 0039 - control circuitry 210 may also provide additional memory features, such as determining an operational status (or a self-refresh operational status) of the memory device 202 and providing the operational status to one or more other devices,.. DQ pins, DMI pin, dedicated pin.. in response to SRX command… in response to the memory device 202 detecting a change in an operating mode (e.g., a beginning or ending of an operating mode, such as a self-refresh mode), a register setting, or an environmental condition. 0049 - Upon receiving the SR EXIT CMD 404, the memory device 104 can determine a self-refresh operational status (e.g., whether the memory device 104 is performing an ABR or a PBR operation). 0043 - the memory device 104 then receives a command 304 to exit the self-refresh mode (SR EXIT CMD 304), which can correspond to the SRX command. Upon receiving the SR EXIT CMD 304, the memory device 104 can determine an operational status (e.g., whether the memory device 104 is currently performing or undergoing an ABR or a PBR operation). In the example depicted in FIG. 3, the memory device 104 determines that the ABR/PBR operation is being performed. In response to the determination, the memory device 104 can transmit a self-refresh operational status signal (SRO status signal) 306 to the host device 102 (e.g., the self-refresh-operation-in-progress signal described with reference to FIG. 1). The SRO status signal 306 indicates that the memory device is performing the ABR/PBR operation and cannot process data read/write requests, even though the host device has transmitted the self-refresh exit command. 0050 - FIG. 4, the memory device 104 determines that the ABR/PBR operation is not being performed. In response to the determination, the memory device 104 can transmit a self-refresh operational status signal (SRO status signal) 406 to the host device 102 (e.g., the no-self-refresh-operation signal described with reference to FIG. 1). the SRO status signal 406 may be realized using a signal with multiple voltages, such as a low or a high voltage level that toggles when the memory device 104 determines whether the ABR/PBR operation is being performed (e.g., low for a no-self-refresh-operation signal and high for self-refresh-operation-in-progress signal, or vice versa). Additionally or alternatively, when the memory device 104 determines no ABR/PBR operation is being performed, the memory device 104 may wait or consume another time duration (not shown) before transmitting the SRO status signal 406 to account for internal operations and other latencies, as described with reference to FIG. 3. 0055 - determine and indicate the self-refresh status, the SRO status signal 506-1 is asserted (e.g., the voltage level is driven high on the one or more pins or other electronic communication mechanism) to indicate that the memory device 104 is performing the self-refresh operation 502-1. 0063 - the memory device 104 or 202 can transmit the no-self-refresh-operation signal, as described with reference to FIG. 1, to the host device 102 or the processors 206 of FIG. 1 and FIG. 2.
In combination with Kim, Boenapalli discloses 0035 - The host controller 112 is configured to initiate a host write monitoring mode. 0039 - the host device 102 may determine a command queue status 146 to detect the idle condition based on one or more operative command queues being empty, and may send the command 148 during the idle condition to prevent the selective refresh operation 180 from interfering . 0045 - which the host controller 112 can use to check the status and determine whether all possible dies 166 in the flash memory device 104 are effectively utilized or not. 0049 - A register, referred to herein as “bWriteMonitoring” (e.g., an 8-bit register), can be set to the value 00h (where “h” indicates hexadecimal) to indicate that write monitoring mode is disabled, 01h to indicate flash device mode, or 02h to indicate host mode. A default mode can be set to 01h (device mode) or to the last operating mode when enabled. In some implementations, the host mode can be enabled when the command queue is empty, and the device mode can be enabled when the flash memory device 104 decides to address its own wear-leveling activities.
The combination of Boenapalli with Kim would have provided the benefit of The host controller 112 is thus configured to evaluate, at the operation 620, whether the trigger condition 132 is satisfied (Boenapalli, 0087) to prevent the selective refresh operation 180 from interfering with execution of pending commands (e.g., read or write commands) (0039), in combination with Kim’s advantage of the benefits of interactive memory self-refresh control (0014) interactive memory self-refresh control can be implemented with a host device or a memory device (0042, 0047).
Claim 12. Marino in view of Boenapalli does not disclose, but Kim discloses
wherein the processing circuitry is further configured to cause the host system to: issue the command to the memory system based at least in part on the value of the mode register being a second value that indicates the self-refresh operation is complete, wherein the command comprises a read command or a write command. (eg., 0015 - in response to a self-refresh exit (SRX) command, the memory device can output a signal to the memory controller that indicates whether the memory device is currently performing an internal self-refresh operation (also referred to as a self-refresh operation… signal indicates the self-refresh operation is complete)).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the self-refresh of a memory system as disclosed by Marino, in view of Boenapalli, with Kim, providing the benefit of improve system performance, including data rate and latency, by reducing the amount of time that read and write requests are paused while self-refresh operations are performed as a memory device exits a self-refresh mode. Sharing the status of the self-refresh operation may also improve queue management for the memory controller while maintaining memory reliability through accurate refresh operations (see Kim, 0015).
Claim 13. Marino in view of Boenapalli does not disclose, but Kim discloses
wherein the processing circuitry is further configured to cause the host system to: issue, to the memory system before polling the mode register, a first command; and determine whether the first command has been executed based at least in part on the value of the mode register (eg., 0015 - in response to a self-refresh exit (SRX) command, the memory device can output a signal to the memory controller that indicates whether the memory device is currently performing an internal self-refresh operation (also referred to as a self-refresh operation… signal indicates the self-refresh operation is complete)); and
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the self-refresh of a memory system as disclosed by Marino, with Boenapalli, with Kim, providing the benefit of improve system performance, including data rate and latency, by reducing the amount of time that read and write requests are paused while self-refresh operations are performed as a memory device exits a self-refresh mode. Sharing the status of the self-refresh operation may also improve queue management for the memory controller while maintaining memory reliability through accurate refresh operations (see Kim, 0015).
Claim 14. Marino in view of Boenapalli does not disclose, but Kim discloses
wherein the processing circuitry is further configured to cause the host system to: transmit, from the host system, a self-refresh exit command that triggers an exit from the self-refresh operation for the memory die of the memory system, wherein the value of the mode register is a second value that indicates the self-refresh operation has been exited based at least in part on the self-refresh exit command (eg., 0015 - in response to a self-refresh exit (SRX) command, the memory device can output a signal to the memory controller that indicates whether the memory device is currently performing an internal self-refresh operation (also referred to as a self-refresh operation… signal indicates the self-refresh operation is complete)).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the self-refresh of a memory system as disclosed by Marino, in view of Boenapalli with Kim, providing the benefit of improve system performance, including data rate and latency, by reducing the amount of time that read and write requests are paused while self-refresh operations are performed as a memory device exits a self-refresh mode. Sharing the status of the self-refresh operation may also improve queue management for the memory controller while maintaining memory reliability through accurate refresh operations (see Kim, 0015).
Claim 15. Marino does not disclose, but Kim discloses
wherein: transmitting the self-refresh exit command is based at least in part on the value of the mode register being set to a first value for at least a threshold time; and the first value indicates that the self-refresh operation is being executed. (e.g., a self-refresh exit command), the memory controller may be “required” to wait for another interval after issuing the command to allow the memory device to complete any in-process self-refresh operations).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the self-refresh of a memory system as disclosed by Marino, with Kim, providing the benefit of improve system performance, including data rate and latency, by reducing the amount of time that read and write requests are paused while self-refresh operations are performed as a memory device exits a self-refresh mode. Sharing the status of the self-refresh operation may also improve queue management for the memory controller while maintaining memory reliability through accurate refresh operations (see Kim, 0015).
Claim 16. Marino does not disclose, but Boenapalli discloses
wherein the processing circuitry is further configured to cause the host system to: issue a second command for a second memory die of the memory system based at least in part on the value of the mode register being set to a first value, wherein the first value indicates that the self-refresh operation is being executed (eg., 0059] The flash memory device 104 performs the selective refresh operation 240 to move the identified data to other dies 166 of the flash memory 164, … moved among the dies 166, the device controller 162 sends to the host controller 112 one or more L2P updates 242 with the latest L2P table information indicating the movement of the data within the flash memory 164.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the host system as disclosed by Manino with Boenapalli, providing the benefit of improvement in write throughput to a flash memory device (eg., Boenapalli, 0021).
Claim 17. Marino does not disclose, but Kim discloses
wherein the processing circuitry is further configured to cause the host system to: issue the command based at least in part on the value of the mode register being set to a first value for at least a threshold time, the command comprising an application exit command or an autonomous driving exit command, wherein the first value indicates that the self-refresh operation is being executed. (e.g., a self-refresh exit command), the memory controller may be “required” to wait for another interval after issuing the command to allow the memory device to complete any in-process self-refresh operations).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the self-refresh of a memory system as disclosed by Marino, with Kim, providing the benefit of improve system performance, including data rate and latency, by reducing the amount of time that read and write requests are paused while self-refresh operations are performed as a memory device exits a self-refresh mode. Sharing the status of the self-refresh operation may also improve queue management for the memory controller while maintaining memory reliability through accurate refresh operations (see Kim, 0015).
Claim 18. Marino does not disclose, but Kim discloses
wherein the processing circuitry is further configured to cause the host system to: receive, via a pin, an indication that the self-refresh operation is complete (eg., [0094] Example 24: The method of any one of examples 21-23, further comprising: detecting a de-assertion of the at least one pin by the memory device to indicate that the memory device has ceased performing the self-refresh operation.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the self-refresh of a memory system as disclosed by Marino, with Kim, providing the benefit of improve system performance, including data rate and latency, by reducing the amount of time that read and write requests are paused while self-refresh operations are performed as a memory device exits a self-refresh mode. Sharing the status of the self-refresh operation may also improve queue management for the memory controller while maintaining memory reliability through accurate refresh operations (see Kim, 0015).
Claim 22. Marino discloses A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to (eg., col 5:40-45 Fig. 2 - host system 230; col 5:35-39 Fig. 2 - The host system 230 can include a host processor 238. ), comprising:
Marino does not disclose, but Boenapalli discloses
transmit, from a host system, a self-refresh initiation command, wherein the self-refresh initiation command is for triggering a self-refresh operation for at least a memory die of a memory system (eg., 0047 - enabling the selective refresh mechanism as initiated by the host device 102.);
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the host system as disclosed by Manino with Boenapalli, providing the benefit of improvement in write throughput to a flash memory device (eg., Boenapalli, 0021).
Marino in view of Boenapalli does not disclose, but Kim discloses
poll a mode register of the memory system, wherein a value of the mode register indicates a status of the self-refresh operation at the memory system (eg., 0015 - in response to a self-refresh exit (SRX) command, the memory device can output a signal to the memory controller that indicates whether the memory device is currently performing an internal self-refresh operation (also referred to as a self-refresh operation… signal indicates the self-refresh operation is complete)); and
determine, based at least in part on the value of the mode register, whether to issue a command to the memory system (eg., 0015 - If a self-refresh operation is being performed, the memory controller can wait until the signal indicates the self-refresh operation is complete and then begin sending data read and write requests. The memory device can output the signal to the host device using, for example, an output data bus).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the self-refresh of a memory system as disclosed by Marino, with Boenapalli, with Kim, providing the benefit of improve system performance, including data rate and latency, by reducing the amount of time that read and write requests are paused while self-refresh operations are performed as a memory device exits a self-refresh mode. Sharing the status of the self-refresh operation may also improve queue management for the memory controller while maintaining memory reliability through accurate refresh operations (see Kim, 0015).
Further for Claim 22, Kim discloses: 0021 - memory device 104 may make the determination of whether the self-refresh operation is currently being performed in response to receiving the command to exit the self-refresh mode. 0029 - The memory device 104 can transmit the signal using, for example, an output data bus (e.g., one or more output DQ pins, a data mask inversion (DMI) pin, or a dedicated pin… including host device 102. 0035 - registers 212 may be implemented, for example, as one or more registers that can be used to store information that can be used by the control circuitry 210. 0039 - control circuitry 210 may also provide additional memory features, such as determining an operational status (or a self-refresh operational status) of the memory device 202 and providing the operational status to one or more other devices,.. DQ pins, DMI pin, dedicated pin.. in response to SRX command… in response to the memory device 202 detecting a change in an operating mode (e.g., a beginning or ending of an operating mode, such as a self-refresh mode), a register setting, or an environmental condition. 0049 - Upon receiving the SR EXIT CMD 404, the memory device 104 can determine a self-refresh operational status (e.g., whether the memory device 104 is performing an ABR or a PBR operation). 0043 - the memory device 104 then receives a command 304 to exit the self-refresh mode (SR EXIT CMD 304), which can correspond to the SRX command. Upon receiving the SR EXIT CMD 304, the memory device 104 can determine an operational status (e.g., whether the memory device 104 is currently performing or undergoing an ABR or a PBR operation). In the example depicted in FIG. 3, the memory device 104 determines that the ABR/PBR operation is being performed. In response to the determination, the memory device 104 can transmit a self-refresh operational status signal (SRO status signal) 306 to the host device 102 (e.g., the self-refresh-operation-in-progress signal described with reference to FIG. 1). The SRO status signal 306 indicates that the memory device is performing the ABR/PBR operation and cannot process data read/write requests, even though the host device has transmitted the self-refresh exit command. 0050 - FIG. 4, the memory device 104 determines that the ABR/PBR operation is not being performed. In response to the determination, the memory device 104 can transmit a self-refresh operational status signal (SRO status signal) 406 to the host device 102 (e.g., the no-self-refresh-operation signal described with reference to FIG. 1). the SRO status signal 406 may be realized using a signal with multiple voltages, such as a low or a high voltage level that toggles when the memory device 104 determines whether the ABR/PBR operation is being performed (e.g., low for a no-self-refresh-operation signal and high for self-refresh-operation-in-progress signal, or vice versa). Additionally or alternatively, when the memory device 104 determines no ABR/PBR operation is being performed, the memory device 104 may wait or consume another time duration (not shown) before transmitting the SRO status signal 406 to account for internal operations and other latencies, as described with reference to FIG. 3. 0055 - determine and indicate the self-refresh status, the SRO status signal 506-1 is asserted (e.g., the voltage level is driven high on the one or more pins or other electronic communication mechanism) to indicate that the memory device 104 is performing the self-refresh operation 502-1. 0063 - the memory device 104 or 202 can transmit the no-self-refresh-operation signal, as described with reference to FIG. 1, to the host device 102 or the processors 206 of FIG. 1 and FIG. 2.
In combination with Kim, Boenapalli discloses 0035 - The host controller 112 is configured to initiate a host write monitoring mode. 0039 - the host device 102 may determine a command queue status 146 to detect the idle condition based on one or more operative command queues being empty, and may send the command 148 during the idle condition to prevent the selective refresh operation 180 from interfering . 0045 - which the host controller 112 can use to check the status and determine whether all possible dies 166 in the flash memory device 104 are effectively utilized or not. 0049 - A register, referred to herein as “bWriteMonitoring” (e.g., an 8-bit register), can be set to the value 00h (where “h” indicates hexadecimal) to indicate that write monitoring mode is disabled, 01h to indicate flash device mode, or 02h to indicate host mode. A default mode can be set to 01h (device mode) or to the last operating mode when enabled. In some implementations, the host mode can be enabled when the command queue is empty, and the device mode can be enabled when the flash memory device 104 decides to address its own wear-leveling activities.
The combination of Boenapalli with Kim would have provided the benefit of The host controller 112 is thus configured to evaluate, at the operation 620, whether the trigger condition 132 is satisfied (Boenapalli, 0087) to prevent the selective refresh operation 180 from interfering with execution of pending commands (e.g., read or write commands) (0039), in combination with Kim’s advantage of the benefits of interactive memory self-refresh control (0014) interactive memory self-refresh control can be implemented with a host device or a memory device (0042, 0047).
Claim 23 is rejected for reasons similar to Claim 12 above.
Claim 24 is rejected for reasons similar to Claim 13 above.
Claims 6, 7, 8 are rejected under 35 U.S.C. 103 as being unpatentable over Marino (US 11561739 B1) and in view of Kim (US 20220139448 A1) and Saifuddin (US 20170316818), and further in view of Boenapalli (US 20250103232 A1)
Claim 6. Marino in view of Kim and Saifuddin does not disclose, but Boenapalli discloses
wherein the processing circuitry is further configured to cause the memory system to: maintain the first value of the mode register based at least in part on the status of the self-refresh operation being pending; and receive, at the memory system based at least in part on the mode register being set to the first value, an access command for a second memory die of the memory system (eg., 0039 - send the command 148 during the idle condition to prevent the selective refresh operation 180 from interfering with execution of pending commands (e.g., read or write commands) for the flash memory device 104.; 0007 - determining whether a trigger condition is satisfied. The trigger condition is associated with checking a distribution of write data that is written to the flash memory device. The method also includes, based on determining that the trigger condition is satisfied, identifying a die of the flash memory device that has a higher data occupancy than at least one other die of the flash memory device, and sending a command to the flash memory device to move data from the identified die to one or more other dies of the flash memory device.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the host system as disclosed by Manino in view of Kim and Saifuddin with Boenapalli, providing the benefit of improvement in write throughput to a flash memory device (eg., Boenapalli, 0021).
Claim 7. Marino in view of Kim and Saifuddin does not disclose, but Boenapalli discloses wherein the processing circuitry is further configured to cause the memory system to: maintain the first value of the mode register based at least in part on the status of the self-refresh operation being pending, wherein maintaining the first value of the mode register comprises refraining from driving an output associated with the mode register (eg., [0096] The host device operations 790 include, when there are no pending requests to be served (e.g., the operative command queue is empty), entering an “idle mode” pre-hibernate state, at 714, and sending recommendations to the flash device to update/spread LBAs to multiple DIEs through a selective refresh command, at 716. ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the host system as disclosed by Manino in view of Kim and Saifuddin with Boenapalli, providing the benefit of improvement in write throughput to a flash memory device (eg., Boenapalli, 0021).
Claim 8. Marino in view of Kim and Saifuddin does not disclose, but Boenapalli discloses
wherein the processing circuitry is further configured to cause the memory system to: receive a self-refresh initiation command, wherein initiating the self-refresh operation for the memory die is based at least in part on the self-refresh initiation command (eg., 0047 - enabling the selective refresh mechanism as initiated by the host device 102.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the host system as disclosed by Manino in view of Kim and Saifuddin with Boenapalli, providing the benefit of improvement in write throughput to a flash memory device (eg., Boenapalli, 0021).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GAUTAM SAIN whose telephone number is (571)270-3555. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared Rutz can be reached at 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GAUTAM SAIN/Primary Examiner, Art Unit 2135
Prosecution Insights