DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Other References: Kim (US 20220246201) - receiving a refresh command, performing a refresh operation on a target row of a bank memory array, and providing status information to a memory controller
Bains (US 20170169880) – Self refresh mode.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 9, 10, 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over Marino (US 11561739 B1) and in view of Kim (US 20220139448 A1)
Claim 1. Marino discloses A memory system (eg., col 4:20-25 Fig. 2 - hybrid memory unit 202 ), comprising:
one or more memory devices (eg., col 4:20-27 Fig. 2 - volatile memory 212 to the non-volatile memory 208); and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to: (eg., col 4:30-35 Fig. 2 - controller 204 can operate the hybrid memory unit 202)
initiate a self-refresh operation for a memory die of the memory system (eg., col 9:54-57 - The hybrid memory unit 302 can put the volatile memory 304 into the self-refresh mode by issuing a self-refresh entry command 348. );
set a mode register to a first value based at least in part on initiating the self-refresh operation, wherein the first value of the mode register indicates that the self-refresh operation is being executed (eg., col 9:15-20 Fig 3 - the health register 342 can include a self-refresh mode value 344, such as a DRAM_NOT_SELF_REFRESH bit. The self-refresh mode value 344 can indicate if the SDRAM of the hybrid memory unit 302 is operating in a self-refresh mode.); and
Marino does not disclose, but Kim discloses
determine whether to reset the mode register to a second value based at least in part on a status of the self-refresh operation, wherein the second value of the mode register indicates that the self-refresh operation is complete (eg., 0015 - in response to a self-refresh exit (SRX) command, the memory device can output a signal to the memory controller that indicates whether the memory device is currently performing an internal self-refresh operation (also referred to as a self-refresh operation… signal indicates the self-refresh operation is complete)).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the self-refresh of a memory system as disclosed by Marino, with Kim, providing the benefit of improve system performance, including data rate and latency, by reducing the amount of time that read and write requests are paused while self-refresh operations are performed as a memory device exits a self-refresh mode. Sharing the status of the self-refresh operation may also improve queue management for the memory controller while maintaining memory reliability through accurate refresh operations (see Kim, 0015).
Claim 2. Marino does not disclose, but Kim discloses
wherein the processing circuitry is further configured to cause the memory system to: complete the self-refresh operation for the memory die; and reset the mode register to the second value based at least in part on completing the self-refresh operation, wherein determining whether to reset the mode register to the second value comprises determining to reset the mode register to the second value based at least in part on completing the self-refresh operation (eg., 0015 - in response to a self-refresh exit (SRX) command, the memory device can output a signal to the memory controller that indicates whether the memory device is currently performing an internal self-refresh operation (also referred to as a self-refresh operation… signal indicates the self-refresh operation is complete)).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the self-refresh of a memory system as disclosed by Marino, with Kim, providing the benefit of improve system performance, including data rate and latency, by reducing the amount of time that read and write requests are paused while self-refresh operations are performed as a memory device exits a self-refresh mode. Sharing the status of the self-refresh operation may also improve queue management for the memory controller while maintaining memory reliability through accurate refresh operations (see Kim, 0015).
Claim 3. Marino does not disclose, but Kim discloses
wherein the processing circuitry is further configured to cause the memory system to: receive a self-refresh exit command; exit the self-refresh operation prior to completion based at least in part on the self-refresh exit command; and reset the mode register to the second value based at least in part on exiting the self-refresh operation, wherein determining whether to reset the mode register to the second value comprises determining to reset the mode register to the second value based at least in part on exiting the self-refresh operation (eg., 0015 - in response to a self-refresh exit (SRX) command, the memory device can output a signal to the memory controller that indicates whether the memory device is currently performing an internal self-refresh operation (also referred to as a self-refresh operation… signal indicates the self-refresh operation is complete)).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the self-refresh of a memory system as disclosed by Marino, with Kim, providing the benefit of improve system performance, including data rate and latency, by reducing the amount of time that read and write requests are paused while self-refresh operations are performed as a memory device exits a self-refresh mode. Sharing the status of the self-refresh operation may also improve queue management for the memory controller while maintaining memory reliability through accurate refresh operations (see Kim, 0015).
Claim 4. Marino does not disclose, but Kim discloses
wherein receiving the self-refresh exit command is based at least in part on the mode register being set to the first value for at least a threshold time (eg., 0012 - memory controller issues a command to end a self-refresh operation or exit a self-refresh mode (e.g., a self-refresh exit command), the memory controller may be “required” to wait for another interval after issuing the command to allow the memory device to complete any in-process self-refresh operations).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the self-refresh of a memory system as disclosed by Marino, with Kim, providing the benefit of improve system performance, including data rate and latency, by reducing the amount of time that read and write requests are paused while self-refresh operations are performed as a memory device exits a self-refresh mode. Sharing the status of the self-refresh operation may also improve queue management for the memory controller while maintaining memory reliability through accurate refresh operations (see Kim, 0015).
Claim 5. Marino does not disclose, but Kim discloses
wherein the processing circuitry is further configured to cause the memory system to: reset the mode register to the second value based at least in part on exiting the self-refresh operation or completing the self-refresh operation; and receive one or more access commands based at least in part on resetting the mode register to the second value, the one or more access commands comprising a read command, a write command, or both (eg., 0015 - If a self-refresh operation is being performed, the memory controller can wait until the signal indicates the self-refresh operation is complete and then begin sending data read and write requests. The memory device can output the signal to the host device using, for example, an output data bus).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the self-refresh of a memory system as disclosed by Marino, with Kim, providing the benefit of improve system performance, including data rate and latency, by reducing the amount of time that read and write requests are paused while self-refresh operations are performed as a memory device exits a self-refresh mode. Sharing the status of the self-refresh operation may also improve queue management for the memory controller while maintaining memory reliability through accurate refresh operations (see Kim, 0015).
Claim 9. Marino does not disclose, but Kim discloses
wherein the processing circuitry is further configured to cause the memory system to: complete the self-refresh operation for the memory die; and transmit, via a pin, a signal that indicates the self-refresh operation is complete (eg., 0015 - in response to a self-refresh exit (SRX) command, the memory device can output a signal to the memory controller that indicates whether the memory device is currently performing an internal self-refresh operation (also referred to as a self-refresh operation… signal indicates the self-refresh operation is complete)).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the self-refresh of a memory system as disclosed by Marino, with Kim, providing the benefit of improve system performance, including data rate and latency, by reducing the amount of time that read and write requests are paused while self-refresh operations are performed as a memory device exits a self-refresh mode. Sharing the status of the self-refresh operation may also improve queue management for the memory controller while maintaining memory reliability through accurate refresh operations (see Kim, 0015).
Claim 10. Marino does not disclose, but Kim discloses
wherein the processing circuitry is further configured to cause the memory system to: set the mode register to the second value based at least in part on completing the self-refresh operation, wherein transmitting the signal is based at least in part on the second value of the mode register (eg., 0015 - in response to a self-refresh exit (SRX) command, the memory device can output a signal to the memory controller that indicates whether the memory device is currently performing an internal self-refresh operation (also referred to as a self-refresh operation… signal indicates the self-refresh operation is complete)).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the self-refresh of a memory system as disclosed by Marino, with Kim, providing the benefit of improve system performance, including data rate and latency, by reducing the amount of time that read and write requests are paused while self-refresh operations are performed as a memory device exits a self-refresh mode. Sharing the status of the self-refresh operation may also improve queue management for the memory controller while maintaining memory reliability through accurate refresh operations (see Kim, 0015).
Claim 19. Marino discloses A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to (eg., col 4:20-25 Fig. 2 - hybrid memory unit 202 ; col 4:30-35 Fig. 2 - controller 204 can operate the hybrid memory unit 202)
initiate a self-refresh operation for a memory die of the memory system (eg., col 9:54-57 - The hybrid memory unit 302 can put the volatile memory 304 into the self-refresh mode by issuing a self-refresh entry command 348. );
set a mode register to a first value based at least in part on initiating the self-refresh operation, wherein the first value of the mode register indicates that the self-refresh operation is being executed (eg., col 9:15-20 Fig 3 - the health register 342 can include a self-refresh mode value 344, such as a DRAM_NOT_SELF_REFRESH bit. The self-refresh mode value 344 can indicate if the SDRAM of the hybrid memory unit 302 is operating in a self-refresh mode.); and
Marino does not disclose, but Kim discloses
determine whether to reset the mode register to a second value based at least in part on a status of the self-refresh operation, wherein the second value of the mode register indicates that the self-refresh operation is complete (eg., 0015 - in response to a self-refresh exit (SRX) command, the memory device can output a signal to the memory controller that indicates whether the memory device is currently performing an internal self-refresh operation (also referred to as a self-refresh operation… signal indicates the self-refresh operation is complete)).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the self-refresh of a memory system as disclosed by Marino, with Kim, providing the benefit of improve system performance, including data rate and latency, by reducing the amount of time that read and write requests are paused while self-refresh operations are performed as a memory device exits a self-refresh mode. Sharing the status of the self-refresh operation may also improve queue management for the memory controller while maintaining memory reliability through accurate refresh operations (see Kim, 0015).
Claim 20 is rejected for reasons similar to Claim 2 above.
Claim 21 is rejected for reasons similar to Claim 3 above.
Claims 11-18, 22-24 are rejected under 35 U.S.C. 103 as being unpatentable over Marino (US 11561739 B1) and in view of Boenapalli (US 20250103232 A1) and further in view of Kim (US 20220139448 A1)
Claim 11. Marino discloses A host system (eg., col 5:40-45 Fig. 2 - host system 230), comprising:
one or more interfaces comprising one or more signal paths operable for communications with one or more memory systems (eg., col 5:45-46 Fig. 2 - memory bus connector 234 is an electromechanical element for attaching the memory to the host system 230); and
processing circuitry coupled with the one or more interfaces and configured to cause the host system to: (eg., col 5:35-39 Fig. 2 - The host system 230 can include a host processor 238. )
Marino does not disclose, but Boenapalli discloses
transmit, from the host system, a self-refresh initiation command, wherein the self-refresh initiation command is for triggering a self-refresh operation for at least a memory die of a memory system (eg., 0047 - enabling the selective refresh mechanism as initiated by the host device 102.);
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the host system as disclosed by Manino with Boenapalli, providing the benefit of improvement in write throughput to a flash memory device (eg., Boenapalli, 0021).
Marino in view of Boenapalli does not disclose, but Kim discloses
poll a mode register of the memory system, wherein a value of the mode register indicates a status of the self-refresh operation at the memory system (eg., 0015 - in response to a self-refresh exit (SRX) command, the memory device can output a signal to the memory controller that indicates whether the memory device is currently performing an internal self-refresh operation (also referred to as a self-refresh operation… signal indicates the self-refresh operation is complete)); and
determine, based at least in part on the value of the mode register, whether to issue a command to the memory system (eg., 0015 - If a self-refresh operation is being performed, the memory controller can wait until the signal indicates the self-refresh operation is complete and then begin sending data read and write requests. The memory device can output the signal to the host device using, for example, an output data bus).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the self-refresh of a memory system as disclosed by Marino, with Boenapalli, with Kim, providing the benefit of improve system performance, including data rate and latency, by reducing the amount of time that read and write requests are paused while self-refresh operations are performed as a memory device exits a self-refresh mode. Sharing the status of the self-refresh operation may also improve queue management for the memory controller while maintaining memory reliability through accurate refresh operations (see Kim, 0015).
Claim 12. Marino in view of Boenapalli does not disclose, but Kim discloses
wherein the processing circuitry is further configured to cause the host system to: issue the command to the memory system based at least in part on the value of the mode register being a second value that indicates the self-refresh operation is complete, wherein the command comprises a read command or a write command. (eg., 0015 - in response to a self-refresh exit (SRX) command, the memory device can output a signal to the memory controller that indicates whether the memory device is currently performing an internal self-refresh operation (also referred to as a self-refresh operation… signal indicates the self-refresh operation is complete)).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the self-refresh of a memory system as disclosed by Marino, in view of Boenapalli, with Kim, providing the benefit of improve system performance, including data rate and latency, by reducing the amount of time that read and write requests are paused while self-refresh operations are performed as a memory device exits a self-refresh mode. Sharing the status of the self-refresh operation may also improve queue management for the memory controller while maintaining memory reliability through accurate refresh operations (see Kim, 0015).
Claim 13. Marino in view of Boenapalli does not disclose, but Kim discloses
wherein the processing circuitry is further configured to cause the host system to: issue, to the memory system before polling the mode register, a first command; and determine whether the first command has been executed based at least in part on the value of the mode register (eg., 0015 - in response to a self-refresh exit (SRX) command, the memory device can output a signal to the memory controller that indicates whether the memory device is currently performing an internal self-refresh operation (also referred to as a self-refresh operation… signal indicates the self-refresh operation is complete)); and
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the self-refresh of a memory system as disclosed by Marino, with Boenapalli, with Kim, providing the benefit of improve system performance, including data rate and latency, by reducing the amount of time that read and write requests are paused while self-refresh operations are performed as a memory device exits a self-refresh mode. Sharing the status of the self-refresh operation may also improve queue management for the memory controller while maintaining memory reliability through accurate refresh operations (see Kim, 0015).
Claim 14. Marino in view of Boenapalli does not disclose, but Kim discloses
wherein the processing circuitry is further configured to cause the host system to: transmit, from the host system, a self-refresh exit command that triggers an exit from the self-refresh operation for the memory die of the memory system, wherein the value of the mode register is a second value that indicates the self-refresh operation has been exited based at least in part on the self-refresh exit command (eg., 0015 - in response to a self-refresh exit (SRX) command, the memory device can output a signal to the memory controller that indicates whether the memory device is currently performing an internal self-refresh operation (also referred to as a self-refresh operation… signal indicates the self-refresh operation is complete)).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the self-refresh of a memory system as disclosed by Marino, in view of Boenapalli with Kim, providing the benefit of improve system performance, including data rate and latency, by reducing the amount of time that read and write requests are paused while self-refresh operations are performed as a memory device exits a self-refresh mode. Sharing the status of the self-refresh operation may also improve queue management for the memory controller while maintaining memory reliability through accurate refresh operations (see Kim, 0015).
Claim 15. Marino does not disclose, but Kim discloses
wherein: transmitting the self-refresh exit command is based at least in part on the value of the mode register being set to a first value for at least a threshold time; and the first value indicates that the self-refresh operation is being executed. (e.g., a self-refresh exit command), the memory controller may be “required” to wait for another interval after issuing the command to allow the memory device to complete any in-process self-refresh operations).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the self-refresh of a memory system as disclosed by Marino, with Kim, providing the benefit of improve system performance, including data rate and latency, by reducing the amount of time that read and write requests are paused while self-refresh operations are performed as a memory device exits a self-refresh mode. Sharing the status of the self-refresh operation may also improve queue management for the memory controller while maintaining memory reliability through accurate refresh operations (see Kim, 0015).
Claim 16. Marino does not disclose, but Boenapalli discloses
wherein the processing circuitry is further configured to cause the host system to: issue a second command for a second memory die of the memory system based at least in part on the value of the mode register being set to a first value, wherein the first value indicates that the self-refresh operation is being executed (eg., 0059] The flash memory device 104 performs the selective refresh operation 240 to move the identified data to other dies 166 of the flash memory 164, … moved among the dies 166, the device controller 162 sends to the host controller 112 one or more L2P updates 242 with the latest L2P table information indicating the movement of the data within the flash memory 164.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the host system as disclosed by Manino with Boenapalli, providing the benefit of improvement in write throughput to a flash memory device (eg., Boenapalli, 0021).
Claim 17. Marino does not disclose, but Kim discloses
wherein the processing circuitry is further configured to cause the host system to: issue the command based at least in part on the value of the mode register being set to a first value for at least a threshold time, the command comprising an application exit command or an autonomous driving exit command, wherein the first value indicates that the self-refresh operation is being executed. (e.g., a self-refresh exit command), the memory controller may be “required” to wait for another interval after issuing the command to allow the memory device to complete any in-process self-refresh operations).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the self-refresh of a memory system as disclosed by Marino, with Kim, providing the benefit of improve system performance, including data rate and latency, by reducing the amount of time that read and write requests are paused while self-refresh operations are performed as a memory device exits a self-refresh mode. Sharing the status of the self-refresh operation may also improve queue management for the memory controller while maintaining memory reliability through accurate refresh operations (see Kim, 0015).
Claim 18. Marino does not disclose, but Kim discloses
wherein the processing circuitry is further configured to cause the host system to: receive, via a pin, an indication that the self-refresh operation is complete (eg., [0094] Example 24: The method of any one of examples 21-23, further comprising: detecting a de-assertion of the at least one pin by the memory device to indicate that the memory device has ceased performing the self-refresh operation.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the self-refresh of a memory system as disclosed by Marino, with Kim, providing the benefit of improve system performance, including data rate and latency, by reducing the amount of time that read and write requests are paused while self-refresh operations are performed as a memory device exits a self-refresh mode. Sharing the status of the self-refresh operation may also improve queue management for the memory controller while maintaining memory reliability through accurate refresh operations (see Kim, 0015).
Claim 22. Marino discloses A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to (eg., col 5:40-45 Fig. 2 - host system 230; col 5:35-39 Fig. 2 - The host system 230 can include a host processor 238. ), comprising:
Marino does not disclose, but Boenapalli discloses
transmit, from a host system, a self-refresh initiation command, wherein the self-refresh initiation command is for triggering a self-refresh operation for at least a memory die of a memory system (eg., 0047 - enabling the selective refresh mechanism as initiated by the host device 102.);
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the host system as disclosed by Manino with Boenapalli, providing the benefit of improvement in write throughput to a flash memory device (eg., Boenapalli, 0021).
Marino in view of Boenapalli does not disclose, but Kim discloses
poll a mode register of the memory system, wherein a value of the mode register indicates a status of the self-refresh operation at the memory system (eg., 0015 - in response to a self-refresh exit (SRX) command, the memory device can output a signal to the memory controller that indicates whether the memory device is currently performing an internal self-refresh operation (also referred to as a self-refresh operation… signal indicates the self-refresh operation is complete)); and
determine, based at least in part on the value of the mode register, whether to issue a command to the memory system (eg., 0015 - If a self-refresh operation is being performed, the memory controller can wait until the signal indicates the self-refresh operation is complete and then begin sending data read and write requests. The memory device can output the signal to the host device using, for example, an output data bus).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the self-refresh of a memory system as disclosed by Marino, with Boenapalli, with Kim, providing the benefit of improve system performance, including data rate and latency, by reducing the amount of time that read and write requests are paused while self-refresh operations are performed as a memory device exits a self-refresh mode. Sharing the status of the self-refresh operation may also improve queue management for the memory controller while maintaining memory reliability through accurate refresh operations (see Kim, 0015).
Claim 23 is rejected for reasons similar to Claim 12 above.
Claim 24 is rejected for reasons similar to Claim 13 above.
Claims 6, 7, 8 are rejected under 35 U.S.C. 103 as being unpatentable over Marino (US 11561739 B1) and in view of Kim (US 20220139448 A1) and in view of Boenapalli (US 20250103232 A1)
Claim 6. Marino in view of Kim does not disclose, but Boenapalli discloses
wherein the processing circuitry is further configured to cause the memory system to: maintain the first value of the mode register based at least in part on the status of the self-refresh operation being pending; and receive, at the memory system based at least in part on the mode register being set to the first value, an access command for a second memory die of the memory system (eg., 0039 - send the command 148 during the idle condition to prevent the selective refresh operation 180 from interfering with execution of pending commands (e.g., read or write commands) for the flash memory device 104.; 0007 - determining whether a trigger condition is satisfied. The trigger condition is associated with checking a distribution of write data that is written to the flash memory device. The method also includes, based on determining that the trigger condition is satisfied, identifying a die of the flash memory device that has a higher data occupancy than at least one other die of the flash memory device, and sending a command to the flash memory device to move data from the identified die to one or more other dies of the flash memory device.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the host system as disclosed by Manino in view of Kim with Boenapalli, providing the benefit of improvement in write throughput to a flash memory device (eg., Boenapalli, 0021).
Claim 7. Marino in view of Kim does not disclose, but Boenapalli discloses wherein the processing circuitry is further configured to cause the memory system to: maintain the first value of the mode register based at least in part on the status of the self-refresh operation being pending, wherein maintaining the first value of the mode register comprises refraining from driving an output associated with the mode register (eg., [0096] The host device operations 790 include, when there are no pending requests to be served (e.g., the operative command queue is empty), entering an “idle mode” pre-hibernate state, at 714, and sending recommendations to the flash device to update/spread LBAs to multiple DIEs through a selective refresh command, at 716. ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the host system as disclosed by Manino in view of Kim with Boenapalli, providing the benefit of improvement in write throughput to a flash memory device (eg., Boenapalli, 0021).
Claim 8. Marino in view of Kim does not disclose, but Boenapalli discloses
wherein the processing circuitry is further configured to cause the memory system to: receive a self-refresh initiation command, wherein initiating the self-refresh operation for the memory die is based at least in part on the self-refresh initiation command (eg., 0047 - enabling the selective refresh mechanism as initiated by the host device 102.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the host system as disclosed by Manino in view of Kim with Boenapalli, providing the benefit of improvement in write throughput to a flash memory device (eg., Boenapalli, 0021).
Conclusion
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/GAUTAM SAIN/Primary Examiner, Art Unit 2135