DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
2. Claims 1-20 are presented for examination.
Abstract
3. The abstract of the disclosure is acceptable for examination purposes.
Oath Declaration
4. The Oath complies with all the requirements set forth in MPEP 602 and therefore is accepted.
Drawings
5. The drawings received on 12/17/2024 are acceptable for examination purposes.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
6. Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
As per claim 1:
The claim recites “A method comprising: sending a select gate scan command to a memory device to cause the memory device to perform a select gate scan at a select gate bias voltage on a memory portion of the memory device; receiving, from the memory device, a failed bit count, wherein the failed bit count is a number of bits of the memory portion with threshold voltages exceeding the select gate bias voltage; determining that the failed bit count satisfies a refresh threshold; and performing a refresh operation on the memory portion in response to determining that the failed bit count satisfies the refresh threshold.”
At Step 1, is the claim directed to a processor, machine, manufacture or composition of matter? Yes, see MPEP 2106.03. The claim recites a series of steps and, therefore, is a process, and thus directed to a statutory category. At step 2A Prong One, Does the claim recite an abstract idea law of nature or natural phenomenon? Yes, see MPEP 2106.04. The claim recites “determining that the failed bit count satisfies a refresh threshold; and performing a refresh operation on the memory portion in response to determining that the failed bit count satisfies the refresh threshold,” as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the human mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea. At step 2A Prong Two, Does the claim recite additional elements that integrate the judicial exception into a practical application? NO, see MPEP 2106.04(d). The claim recites additional element/s of “sending a select gate scan command --- to perform a select gate scan at a select gate bias voltage on a memory portion---,” “receiving, ---, a failed bit count, wherein the failed bit count is a number of bits of the memory portion with threshold voltages exceeding the select gate bias voltage” and do not integrate the abstract idea into a practical application because is generic computer function of data mere data gathering and sending. These extra-solution activities do not provide practical application, as discussed in MPEP 2106.05(f). At step 2B, Does the claim recite additional elements that amount to significantly more than judicial exception? NO, see MPEP 2106.05. The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional element/s “memory device” is generic components that are well understood, routine and conventional and do not result in the claim as a whole amounting to significantly more than the abstract idea. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. In Berkheimer v. HP, Inc., 881 F.3d 1360, 125 USPQ2d 1649 (Fed. Cir. 2018), in which the patentee claimed methods for parsing and evaluating data using a computer processing system. See the prior art Shukla et al. US 2023/0195355 A1 in Figs. 1 & 9, and Trivedi US 20230207029 A1 in Figs. 1 & 5 teach well known elements. Therefore, the claim is not patent eligible.
As per claim 9:
The claim recites “A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: send a select gate scan command to a memory device to cause the memory device to perform a select gate scan at a select gate bias voltage on a memory portion of the memory device; receive, from the memory device, a failed bit count, wherein the failed bit count is a number of bits of the memory portion with threshold voltages exceeding the select gate bias voltage; determine that the failed bit count satisfies a refresh threshold; and perform a refresh operation on the memory portion in response to determining that the failed bit count satisfies the refresh threshold.”
At Step 1, is the claim directed to a processor, machine, manufacture or composition of matter? Yes, see MPEP 2106.03. The claim is directed to "A non-transitory, computer-readable media" and thus directed to a statutory category. At step 2A Prong One, Does the claim recite an abstract idea law of nature or natural phenomenon? Yes, see MPEP 2106.04. The claim recites “wherein the failed bit count is a number of bits of --- with threshold voltages exceeding the select gate bias voltage; determine that the failed bit count satisfies a refresh threshold; and perform a refresh operation on the memory portion in response to determining that the failed bit count satisfies the refresh threshold,” as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the human mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea. At step 2A Prong Two, Does the claim recite additional elements that integrate the judicial exception into a practical application? NO, see MPEP 2106.04(d). The claim recites additional element/s of “send a select gate scan command --- to cause the memory device to perform a select gate scan at a select gate bias voltage ---; receive, from the memory device, a failed bit count” and do not integrate the abstract idea into a practical application because is generic computer function of data mere data gathering and sending. These extra-solution activities do not provide practical application, as discussed in MPEP 2106.05(f). At step 2B, Does the claim recite additional elements that amount to significantly more than judicial exception? NO, see MPEP 2106.05. The claim recites additional element/s “a memory device,” “a memory portion,” “A non-transitory computer-readable storage medium,” and “a processing device” are generic components that are well understood, routine and conventional and do not result in the claim as a whole amounting to significantly more than the abstract idea. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. In Berkheimer v. HP, Inc., 881 F.3d 1360, 125 USPQ2d 1649 (Fed. Cir. 2018), in which the patentee claimed methods for parsing and evaluating data using a computer processing system. The Federal Circuit determined that these claims were directed to mental processes of parsing and comparing data, because the steps were recited at a high level of generality and merely used computers as a tool to perform the processes. 881 F.3d at 1366, 125 USPQ2d at 1652-53. See MPEP 2106.05(a). See the prior art Shukla et al. US 2023/0195355 A1 in Figs. 1 & 9, and Trivedi US 20230207029 A1 in Figs. 1 & 5 teach well known elements. Therefore, the claim is not patent eligible.
As per claim 17:
The claim recites “A system comprising: a plurality of memory devices; and a processing device, operatively coupled with the plurality of memory devices, to: determine a select gate type for a select gate scan command; determine a select gate bias voltage using the select gate type; send the select gate scan command including the select gate bias voltage to a memory device to cause the memory device to perform a select gate scan at the select gate bias voltage on a memory portion of the memory device; receive, from the memory device, a failed bit count, wherein the failed bit count is a number of bits of the memory portion with threshold voltages exceeding the select gate bias voltage; determine that the failed bit count satisfies a refresh threshold; and perform a refresh operation on the memory portion in response to determining that the failed bit count satisfies the refresh threshold.”
At Step 1, is the claim directed to a processor, machine, manufacture or composition of matter? Yes, see MPEP 2106.03. The claim is directed to "a system" and thus directed to a statutory category. At step 2A Prong One, Does the claim recite an abstract idea law of nature or natural phenomenon? Yes, see MPEP 2106.04. The claim recites “determine a select gate type for a select gate scan command; determine a select gate bias voltage using the select gate type;--- wherein the failed bit count is a number of bits of the memory portion with threshold voltages exceeding the select gate bias voltage; determine that the failed bit count satisfies a refresh threshold; and perform a refresh operation on the memory portion in response to determining that the failed bit count satisfies the refresh threshold,” as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the human mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea. At step 2A Prong Two, Does the claim recite additional elements that integrate the judicial exception into a practical application? NO, see MPEP 2106.04(d). The claim recites additional element/s of “send the select gate scan command including the select gate bias voltage --- perform a select gate scan at the select gate bias voltage ---; receive --- a failed bit count” do not integrate the abstract idea into a practical application because is generic computer function of data mere data gathering and sending. These extra-solution activities do not provide practical application, as discussed in MPEP 2106.05(f). At step 2B, Does the claim recite additional elements that amount to significantly more than judicial exception? NO, see MPEP 2106.05. The claim recites additional element/s “a plurality of memory devices,” “a processing device,” “a memory device,” “a memory portion,” are generic components that are well understood, routine and conventional and do not result in the claim as a whole amounting to significantly more than the abstract idea. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. In Berkheimer v. HP, Inc., 881 F.3d 1360, 125 USPQ2d 1649 (Fed. Cir. 2018), in which the patentee claimed methods for parsing and evaluating data using a computer processing system. The Federal Circuit determined that these claims were directed to mental processes of parsing and comparing data, because the steps were recited at a high level of generality and merely used computers as a tool to perform the processes. 881 F.3d at 1366, 125 USPQ2d at 1652-53. See MPEP 2106.05(a). See the prior art Shukla et al. US 2023/0195355 A1 in Figs. 1 & 9, and Trivedi US 20230207029 A1 in Figs. 1 & 5 teach well known elements. Therefore, the claim is not patent eligible.
Dependent claims 2-8, 10-16, and 18-20 are extended elements of the abstract idea of the independent claims and the claims are abstract in nature falling withing Mental Processes. The dependent claims do not add any meaningful limits to the abstract idea to improve the technology or the computer component and fails to add significantly more than the abstracts idea. Therefore, the dependent claims are not patent eligible.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
7. Claims 1-20 are rejected under 35 U.S.C. 103 (a) as being unpatentable over Shukla et al. (US 2023/0195355 A1) "herein after as Shukla" in view of Liang et al. (US 2016/0163393 A1) "herein after as Liang."
As per claim 1:
Shukla substantially teaches or discloses a method comprising: sending a select gate scan command to a memory device to cause the memory device to perform a select gate scan at a select gate bias voltage on a memory portion of the memory device (see abstract, paragraph [0040], herein the memory sub-system 110 can include a select gate scan component 113. Although not shown in FIG. 1 so as to not obfuscate the drawings, the select gate component 113 can include various circuitry to facilitate performance of select gate scan operations. As described in more detail, herein, the select gate scan operations can be performed dynamically and/or adaptively on the select gates of individual memory dice based on quality characteristics of the memory dice and/or select gates, and Fig. 2); receiving, from the memory device, a failed bit count, wherein the failed bit count is a number of bits of the memory portion with threshold voltages exceeding the select gate bias voltage (see paragraph [0060], herein As shown in FIG. 4, a one check fail byte scheme (a CFBYTE scheme) can be modulated such that slopes of the tail ends (e.g., the curves 443, 445, 447, and 449) of the V.sub.T distribution 441 of at least one of the select gates can be determined as part of determining when to perform select gate scan operations. As used herein, a “one check fail byte scheme” or “CFBYTE scheme” generally refers to schemes in which the number of failed bytes on cells or programmable select gates targeted at a specific level in programming the memory cells are counted to determine behavior of the cells or the programmable select gates. As an example, CFBYTE and its process can provide a method to count or check the number of fail bytes for a particular level, such that a microcontroller inside a memory device component being programmed can track the progress of the program algorithm and determine eventually the pass/fail status of the program of the memory device); determining that the failed bit count satisfies a refresh threshold (see paragraph [0072, herein at operation 663 a determination can be made as to whether a program erase count (PEC) of the memory die is greater than or equal to a normal or expected PEC count for the memory die. If the PEC count of the memory die is not greater than or equal (e.g., is less than) to the normal or expected PEC count, the flow 660 can continue as indicated by the Arabic numeral “1” on the right side of the flow diagram 660 and, at operation 681, the block erase operation can be completed. If, however, the PEC count of the memory die is greater than or equal to the normal or expected PEC count, the flow 660 can continue to operations 664, 665, and/or 666 or the flow 660 can continue to operations 668, 669, and/or 670).
Shukla does not explicitly teach performing a refresh operation on the memory portion in response to determining that the failed bit count satisfies the refresh threshold. However, Liang in the same the field of endeavor teaches performing a refresh operation on the memory portion in response to determining that the failed bit count satisfies the refresh threshold (see abstract and paragraph [0024], herein data stored in memory cells connected to a word line with a fail bit count above an error threshold (e.g., more than two bit errors per page or more than three bit errors per word line) may be refreshed by performing a read operation on the memory cells, generating corrected data for the memory cells (e.g., by generating the corrected data using ECC information associated with the data stored in the memory cells), performing a partial block erase operation on one or more word lines including the word line, and then writing the corrected data into the memory cells. In one example, the one or more word lines may include the word line with the fail bit count above the error threshold and an adjacent word line that is adjacent to the word line (e.g., a drain-side word line or a source-side word line arranged next to the word line; paragraph [0087], and Fig. 8 step 810)). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the memory system of Shukla with the teachings of Liang by performing a refresh operation on the memory portion in response to determining that the failed bit count satisfies the refresh threshold. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the performing a refresh operation on the memory portion in response to determining that the failed bit count satisfies the refresh threshold would have improved the data reliability of the memory system.
As per claim 2:
Shukla teaches that determining a select gate type for the select gate scan command; and determining the select gate bias voltage using the select gate type, wherein sending the select gate scan command includes the select gate bias voltage (see paraph [0046], herein the select gates (SG) 332 comprise a drain region (SGD) 331-1 to 331-N and can be referred to in the alternative as “upper select gates,” herein. In addition, the select gates (SG) 332 comprise a source region (SGS) 334-1 to 334-N and can be referred to in the alternative as “lower select gates, and Fig. 3).
As per claim 3:
Shukla teaches that determining a scan address for a subset of the memory portion using defectivity information for the memory portion, wherein the select gate scan command further includes the scan address and wherein the select gate scan command including the scan address causes the memory device to perform a select gate scan at a select gate bias voltage on the subset of the memory portion (see paragraph [0018], herein Because the select gates of replacement-gate NAND architectures can be programmed (e.g., can be biased to a logic HIGH or logic LOW state, or states in between), such select gates can be susceptible to shifting or “drifting” of the voltage corresponding to the state programmed to the select gates. For example, the threshold voltage (V.sub.T) distribution of the select gates of replacement-gate NAND architectures can shift or “drift” during operation of the NAND memory device).
As per claim 4:
Shukla teaches that wherein determining to perform the select gate scan on the memory portion comprises: determining a program erase cycle count for the memory portion (see paragraph [0020], herein a quantity of program-erase cycles (PEC) that memory cells of the memory die have undergone); and determining that the program erase cycle count satisfies a program erase cycle threshold (see paragraph [0072], herein If it is determined that the memory die was fabricated within a center area 791 of the wafer 790, at operation 663 a determination can be made as to whether a program erase count (PEC) of the memory die is greater than or equal to a normal or expected PEC count for the memory die; and paragraph [0090]).
As per claim 5:
Shukla teaches that determining the select gate bias voltage using the program erase cycle count (see paragraph [0072], herein If the PEC count of the memory die is not greater than or equal (e.g., is less than) to the normal or expected PEC count, the flow 660 can continue as indicated by the Arabic numeral “1” on the right side of the flow diagram 660 and, at operation 681, the block erase operation can be completed. If, however, the PEC count of the memory die is greater than or equal to the normal or expected PEC count, the flow 660 can continue to operations 664, 665, and/or 666 or the flow 660 can continue to operations 668, 669, and/or 670).
As per claim 6:
Shukla teaches that determining that a scan time for the memory portion satisfies a scan time threshold (see paragraph [0072], herein If it is determined that the memory die was fabricated within a center area 791 of the wafer 790, at operation 663 a determination can be made as to whether a program erase count (PEC) of the memory die is greater than or equal to a normal or expected PEC count for the memory die; and paragraph [0090]), wherein determining the scan address is in response to determining that the scan time satisfies the scan time threshold (see paragraph [0073], at operation 667 a determination can be made as to whether a PEC of the memory die is greater than or equal to a tight PEC count for the memory die. In some embodiments, a “tight PEC count” can correspond to performance of V.sub.T scans more frequently than a PEC count that is not “tight.” Accordingly, in some embodiments, a “tight PEC count” can translates to a higher frequency of SG scan operation performance, which can allow for a tail of a V.sub.T distribution to be accurately or carefully monitored. If the PEC count of the memory die is not greater than or equal (e.g., is less than) to the tight PEC count, the flow 660 can continue to operation 681, and the block erase operation can be completed. If, however, the PEC count of the memory die is greater than or equal to the tight PEC count, the flow 660 can continue to operations 664, 665, and/or 666 or the flow 660 can continue to operations 668, 669, and/or 670).
As per claim 7:
Shukla teaches that sending, in response to performing the refresh operation, a second select gate scan command to the memory device to cause the memory device to perform a second select gate scan on the memory portion; receiving, from the memory device, a second failed bit count; determining that the second failed bit count satisfies the refresh threshold (see paragraph [0019], herein perform such select gate scan operations on all of the select gates of an entire memory die or of all the memory dice of a memory device or memory sub-system without regard for characteristics of the memory dice. While such approaches can correct the effects of charge loss, charge gain, and/or other voltage drift phenomenon experienced by programmable select gates over time, at due to the static nature of select gate scan operations in such approaches, variations across all the memory dice and/or memory blocks of a memory device or memory sub-system may not effectively be captured. By failing to account for these and other real-life characteristics of memory dice, such approaches can lead to the need for deep error recovery flows to be invoked in order to correct the effects of charge loss, charge gain, and/or other voltage drift phenomenon experienced by programmable select gates over time); and retiring the memory portion in response to determining that the second failed bit count satisfies the refresh threshold (see paragraph [0066], herein a “read level” generally refers to a specific voltage level that is applied to cells and/or programmable select gates to retrieve information associated with the cells and/or programmable select gates).
As per claim 8:
Shukla teaches that sending a second select gate scan command including a second select gate bias voltage to the memory device to cause the memory device to perform a second select gate scan at the second select gate bias voltage on a second memory portion of the memory device; receiving, from the memory device, a second failed bit count, wherein the second failed bit count is a number of bits of the second memory portion with threshold voltages exceeding the second select gate bias voltage (see paragraph [0019], herein perform such select gate scan operations on all of the select gates of an entire memory die or of all the memory dice of a memory device or memory sub-system without regard for characteristics of the memory dice. While such approaches can correct the effects of charge loss, charge gain, and/or other voltage drift phenomenon experienced by programmable select gates over time, at due to the static nature of select gate scan operations in such approaches, variations across all the memory dice and/or memory blocks of a memory device or memory sub-system may not effectively be captured. By failing to account for these and other real-life characteristics of memory dice, such approaches can lead to the need for deep error recovery flows to be invoked in order to correct the effects of charge loss, charge gain, and/or other voltage drift phenomenon experienced by programmable select gates over time); determining that the second failed bit count satisfies a reallocation threshold; and reallocating data stored in the second memory portion in response to the failed bit count satisfying the reallocation threshold (see paragraph [0066], herein a “read level” generally refers to a specific voltage level that is applied to cells and/or programmable select gates to retrieve information associated with the cells and/or programmable select gates, and paragraphs [0071]-[0073]).
As per claim 9:
Shukla substantially teaches or discloses a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: send a select gate scan command to a memory device to cause the memory device to perform a select gate scan at a select gate bias voltage on a memory portion of the memory device (see abstract, paragraph [0040], herein the memory sub-system 110 can include a select gate scan component 113. Although not shown in FIG. 1 so as to not obfuscate the drawings, the select gate component 113 can include various circuitry to facilitate performance of select gate scan operations. As described in more detail, herein, the select gate scan operations can be performed dynamically and/or adaptively on the select gates of individual memory dice based on quality characteristics of the memory dice and/or select gates, and Fig. 2); receive, from the memory device, a failed bit count, wherein the failed bit count is a number of bits of the memory portion with threshold voltages exceeding the select gate bias voltage (see paragraph [0060], herein As shown in FIG. 4, a one check fail byte scheme (a CFBYTE scheme) can be modulated such that slopes of the tail ends (e.g., the curves 443, 445, 447, and 449) of the V.sub.T distribution 441 of at least one of the select gates can be determined as part of determining when to perform select gate scan operations. As used herein, a “one check fail byte scheme” or “CFBYTE scheme” generally refers to schemes in which the number of failed bytes on cells or programmable select gates targeted at a specific level in programming the memory cells are counted to determine behavior of the cells or the programmable select gates. As an example, CFBYTE and its process can provide a method to count or check the number of fail bytes for a particular level, such that a microcontroller inside a memory device component being programmed can track the progress of the program algorithm and determine eventually the pass/fail status of the program of the memory device); determine that the failed bit count satisfies a refresh threshold (see paragraph [0072, herein at operation 663 a determination can be made as to whether a program erase count (PEC) of the memory die is greater than or equal to a normal or expected PEC count for the memory die. If the PEC count of the memory die is not greater than or equal (e.g., is less than) to the normal or expected PEC count, the flow 660 can continue as indicated by the Arabic numeral “1” on the right side of the flow diagram 660 and, at operation 681, the block erase operation can be completed. If, however, the PEC count of the memory die is greater than or equal to the normal or expected PEC count, the flow 660 can continue to operations 664, 665, and/or 666 or the flow 660 can continue to operations 668, 669, and/or 670).
Shukla does not explicitly teach perform a refresh operation on the memory portion in response to determining that the failed bit count satisfies the refresh threshold. However, Liang in the same the field of endeavor teaches perform a refresh operation on the memory portion in response to determining that the failed bit count satisfies the refresh threshold (see abstract and paragraph [0024], herein data stored in memory cells connected to a word line with a fail bit count above an error threshold (e.g., more than two bit errors per page or more than three bit errors per word line) may be refreshed by performing a read operation on the memory cells, generating corrected data for the memory cells (e.g., by generating the corrected data using ECC information associated with the data stored in the memory cells), performing a partial block erase operation on one or more word lines including the word line, and then writing the corrected data into the memory cells. In one example, the one or more word lines may include the word line with the fail bit count above the error threshold and an adjacent word line that is adjacent to the word line (e.g., a drain-side word line or a source-side word line arranged next to the word line; paragraph [0087], and Fig. 8 step 810)). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the memory system of Shukla with the teachings of Liang by performing a refresh operation on the memory portion in response to determining that the failed bit count satisfies the refresh threshold. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the performing a refresh operation on the memory portion in response to determining that the failed bit count satisfies the refresh threshold would have improved the data reliability of the memory system.
As per claim 10:
Shukla teaches that wherein the processing device is further to: determine a select gate type for the select gate scan command; and determine the select gate bias voltage using the select gate type, wherein sending the select gate scan command includes the select gate bias voltage (see paraph [0046], herein the select gates (SG) 332 comprise a drain region (SGD) 331-1 to 331-N and can be referred to in the alternative as “upper select gates,” herein. In addition, the select gates (SG) 332 comprise a source region (SGS) 334-1 to 334-N and can be referred to in the alternative as “lower select gates, and Fig. 3).
As per claim 11:
Shukla teaches that wherein the processing device is further to: determine a scan address for a subset of the memory portion using defectivity information for the memory portion, wherein the select gate scan command further includes the scan address and wherein the select gate scan command including the scan address causes the memory device to perform a select gate scan at a select gate bias voltage on the subset of the memory portion (see paragraph [0018], herein Because the select gates of replacement-gate NAND architectures can be programmed (e.g., can be biased to a logic HIGH or logic LOW state, or states in between), such select gates can be susceptible to shifting or “drifting” of the voltage corresponding to the state programmed to the select gates. For example, the threshold voltage (V.sub.T) distribution of the select gates of replacement-gate NAND architectures can shift or “drift” during operation of the NAND memory device).
As per claim 12:
Shukla teaches that wherein determining to perform the select gate scan on the memory portion comprises: determine a program erase cycle count for the memory portion; and determine that the program erase cycle count satisfies a program erase cycle threshold (see paragraph [0020], herein a quantity of program-erase cycles (PEC) that memory cells of the memory die have undergone); and determining that the program erase cycle count satisfies a program erase cycle threshold (see paragraph [0072], herein If it is determined that the memory die was fabricated within a center area 791 of the wafer 790, at operation 663 a determination can be made as to whether a program erase count (PEC) of the memory die is greater than or equal to a normal or expected PEC count for the memory die; and paragraph [0090]).
As per claim 13:
Shukla teaches that wherein the processing device is further to: determine the select gate bias voltage using the program erase cycle count (see paragraph [0072], herein If the PEC count of the memory die is not greater than or equal (e.g., is less than) to the normal or expected PEC count, the flow 660 can continue as indicated by the Arabic numeral “1” on the right side of the flow diagram 660 and, at operation 681, the block erase operation can be completed. If, however, the PEC count of the memory die is greater than or equal to the normal or expected PEC count, the flow 660 can continue to operations 664, 665, and/or 666 or the flow 660 can continue to operations 668, 669, and/or 670).
As per claim 14:
Shukla teaches that wherein the processing device is further to: determine that a scan time for the memory portion satisfies a scan time threshold (see paragraph [0072], herein If it is determined that the memory die was fabricated within a center area 791 of the wafer 790, at operation 663 a determination can be made as to whether a program erase count (PEC) of the memory die is greater than or equal to a normal or expected PEC count for the memory die; and paragraph [0090]), wherein determining the scan address is in response to determining that the scan time satisfies the scan time threshold (see paragraph [0073], at operation 667 a determination can be made as to whether a PEC of the memory die is greater than or equal to a tight PEC count for the memory die. In some embodiments, a “tight PEC count” can correspond to performance of V.sub.T scans more frequently than a PEC count that is not “tight.” Accordingly, in some embodiments, a “tight PEC count” can translates to a higher frequency of SG scan operation performance, which can allow for a tail of a V.sub.T distribution to be accurately or carefully monitored. If the PEC count of the memory die is not greater than or equal (e.g., is less than) to the tight PEC count, the flow 660 can continue to operation 681, and the block erase operation can be completed. If, however, the PEC count of the memory die is greater than or equal to the tight PEC count, the flow 660 can continue to operations 664, 665, and/or 666 or the flow 660 can continue to operations 668, 669, and/or 670).
As per claim 15:
Shukla teaches that wherein the processing device is further to: send, in response to performing the refresh operation, a second select gate scan command to the memory device to cause the memory device to perform a second select gate scan on the memory portion; receive, from the memory device, a second failed bit count; determine that the second failed bit count satisfies the refresh threshold (see paragraph [0019], herein perform such select gate scan operations on all of the select gates of an entire memory die or of all the memory dice of a memory device or memory sub-system without regard for characteristics of the memory dice. While such approaches can correct the effects of charge loss, charge gain, and/or other voltage drift phenomenon experienced by programmable select gates over time, at due to the static nature of select gate scan operations in such approaches, variations across all the memory dice and/or memory blocks of a memory device or memory sub-system may not effectively be captured. By failing to account for these and other real-life characteristics of memory dice, such approaches can lead to the need for deep error recovery flows to be invoked in order to correct the effects of charge loss, charge gain, and/or other voltage drift phenomenon experienced by programmable select gates over time); and retire the memory portion in response to determining that the second failed bit count satisfies the refresh threshold (see paragraph [0066], herein a “read level” generally refers to a specific voltage level that is applied to cells and/or programmable select gates to retrieve information associated with the cells and/or programmable select gates).
As per claim 16:
Shukla teaches that wherein the processing device is further to: send a second select gate scan command including a second select gate bias voltage to the memory device to cause the memory device to perform a second select gate scan at the second select gate bias voltage on a second memory portion of the memory device; receive, from the memory device, a second failed bit count, wherein the second failed bit count is a number of bits of the second memory portion with threshold voltages exceeding the second select gate bias voltage (see paragraph [0019], herein perform such select gate scan operations on all of the select gates of an entire memory die or of all the memory dice of a memory device or memory sub-system without regard for characteristics of the memory dice. While such approaches can correct the effects of charge loss, charge gain, and/or other voltage drift phenomenon experienced by programmable select gates over time, at due to the static nature of select gate scan operations in such approaches, variations across all the memory dice and/or memory blocks of a memory device or memory sub-system may not effectively be captured. By failing to account for these and other real-life characteristics of memory dice, such approaches can lead to the need for deep error recovery flows to be invoked in order to correct the effects of charge loss, charge gain, and/or other voltage drift phenomenon experienced by programmable select gates over time); determine that the second failed bit count satisfies a reallocation threshold; and reallocate data stored in the second memory portion in response to the failed bit count satisfying the reallocation threshold (see paragraph [0066], herein a “read level” generally refers to a specific voltage level that is applied to cells and/or programmable select gates to retrieve information associated with the cells and/or programmable select gates, and paragraphs [0071]-[0073]).
As per claim 17:
Shukla substantially teaches or discloses a system comprising: a plurality of memory devices; and a processing device, operatively coupled with the plurality of memory devices, to: determine a select gate type for a select gate scan command; determine a select gate bias voltage using the select gate type (see paraph [0046], herein the select gates (SG) 332 comprise a drain region (SGD) 331-1 to 331-N and can be referred to in the alternative as “upper select gates,” herein. In addition, the select gates (SG) 332 comprise a source region (SGS) 334-1 to 334-N and can be referred to in the alternative as “lower select gates, and Fig. 3); send the select gate scan command including the select gate bias voltage to a memory device to cause the memory device to perform a select gate scan at the select gate bias voltage on a memory portion of the memory device (see abstract, paragraph [0040], herein the memory sub-system 110 can include a select gate scan component 113. Although not shown in FIG. 1 so as to not obfuscate the drawings, the select gate component 113 can include various circuitry to facilitate performance of select gate scan operations. As described in more detail, herein, the select gate scan operations can be performed dynamically and/or adaptively on the select gates of individual memory dice based on quality characteristics of the memory dice and/or select gates, and Fig. 2); receive, from the memory device, a failed bit count, wherein the failed bit count is a number of bits of the memory portion with threshold voltages exceeding the select gate bias voltage (see paragraph [0060], herein As shown in FIG. 4, a one check fail byte scheme (a CFBYTE scheme) can be modulated such that slopes of the tail ends (e.g., the curves 443, 445, 447, and 449) of the V.sub.T distribution 441 of at least one of the select gates can be determined as part of determining when to perform select gate scan operations. As used herein, a “one check fail byte scheme” or “CFBYTE scheme” generally refers to schemes in which the number of failed bytes on cells or programmable select gates targeted at a specific level in programming the memory cells are counted to determine behavior of the cells or the programmable select gates. As an example, CFBYTE and its process can provide a method to count or check the number of fail bytes for a particular level, such that a microcontroller inside a memory device component being programmed can track the progress of the program algorithm and determine eventually the pass/fail status of the program of the memory device); determine that the failed bit count satisfies a refresh threshold (see paragraph [0072, herein at operation 663 a determination can be made as to whether a program erase count (PEC) of the memory die is greater than or equal to a normal or expected PEC count for the memory die. If the PEC count of the memory die is not greater than or equal (e.g., is less than) to the normal or expected PEC count, the flow 660 can continue as indicated by the Arabic numeral “1” on the right side of the flow diagram 660 and, at operation 681, the block erase operation can be completed. If, however, the PEC count of the memory die is greater than or equal to the normal or expected PEC count, the flow 660 can continue to operations 664, 665, and/or 666 or the flow 660 can continue to operations 668, 669, and/or 670).
Shukla does not explicitly teach perform a refresh operation on the memory portion in response to determining that the failed bit count satisfies the refresh threshold. However, Liang in the same the field of endeavor teaches perform a refresh operation on the memory portion in response to determining that the failed bit count satisfies the refresh threshold (see abstract and paragraph [0024], herein data stored in memory cells connected to a word line with a fail bit count above an error threshold (e.g., more than two bit errors per page or more than three bit errors per word line) may be refreshed by performing a read operation on the memory cells, generating corrected data for the memory cells (e.g., by generating the corrected data using ECC information associated with the data stored in the memory cells), performing a partial block erase operation on one or more word lines including the word line, and then writing the corrected data into the memory cells. In one example, the one or more word lines may include the word line with the fail bit count above the error threshold and an adjacent word line that is adjacent to the word line (e.g., a drain-side word line or a source-side word line arranged next to the word line; paragraph [0087], and Fig. 8 step 810)). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the memory system of Shukla with the teachings of Liang by performing a refresh operation on the memory portion in response to determining that the failed bit count satisfies the refresh threshold. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the performing a refresh operation on the memory portion in response to determining that the failed bit count satisfies the refresh threshold would have improved the data reliability of the memory system.
As per claim 18:
Shukla teaches that wherein the processing device is further to: determine a scan address for a subset of the memory portion using defectivity information for the memory portion, wherein the select gate scan command further includes the scan address and wherein the select gate scan command including the scan address causes the memory device to perform a select gate scan at a select gate bias voltage on the subset of the memory portion (see paragraph [0018], herein Because the select gates of replacement-gate NAND architectures can be programmed (e.g., can be biased to a logic HIGH or logic LOW state, or states in between), such select gates can be susceptible to shifting or “drifting” of the voltage corresponding to the state programmed to the select gates. For example, the threshold voltage (V.sub.T) distribution of the select gates of replacement-gate NAND architectures can shift or “drift” during operation of the NAND memory device); and determine that a scan time for the memory portion satisfies a scan time threshold (see paragraph [0072], herein If it is determined that the memory die was fabricated within a center area 791 of the wafer 790, at operation 663 a determination can be made as to whether a program erase count (PEC) of the memory die is greater than or equal to a normal or expected PEC count for the memory die; and paragraph [0090]), wherein determining the scan address is in response to determining that the scan time satisfies the scan time threshold (see paragraph [0073], at operation 667 a determination can be made as to whether a PEC of the memory die is greater than or equal to a tight PEC count for the memory die. In some embodiments, a “tight PEC count” can correspond to performance of V.sub.T scans more frequently than a PEC count that is not “tight.” Accordingly, in some embodiments, a “tight PEC count” can translates to a higher frequency of SG scan operation performance, which can allow for a tail of a V.sub.T distribution to be accurately or carefully monitored. If the PEC count of the memory die is not greater than or equal (e.g., is less than) to the tight PEC count, the flow 660 can continue to operation 681, and the block erase operation can be completed. If, however, the PEC count of the memory die is greater than or equal to the tight PEC count, the flow 660 can continue to operations 664, 665, and/or 666 or the flow 660 can continue to operations 668, 669, and/or 670).
As per claim 19:
Shukla teaches that wherein determining to perform the select gate scan on the memory portion comprises: determine a program erase cycle count for the memory portion (see paragraph [0020], herein a quantity of program-erase cycles (PEC) that memory cells of the memory die have undergone); and determining that the program erase cycle count satisfies a program erase cycle threshold (see paragraph [0072], herein If it is determined that the memory die was fabricated within a center area 791 of the wafer 790, at operation 663 a determination can be made as to whether a program erase count (PEC) of the memory die is greater than or equal to a normal or expected PEC count for the memory die; and paragraph [0090]); and determine that the program erase cycle count satisfies a program erase cycle threshold and wherein the processing device is further to determine the select gate bias voltage using the program erase cycle count (see paragraph [0072], herein If the PEC count of the memory die is not greater than or equal (e.g., is less than) to the normal or expected PEC count, the flow 660 can continue as indicated by the Arabic numeral “1” on the right side of the flow diagram 660 and, at operation 681, the block erase operation can be completed. If, however, the PEC count of the memory die is greater than or equal to the normal or expected PEC count, the flow 660 can continue to operations 664, 665, and/or 666 or the flow 660 can continue to operations 668, 669, and/or 670).
As per claim 20:
Shukla teaches that wherein the processing device is further to: send, in response to performing the refresh operation, a second select gate scan command to the memory device to cause the memory device to perform a second select gate scan on the memory portion; receive, from the memory device, a second failed bit count; determine that the second failed bit count satisfies the refresh threshold (see paragraph [0019], herein perform such select gate scan operations on all of the select gates of an entire memory die or of all the memory dice of a memory device or memory sub-system without regard for characteristics of the memory dice. While such approaches can correct the effects of charge loss, charge gain, and/or other voltage drift phenomenon experienced by programmable select gates over time, at due to the static nature of select gate scan operations in such approaches, variations across all the memory dice and/or memory blocks of a memory device or memory sub-system may not effectively be captured. By failing to account for these and other real-life characteristics of memory dice, such approaches can lead to the need for deep error recovery flows to be invoked in order to correct the effects of charge loss, charge gain, and/or other voltage drift phenomenon experienced by programmable select gates over time); and retire the memory portion in response to determining that the second failed bit count satisfies the refresh threshold (see paragraph [0066], herein a “read level” generally refers to a specific voltage level that is applied to cells and/or programmable select gates to retrieve information associated with the cells and/or programmable select gates).
Examiner Notes
8. When amending the claims, applicants are respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Prior Art
8. The prior art of record, considered pertinent to the applicant’s disclosure, is listed in the attached PTO-892 form.
Conclusion
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to OSMAN ALSHACK whose telephone number is (571)272-2069. The examiner can normally be reached on MON-FRI 8:30 AM-5:00 PM EST, also please fax interview request to (571) 273- 2069. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ALBERT DECADY can be reached on 5712723819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/OSMAN M ALSHACK/Examiner, Art Unit 2112
Prosecution Insights