DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings received on 12/17/2024 have been accepted by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Marukame et al (US20180082168).
Regarding claim 1, Marukame discloses a capacitive synaptic component(FIG 8; [0036-0037 & 0057] discloses a neuron device comprising capacitance component 11), comprising: a semiconductor layer having an adjustable capacitance to be caused by an electrical charge[FIG 8; [0054-0056]11 comprising a semiconductor layer comprising 15 that is adjustable by an electrical charge) ; a gate electrode disposed on the semiconductor layer(121); and a dielectric layer disposed between the gate electrode and the semiconductor layer(123 124 between 121 and 15), wherein the semiconductor layer comprises a first doped zone and a second doped zone and further comprises one or more contacts to charge or discharge the semiconductor layer (FIG 8; [0055-0056] discloses 14 that does not change its electrostatic capacitance with respect to writing e.g., discharging and 15 that changes its electrostatic capacitance with writing e.g., charged e.g., upper and lower surface).
Regarding claim 2, Marukame discloses wherein the semiconductor layer comprises a plurality of contacts, a first contact of the plurality of contacts to allow inflow the electrical charge and a second contact of the plurality of contacts to allow outflow of the electrical charge (FIG 8-9; input contacts e.g., gates and readout contacts e.g., 125 inputs 151/152 and output readout connected to 125 connected).
Regarding claim 3, Marukame discloses wherein during readout of the capacitive synaptic component the one or more contacts is to be coupled to ground (FIG 8-9; readout connected to output Vss).
Regarding claim 4, Marukame discloses wherein the dielectric layer and/or the semiconductor layer are/is configured as an active storage medium (FIG 8-9; 123 storage element).
Regarding claim 5, Marukame discloses herein the dielectric layer is an active storage medium to store different charge states (FIG 8-9; [0046] discloses ferroelectric memory and phase change storing therein data of two or more values).
Regarding claim 6, Marukame discloses wherein the dielectric layer comprises a ferroelectric material (FIG 8-9; [0046] discloses ferroelectric memory and phase change).
Regarding claim 7, Marukame discloses wherein the dielectric layer comprises charge traps (FIG 8; [0053] 124 charge accumulating unit e.g., charge traps).
Regarding claim 8, Marukame discloses wherein readout of the capacitive synaptic component is performed through the semiconductor layer (FIG 8; 125).
Regarding claim 9, Marukame discloses wherein the semiconductor layer is an active storage medium to provide different resistance values and is to store a resistance value in a nonvolatile manner s (FIG 8-9; [0046 & 0054] discloses ferroelectric memory and phase change storing therein data of two or more values).
Regarding claim 10, Marukame discloses wherein the first and second doped zones are equivalent charge carrier zones (FIG 8; [0053-0055 discloses upper and lower surface e.g., charge carrier zones).
Regarding claim 11, Marukame discloses wherein the first doped zone is a p-type zone and the second doped zone is an n-type zone (FIG 7; p-type transistor bottom going out and n-type transistor tope going in).
Regarding claim 12, Marukame discloses a method to operate capacitive synaptic component, comprising: generating voltage difference between a gate electrode and a semiconductor layer(FIG 8; [0057] discloses volage difference between upper electrode 121 and lower electrode 125 of 11), the gate electrode disposed on the semiconductor layer(121), and the semiconductor layer having an adjustable capacitance and comprises a first doped zone and a second doped zone separated by a portion of the semiconductor layer (FIG 8; [0055-0056] discloses 14 that does not change its electrostatic capacitance with respect to writing e.g., discharging and 15 that changes its electrostatic capacitance with writing e.g., charged e.g., upper and lower surface) ; based on the voltage difference, accumulating an electrical charge in a dielectric layer disposed between the gate electrode and the semiconductor layer; and increasing the adjustable capacitance of the semiconductor layer to discharge the electrical charge in the dielectric layer (FIG 8, 10 & 11-13; [0057 & 0067-0068]discloses adjusting charge value based on the voltage difference e.g., electrostatic capacitance of 15 increasing).
Regarding claim 13, Marukame discloses wherein the electrical charge in the dielectric layer is discharged through the semiconductor layer based on increasing a resistance of the semiconductor layer (FIG 8; [0056-0057] variable resistance portion 122, and capacitor 15 that changes its electrostatic capacitance in according with write operation e.g., change in 122).
Regarding claim 14, Marukame discloses further comprising coupling the semiconductor layer to ground to discharge the electrical charge in the dielectric layer (FIG 7-8; 11 is grounded e.g., Vss).
Regarding claim 15, Marukame discloses further comprising depleting the semiconductor layer to discharge the electrical charge in the dielectric layer (FIG 8; [0055-0056] discloses 14 that does not change its electrostatic capacitance with respect to writing e.g., discharging and 15 that changes its electrostatic capacitance with writing e.g., charged e.g., upper and lower surface)
Regarding claim 16, Marukame discloses (FIG 8-9; [0046] discloses ferroelectric memory and phase change).
Regarding claim 17, Marukame discloses wherein the dielectric layer comprises charge traps (FIG 8; [0053] 124 charge accumulating unit e.g., charge traps).
Regarding claim 18, Marukame discloses wherein readout of the capacitive synaptic component is performed through the semiconductor layer (FIG 8; 125).
Regarding claim 19, Marukame discloses wherein the first and second doped zones are equivalent charge carrier zones (FIG 8; [0053-0055 discloses upper and lower surface e.g., charge carrier zones).
Regarding claim 20, Marukame discloses wherein the first doped zone is a p-type zone and the second doped zone is an n-type zone (FIG 7; p-type transistor bottom going out and n-type transistor tope going in).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Demasius et al (US2022059161 FIG 2-4; discloses a capacitance synaptic component having layer comprising dielectric layer, gate electrode and read output electrode connected to a second dielectric layer).
Bakalski et al (US20140104132 FIG 10; discloses capacitive network element, having adjusted charges).
Le et al (US6515903 FIG 7-8) & Ham et al (US20180268970).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUNA A TECHANE whose telephone number is (571)272-7856. The examiner can normally be reached 571-272-7856.
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/MUNA A TECHANE/Primary Examiner, Art Unit 2827
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