DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statement filed on March 18, 2026 is considered.
Response to Amendment
This Office action is in response to amendment filed 6/10/2026. Accordingly, claims 1-12 were withdrawn and claims 13-20 are pending for examination
Election/Restrictions
Applicant’s election without traverse of Group II in the reply filed on 6/10/2026 is acknowledged.
Claims 1-12 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group I, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/10/2026.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 17-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because claims 17-20 are directed to a computer program product, which the computer program product comprises one or more computer readable storage media, and program instructions collectively stored on the one or more computer readable storage media. However, the original claims and specification do not specifically define computer program product and computer readable storage media as non-transitory computer readable storage media to exclude from signals or carrier waves. Thus, claims 17-20 are directed to non-statutory subject matter.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 13-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US 2023/0087260 A1, hereinafter Park).
Regarding claim 13, Park discloses a system as shown in figure 1 comprising: a storage device (figure 1, 200); and a controller (figure 1, 210), associated with the storage device, to: receive, from a host device (figure 1, 100), a first read command that indicates a first logical address for data stored on the storage device ([0036], the packet transmitted from the host device 100 to the host interface 211 may include a command or data to be written in the non-volatile memory 220, and the packet transmitted from the host interface 211 to the host device 100 may include a response to the command or data read from the non-volatile memory 220); store the first logical address and the data on a random access memory (RAM) associated with the storage device ([0040], the buffer memory 216 may temporarily store data to be written in the non-volatile memory 220 or data to be read from the non-volatile memory 220); receive a second read command that indicates a second logical address for stored data on the storage device ([0075] and [0113], if the first tenant VM 1 reads the first tenant data stored in the first non-volatile memory region NMR 1 of the storage device 200, at this time (or in response), the host controller 110 sends the first access information Acc_Inf 1 related to the first tenant VM 1 to the storage device 200); identify a match between the first logical address and the second logical address ([0075] and [0114], when it is determined that the host memory address, the namespace identifier and the logic block address, which exist in the first access information Acc_Inf, are the same as the first host memory address HMA 1, the first namespace identifier NSID 1 and the first logic block address LBA 1, which are stored in the mapping table 219); and provide the data to the host device from the RAM based at least in part on the match ([0075] and [0115], the first tenant VM 1 may complete the read operation for the first tenant data transmitted to the first host memory region 106).
Regarding claim 14, Park discloses wherein the controller is to store the data on the RAM based at least in part on receiving the first read command, and wherein, to provide the data to the host device, the controller is to provide the data from the RAM ([0040], the buffer memory 216 may temporarily store data to be written in the non-volatile memory 220 or data to be read from the non-volatile memory 220).
Regarding claim 15, Park discloses wherein, to provide the data from the RAM, the controller is to: provide the data from the RAM without first performing, after receiving the second read command, a read operation at a physical location associated with the local address of the storage device ([0115], if the first tenant VM 1 reads the first tenant data stored in the first buffer region BR 1 of the storage device 200, the host controller 110 sends the first access information Acc_Inf 1 related to the first tenant VM 1 to the storage device 200, and afterward, when it is determined that the host memory address, the namespace identifier, the buffer address and the logic block address, which exist in the first access information Acc_Inf 1, are the same as the first host memory address HMA 1, the first namespace identifier NSID 1).
Regarding claim 16. (Original) The system of claim 13, wherein the match comprises one or more of: an identical match between the first logical address and the second logical address, or a match by the first logical address and the second logical address to one or more intermediate identifiers ([0114], the buffer address and the logic block address in the access information received from the host controller 110, compares the extracted ones with those stored in the mapping table 219).
Regarding claim 17, the limitations of the claim are rejected as the same reasons as set forth in claim 13. Park also teaches that the host controller 110 sends the first access information Acc_Inf 1 related to the first tenant VM 1 to the storage device 200 such that there is an indication of a link between the first logical address and the physical address.
Regarding claim 18, Park teaches wherein, to store the indication of the link, the program instructions comprise: program instructions to store a set of links between logical addresses and physical addresses associated with a set of one or more most-recent read commands ([0116], the host controller 110 sends the first access information Acc_Inf 1 related to the first tenant VM 1 and the first tenant data to the storage device 200. Afterwards, when it is determined that the host memory address, the namespace identifier, the buffer address and the logic block address, which exist in the first access information Acc_Inf 1, are the same as the first host memory address HMA 1, the first namespace identifier NSID 1, the first buffer address Buffer address 1 and the first logic block address LBA 1, which are stored in the mapping table 219 such that a set of links between logical addresses and physical addresses associated with a set of one or more most-recent read commands are stored).
Regarding claim 19, Park teaches that wherein, to translate the first logical address to the physical address, the program instructions comprise: program instructions to convert the first logical address to a local logical address; and program instructions to convert the local logical address to the physical address ([0037], flash translation layer 214 may perform various functions, such as address mapping to change a logical address received from the host device 100 to a physical address used to actually store data in the non-volatile memory 220).
Regarding claim 20, Park teaches wherein, to perform the read operation at the physical location of the storage device, the program instructions comprise: program instructions to perform the read operation without first performing, after receiving the second read command, a first conversion from the first logical address to a local logical address ([0124], the device security manager 215 in the storage device 200 determines that the corresponding operation is not the security attack performed from the first tenant VM 1, and approves the read operation of the first tenant VM 1 such that the storage device perform the read operation without first performing, after receiving the second read command, a first conversion from the first logical address to a local logical address).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Shimonomura (US 2025/0265005 A1) discloses a memory controller having a speculative reading mode of reading in advance data predicted to be requested by the host from a nonvolatile memory such that when determining to transition to the speculative reading mode, transition to the speculative reading mode, and read, from the nonvolatile memory, data in a range determined with respect to a physical address associated with a logical address specified by the host (abstract and [0024]).
Lin (US 2024/0111451 A1) discloses a when determining to transition to the speculative reading mode, transition to the speculative reading mode, and read, from the nonvolatile memory, data in a range determined with respect to a physical address associated with a logical address specified by the host ([0003]-[0011]).
Sallese et al. (US 2021/0278996 A10 discloses a method for performing sub-logical page write operations in a NVRAM using pre-populated buffers in a data storage system, and creating a searchable entry which includes the first LBA, and thus enables improving the performance characteristics of NAND Flash (abstract and figure 3).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHUO H LI whose telephone number is (571)272-4183. The examiner can normally be reached Mon. Tue. and Thurs. 8:00-4:00 PM.
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/ZHUO H LI/ Primary Examiner, Art Unit 2133
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