Prosecution Insights
Last updated: October 04, 2026
Application No. 18/985,112

Protection Circuit, Control Method and Photovoltaic System

Non-Final OA §103§112
Filed
Dec 18, 2024
Priority
Dec 21, 2023 — CN 202311774148.6 +1 more
Examiner
FAUBERT, SAMANTHA LYNETTE
Art Unit
Tech Center
Assignee
Shanghai Sigeyuan Intelligent Technology Co. Ltd.
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
10m
Est. Remaining
85%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
50 granted / 60 resolved
+23.3% vs TC avg
Minimal +2% lift
Without
With
+1.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
15 currently pending
Career history
70
Total Applications
across all art units

Statute-Specific Performance

§103
62.2%
+22.2% vs TC avg
§102
31.5%
-8.5% vs TC avg
§112
6.3%
-33.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 60 resolved cases

Office Action

§103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Claim Rejections - 35 USC § 112 Claim 16 recites the limitation "a controller" twice in line 4 and 16. There is insufficient antecedent basis for this limitation in the claim. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-2, 7-8, 11-12 and 14-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al., CN115664240 (hereinafter referred to as Wang), in view of Gao et al., US20230208312 (hereinafter referred to as Gao). In regards to claim 1, Wang teaches a protection circuit (circuit of Fig. 5), wherein the protection circuit is applied to a three-phase inverter circuit (inverter, implicit; [Abstract] & [Fig. 5]); a direct current (DC) side (left side terminals of Fig. 5) of the three-phase inverter circuit is configured to connect a power supply assembly (photovoltaic system; [Abstract]); and the protection circuit comprises: a controllable power device (switch tube S; [Fig. 5]) in parallel (implicit; [Fig. 5]) connection with a bridge arm (switch tube S2 and diode D2; [Fig. 5]) in the three-phase inverter circuit; a fault detection module (fault protection device; [Pg. 2, Para. 5-Pg. 3, Para. 1]) electrically connected to the three-phase inverter circuit, and configured to generate a fault signal (implicit output signal that cuts off the connection of the power conversion circuit; [Pg. 2, Para. 5-Pg. 3, Para. 1]) when detecting a short-to-ground (STG) fault (abnormal large current; [Pg. 2, Para. 5-Pg. 3, Para. 1]); a current detection circuit (current detecting device; [Pg. 2, Para. 5-Pg. 3, Para. 1]) electrically connected to the three-phase inverter circuit, and configured to detect an output current of each phase in the three-phase inverter circuit; and a controller (controller; [Fig. 5]) electrically connected to the fault detection module (notified to the controller; [Pg. 2, Para. 5-Pg. 3, Para. 1]) and the current detection circuit. Wang does not teach an output terminal of each phase in the three- phase inverter circuit is provided with a relay assembly; and a controller electrically connected to the relay assembly and configured to control the controllable power device to be on after receiving the fault signal and disconnect the relay assembly of each phase when the output current of each phase meets a zero-crossing condition. Gao teaches an output terminal of each phase (right side of K4-K6; [Fig. 14]) in the three-phase inverter circuit is provided with a relay assembly (switches K1-K6; [Fig. 14]); and the controller (controller 102; [Fig. 14]) (controller, Wang) electrically connected to the relay assembly (implicit; [Fig. 14]) and configured to control the controllable power device to be on after receiving the fault signal (short circuit fault; [0020]) and disconnect (controls the power conversion circuit to be disconnected; [0020]) the relay assembly of each phase when the output current of each phase meets a zero-crossing condition (voltage zero-crossing, Wang; [Pg. 2, Para. 5-Pg. 3, Para. 1]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Wang in order to incorporate an output terminal of each phase in the three- phase inverter circuit is provided with a relay assembly; and the controller electrically connected to the relay assembly and configured to control the controllable power device to be on after receiving the fault signal and disconnect the relay assembly of each phase when the output current of each phase meets a zero-crossing condition as taught by Gao. The motivation for doing so would be an engineering design choice to provide an isolating, overcurrent protection device for the power supply assembly. In regards to claim 2, Wang teaches wherein the bridge arm comprises an upper bridge arm (S1 & D1; [Fig. 5]) and a lower bridge arm (S2 and D2; [Fig. 5]); and the fault detection module is configured to generate a first fault signal when detecting an anode STG fault of the power supply assembly (implicit output signal that cuts off the connection of the power conversion circuit; [Pg. 2, Para. 5-Pg. 3, Para. 1]), and/or generate a second fault signal when detecting a cathode STG fault of the power supply assembly; and the controller is configured to control the controllable power device in parallel connection with the upper bridge arm to be on (the controllable switch to conduct; [Pg. 11, Para. 3]) when receiving the first fault signal, and/or control the controllable power device in parallel connection with the lower bridge arm to be on when receiving the second fault signal. In regards to claim 7, Wang does not teach wherein the relay assembly comprises a plurality of relays connected in series; and the controller is electrically connected to the plurality of relays , and configured to use at least two relay disconnecting sequences when disconnecting the relay assembly repeatedly; and the relay assembly comprises a first relay and a second relay connected in series; and the controller is configured to execute the following operations alternately: disconnecting the first relay prior to the second relay; or, disconnecting the second relay prior to the first relay. Gao teaches wherein the relay assembly comprises a plurality of relays (x2 switches; [Fig. 14]) connected in series (implicit; [Fig. 14]); and the controller is electrically connected to the plurality of relays (implicit; [Fig. 14]), and configured to use at least two relay disconnecting sequences when disconnecting the relay assembly repeatedly (control signal 21, 22, or 23; and control signal 24; [Fig. 14]); and the relay assembly comprises a first relay (K1 or K2 or K3; [Fig. 14]) and a second relay (respectively K4 or K5 or K6; [Fig. 14]) connected in series (implicit; [Fig. 14]); and the controller is configured to execute the following operations alternately: disconnecting the first relay prior to the second relay (to turn off respectively the first stage relay and the second stage relay in sequence; [0006]); or, disconnecting the second relay prior to the first relay. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Wang in order to incorporate wherein the relay assembly comprises a plurality of relays connected in series; and the controller is electrically connected to the plurality of relays , and configured to use at least two relay disconnecting sequences when disconnecting the relay assembly repeatedly; and the relay assembly comprises a first relay and a second relay connected in series; and the controller is configured to execute the following operations alternately: disconnecting the first relay prior to the second relay; or, disconnecting the second relay prior to the first relay as taught by Gao. The motivation for doing so would be to implement the required number of relays for connecting/disconnecting from the power grid. In regards to claim 8, Wang teaches wherein the controllable power device comprises silicon controlled rectifiers (SCRs) (switch tube S; [Fig. 5]) (Examiner’s Note: The broadest reasonable interpretation of an SCR would include a switch tube.) corresponding to output phases of the three-phase inverter circuit (implicit with the switch tube coupled to the input of each phase’s inductor; [Fig. 5]); each SCR is provided between an anode of the power supply assembly (input negative terminal; [Abstract] & [Fig. 5]) and the bridge arm of each phase (implicit within each phase’s box of Fig. 5); and when the anode of the power supply assembly is grounded (an abnormally large current; [Pg. 11, Para. 3]), the controllable power device is started (the controllable switch to conduct; [Pg. 11, Para. 3]), and the SCR is turned on to shunt a current (shunts; [Pg. 11, Para. 3]) from the anode of the power supply assembly to a first switching device, wherein the first switching device is between the bridge arms of the phases at an alternating current (AC) side of the three-phase inverter circuit; or each SCR is provided between a cathode of the power supply assembly and the bridge arm of each phase; and when the cathode of the power supply assembly is grounded, the controllable power device is started, and the SCR is turned on to shunt a current from the cathode of the power supply assembly to a second switching device, wherein the second switching device is between the bridge arms of the phases at the AC side of the three-phase inverter circuit. In regards to claim 11, Wang teaches a control method, wherein the control method is applied to a three-phase inverter circuit (inverter, implicit; [Abstract] & [Fig. 5]); a direct current (DC) side (left side terminals of Fig. 5) of the three-phase inverter circuit is configured to connect a power supply assembly (photovoltaic system; [Abstract]); a bridge arm (switch tube S2 and diode D2; [Fig. 5]) in the three-phase inverter circuit is in parallel (implicit; [Fig. 5]) connection with a controllable power device (switch tube S; [Fig. 5]); and the control method comprises the following steps: controlling the controllable power device to be on when a short-to-ground (STG) fault (an abnormally large current; [Pg. 11, Para. 3]) of the power supply assembly is detected; and detecting an output current of each phase (current detecting device; [Pg. 2, Para. 5-Pg. 3, Para. 1]) in the three-phase inverter circuit. Wang does not teach an output terminal of each phase in the three-phase inverter circuit is provided with a relay assembly; and is connecting the relay assembly of each phase after the controllable power device is turned on and when the output current of each phase meets a zero-crossing condition. Gao teaches an output terminal (right side of K4-K6; [Fig. 14]) of each phase in the three-phase inverter circuit is provided with a relay assembly (switches K1-K6; [Fig. 14]); and is connecting the relay assembly (controls the power conversion circuit to be disconnected; [0020]) of each phase after the controllable power device is turned on and when the output current of each phase (a current of each phase; [0018]) meets a zero-crossing condition (zero-crossing; [0018]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Wang in order to incorporate an output terminal of each phase in the three-phase inverter circuit is provided with a relay assembly; and is connecting the relay assembly of each phase after the controllable power device is turned on and when the output current of each phase meets a zero-crossing condition as taught by Gao. The motivation for doing so would be an engineering design choice to provide an isolating, overcurrent protection device for the power supply assembly. In regards to claim 12, Wang does not teach wherein the step of disconnecting the relay assembly of each phase when the output current of each phase meets a zero-crossing condition comprises: in a first stage, determining zero-crossing time when the output current of each phase in the three-phase inverter circuit crosses a zero point for a first time; and in a second stage, disconnecting the relay assembly of a corresponding phase, when each phase meets at least one of the following conditions: a time difference between present time and the zero-crossing time is less than a threshold; or, the output current is less than a fifth current threshold. Gao teaches wherein the step of disconnecting the relay assembly of each phase when the output current of each phase meets a zero-crossing condition comprises: in a first stage, determining zero-crossing time when the output current of each phase in the three-phase inverter circuit crosses a zero point for a first time (zero-crossing moment of the current; [0019]); and in a second stage, disconnecting the relay assembly of a corresponding phase (turn-off moment of the relay; [0019]), when each phase meets at least one of the following conditions: a time difference between present time and the zero-crossing time is less than a threshold (a turn-off delay time td and t1 need to be comprehensively considered; [0019]); or, the output current is less than a fifth current threshold. Therefore, wherein the step of disconnecting the relay assembly of each phase when the output current of each phase meets a zero-crossing condition comprises: in a first stage, determining zero-crossing time when the output current of each phase in the three-phase inverter circuit crosses a zero point for a first time; and in a second stage, disconnecting the relay assembly of a corresponding phase, when each phase meets at least one of the following conditions: a time difference between present time and the zero-crossing time is less than a threshold; or, the output current is less than a fifth current threshold. The motivation for doing so would be to improve the zero-crossing design for safely disconnecting the phase currents. In regards to claim 14, Wang teaches wherein the bridge arm of the three-phase inverter circuit comprises an upper bridge arm (S1 & D1; [Fig. 5]); and the step of controlling the controllable power device to be on when detecting the STG fault comprises: when detecting that a negative output current of at least one phase in the three-phase inverter circuit is greater than a first current threshold (abnormal large current; [Pg. 2, Para. 5-Pg. 3, Para. 1]), and/or a negative common-mode current at the DC side of the three-phase inverter circuit is greater than a third current threshold, and/or a voltage- to-ground between an anode of the power supply assembly and a ground node is less than a first voltage threshold, determining an anode STG fault of the power supply assembly (implicit fault that cuts off the connection of the power conversion circuit; [Pg. 2, Para. 5-Pg. 3, Para. 1]); and when the anode STG fault of the power supply assembly occurs, controlling the controllable power device in parallel connection with the upper bridge arm to be on (the controllable switch to conduct; [Pg. 11, Para. 3]). In regards to claim 15, Wang teaches wherein the bridge arm of the three-phase inverter circuit comprises a lower bridge arm (S2 and D2; [Fig. 5]); and the step of controlling the controllable power device to be on (the controllable switch to conduct; [Pg. 11, Para. 3]) when detecting the STG fault comprises: when detecting that a positive output current of at least one phase in the three-phase inverter circuit is greater than a second current threshold (abnormal large current; [Pg. 2, Para. 5-Pg. 3, Para. 1]), and/or a positive common-mode current at the DC side of the three-phase inverter circuit is greater than a fourth current threshold, and/or a voltage-to-ground between a cathode of the power supply assembly and a ground node is less than a second voltage threshold, determining a cathode STG fault of the power supply assembly (implicit fault that cuts off the connection of the power conversion circuit; [Pg. 2, Para. 5-Pg. 3, Para. 1]); and when the cathode STG fault of the power supply assembly occurs, controlling the controllable power device in parallel connection with the lower bridge arm to be on (the controllable switch to conduct; [Pg. 11, Para. 3]). In regards to claim 16, Wang teaches a photovoltaic system (photovoltaic system; [Abstract]), comprising a power supply assembly (boost circuit; [Fig. 12]) and an inverter (inverter; [Abstract] & [Fig. 5]), wherein the inverter comprises a direct current (DC) side (left side terminals of Fig. 5) configured to connect the power supply assembly (implicit; [Fig. 12]), and an alternating current (AC) side configured to connect a power grid (right side AC voltage; [Fig. 12]); and the inverter comprises a protection circuit, or a controller (controller; [Fig. 5]) for realizing a control method; wherein the protection circuit is applied to a three-phase inverter circuit (implicit; [Fig. 12]); a DC side of the three-phase inverter circuit is configured to connect a power supply assembly (implicit; [Fig. 12]); and the protection circuit comprises: a controllable power device (switch tube S; [Fig. 5]) in parallel (implicit; [Fig. 5]) connection with a bridge arm (switch tube S2 and diode D2; [Fig. 5]) in the three-phase inverter circuit; a fault detection module (fault protection device; [Pg. 2, Para. 5-Pg. 3, Para. 1]) electrically connected to the three-phase inverter circuit, and configured to generate a fault signal (implicit output signal that cuts off the connection of the power conversion circuit; [Pg. 2, Para. 5-Pg. 3, Para. 1]) when detecting a short-to-ground (STG) fault (abnormal large current; [Pg. 2, Para. 5-Pg. 3, Para. 1]); a current detection circuit (current detecting device; [Pg. 2, Para. 5-Pg. 3, Para. 1]) electrically connected to the three-phase inverter circuit, and configured to detect an output current of each phase in the three-phase inverter circuit; and a controller (controller; [Fig. 5]) electrically connected to the fault detection module (notified to the controller; [Pg. 2, Para. 5-Pg. 3, Para. 1]), the control method is applied to the three-phase inverter circuit; and the control method comprises the following steps: controlling the controllable power device to be on (the controllable switch to conduct; [Pg. 11, Para. 3]) when the STG fault (an abnormally large current; [Pg. 11, Para. 3]) of the power supply assembly is detected. Wang does not teach an output terminal of each phase in the three-phase inverter circuit is provided with a relay assembly; and the current detection circuit and the relay assembly, and configured to control the controllable power device to be on after receiving the fault signal and disconnect the relay assembly of each phase when the output current of each phase meets a zero-crossing condition; and detecting the output current of each phase in the three-phase inverter circuit; and is connecting the relay assembly of each phase after the controllable power device is turned on and when the output current of each phase meets a zero-crossing condition. Gao teaches an output terminal (right side of K4-K6; [Fig. 14]) of each phase in the three-phase inverter circuit is provided with a relay assembly (switches K1-K6; [Fig. 14]); and the current detection circuit and the relay assembly, and configured to control the controllable power device to be on after receiving the fault signal and disconnect the relay assembly of each phase (controls the power conversion circuit to be disconnected; [0020]) when the output current of each phase meets a zero-crossing condition (zero-crossing; [0018]); and detecting the output current (a current of each phase; [0018]) of each phase in the three-phase inverter circuit; and is connecting the relay assembly of each phase after the controllable power device is turned on and when the output current of each phase meets a zero-crossing condition. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Wang in order to incorporate an output terminal of each phase in the three-phase inverter circuit is provided with a relay assembly; and the current detection circuit and the relay assembly, and configured to control the controllable power device to be on after receiving the fault signal and disconnect the relay assembly of each phase when the output current of each phase meets a zero-crossing condition; and detecting the output current of each phase in the three-phase inverter circuit; and is connecting the relay assembly of each phase after the controllable power device is turned on and when the output current of each phase meets a zero-crossing condition. In regards to claim 17, Wang does not teach wherein the relay assembly comprises a plurality of relays connected in series; and the controller is electrically connected to the plurality of relays, and configured to use at least two relay disconnecting sequences when disconnecting the relay assembly repeatedly; and the relay assembly comprises a first relay and a second relay connected in series; and the controller is configured to execute the following operations alternately: disconnecting the first relay prior to the second relay; or, disconnecting the second relay prior to the first relay. Gao teaches wherein the relay assembly comprises a plurality of relays (x2 switches; [Fig. 14]) connected in series (implicit; [Fig. 14]); and the controller is electrically connected to the plurality of relays (implicit; [Fig. 14]), and configured to use at least two relay disconnecting sequences when disconnecting the relay assembly repeatedly (control signal 21, 22, or 23; and control signal 24; [Fig. 14]); and the relay assembly comprises a first relay (K1 or K2 or K3; [Fig. 14]) and a second relay (respectively K4 or K5 or K6; [Fig. 14]) connected in series (implicit; [Fig. 14]); and the controller is configured to execute the following operations alternately: disconnecting the first relay prior to the second relay (to turn off respectively the first stage relay and the second stage relay in sequence; [0006]); or, disconnecting the second relay prior to the first relay. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Wang in order to incorporate wherein the relay assembly comprises a plurality of relays connected in series; and the controller is electrically connected to the plurality of relays, and configured to use at least two relay disconnecting sequences when disconnecting the relay assembly repeatedly; and the relay assembly comprises a first relay and a second relay connected in series; and the controller is configured to execute the following operations alternately: disconnecting the first relay prior to the second relay; or, disconnecting the second relay prior to the first relay. Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al., CN115664240 (hereinafter referred to as Wang), in view of Gao et al., US20230208312 (hereinafter referred to as Gao), and in further view of Yin et al., US20100088052 (hereinafter referred to as Yin). In regards to claim 13, Wang teaches wherein the three-phase inverter circuit uses a three-phase four-wire system (Phases A, B, C and ground; [Fig. 2]), and in the second stage, disconnecting the relay assembly of the corresponding phase, when each phase meets at least one of the following conditions: the time difference between the present time and the zero-crossing time is less than the threshold (a turn-off delay time td and t1 need to be comprehensively considered; [0019]); the output current is less than the fifth current threshold; or, the angle of the phase voltage falls within a target angle range, wherein when an anode STG fault occurs, the target angle range is [1800, 180+010]; and when a cathode STG fault occurs, the target angle range is [00, 020], 01 being a first angle threshold, and 02 being a second angle threshold. Wang & Gao do not teach the control method further comprises: acquiring an angle of each phase voltage. Yin teaches the control method further comprises: acquiring an angle of each phase voltage (measure the phase angle between the AC voltage; [0031]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Wang & Gao in order to incorporate the control method further comprises: acquiring an angle of each phase voltage as taught by Yin. The motivation for doing so would be to determine the status of the AC relays (Yin, [0032]). Allowable Subject Matter Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 3 is indicated containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 1, especially “wherein the fault detection module comprises: an overcurrent detection module electrically connected to the current detection circuit, and configured to generate a first overcurrent signal when a negative output current of at least one phase is greater than a first current threshold, and/or generate a second overcurrent signal when a positive output current of at least one phase is greater than a second current threshold; a common-mode current detection module electrically connected to the DC side of the three-phase inverter circuit, and configured to generate a first common-mode current signal when a negative common-mode current at the DC side of the three-phase inverter circuit is greater than a third current threshold, and/or generate a second common-mode current signal when a positive common-mode current at the DC side of the three-phase inverter circuit is greater than a fourth current threshold; a voltage detection module electrically connected to an anode of the power supply assembly, a cathode of the power supply assembly and a ground node, and configured to generate a first voltage-to-ground signal when a voltage-to-ground between the anode of the power supply assembly and the ground node is less than a first voltage threshold, and/or generate a second voltage-to-ground signal when a voltage-to-ground between the cathode of the power supply assembly and the ground node is less than a second voltage threshold; and a signal conversion module electrically connected to the overcurrent detection module, the common-mode current detection module and the voltage detection module, and configured to generate the first fault signal when receiving at least one of the first overcurrent signal, the first common-mode current signal and the first voltage-to-ground signal; and/or the signal conversion module is configured to generate the second fault signal when receiving at least one of the second overcurrent signal, the second common-mode current signal and the second voltage-to-ground signal.” Claims 4-6, 9-10, and 18-20 would be allowed based on dependence of claim 3. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMANTHA L FAUBERT whose telephone number is (703)756-1311. The examiner can normally be reached Monday - Friday 8AM - 5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal Hammond can be reached at 5712701682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. SAMANTHA LYNETTE FAUBERT Examiner Art Unit 2836 /CRYSTAL L HAMMOND/Supervisory Primary Examiner, Art Unit 2838
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Prosecution Timeline

Dec 18, 2024
Application Filed
Aug 07, 2026
Non-Final Rejection mailed — §103, §112
Sep 14, 2026
Applicant Interview (Telephonic)
Sep 14, 2026
Examiner Interview Summary

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