Prosecution Insights
Last updated: August 18, 2026
Application No. 18/985,174

ADAPTIVE CASCODE GATE BIAS GENERATION CIRCUIT

Final Rejection §102§103
Filed
Dec 18, 2024
Examiner
SKIBINSKI, TOMI SWEET
Art Unit
2836
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Avago Technologies International Sales Pte. Limited
OA Round
2 (Final)
84%
Grant Probability
Favorable
3-4
OA Rounds
1m
Est. Remaining
87%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
737 granted / 881 resolved
+15.7% vs TC avg
Minimal +3% lift
Without
With
+3.2%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 9m
Avg Prosecution
17 currently pending
Career history
896
Total Applications
across all art units

Statute-Specific Performance

§101
1.5%
-38.5% vs TC avg
§103
53.4%
+13.4% vs TC avg
§102
26.6%
-13.4% vs TC avg
§112
17.4%
-22.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 881 resolved cases

Office Action

§102 §103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 2, and 4-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoshimasu et al (US PGPUB 2020/0036340). Regarding claim 1, Figure 7 of Yoshimasu discloses a circuit comprising: a first resistor [R13] between a voltage rail [V_bias] and a drive interconnect [node between R13 and R12], the drive interconnect and the voltage rail being electrically connected to the first resistor [R13] a second resistor between the drive interconnect and ground, ground and the drive interconnect being electrically connected to the second resistor [R12] a current source between the voltage rail and the drive interconnect, the drive interconnect and the voltage rail being electrically connected to the current source [R13] a transistor between the drive interconnect and a sink interconnect, the drive interconnect and the sink interconnect being electrically connected to the transistor [TR3] Regarding claim 2, Figure 7 of Yoshimasu discloses a current sink between the sink interconnect and ground, ground and the sink interconnect being electrically connected to the current sink [TR1 and TR2]. Regarding claim 4, Figure 7 of Yoshimasu discloses wherein the current sink is configured to pull, from the sink interconnect, a sink current to ground [TR1 and TR2]. Regarding claim 5, Figure 7 of Yoshimasu discloses wherein the current sink is between a reference interconnect and ground, the reference interconnect being electrically connected to the current sink [TR2]. Regarding claim 6, Figure 7 of Yoshimasu discloses wherein the current source is between the voltage rail and the reference interconnect, the reference interconnect being electrically connected to the current source [R13]. Regarding claim 7, Figure 7 of Yoshimasu discloses wherein the transistor is a diode-connected transistor [TR3]. Regarding claim 8, Figure 7 of Yoshimasu discloses wherein a drain and gate of the transistor are shorted together [TR3]. Regarding claim 9, Figure 7 of Yoshimasu discloses wherein the current source is configured to push, from the voltage rail, a drive current onto the drive interconnect [R13]. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshimasu et al (US PGPUB 2020/0036340). Regarding claim 3, Yoshimasu does not explicitly disclose wherein the current sink is electrically connected directly to the voltage rail. However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Figure 7 of Yoshimasu by removing the resistor between the current sink and the voltage rail as a matter of simple design-choice, since it was well-known in the art to directly connect current mirrors to voltage rails. Allowable Subject Matter Claims 10-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 13 and 15-20 are allowed. Response to Arguments Applicant’s arguments filed 05/19/2026, with respect to the rejection(s) of claim(s) 1-20 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Yoshimasu et al (US PGPUB 2020/0036340), as provided on the IDS filed 07/01/2026. Conclusion Applicant's submission of an information disclosure statement under 37 CFR 1.97(c) with the timing fee set forth in 37 CFR 1.17(p) on 07/01/2026 prompted the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 609.04(b). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Tomi S Skibinski whose telephone number is (571)270-7581. The examiner can normally be reached Mon. - Thurs. 8am - 6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at (571)270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TOMI SKIBINSKI/Primary Examiner, Art Unit 2836
Read full office action

Prosecution Timeline

Dec 18, 2024
Application Filed
Mar 02, 2026
Non-Final Rejection mailed — §102, §103
May 19, 2026
Response Filed
Jul 28, 2026
Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
84%
Grant Probability
87%
With Interview (+3.2%)
1y 9m (~1m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 881 resolved cases by this examiner. Grant probability derived from career allowance rate.

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