DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 6,366,149 B1).
Regarding Claim 1, Lee et al. teaches in Figure 3 a circuit comprising:
one or more tri-state inverters (10-1 through 10-n; 20-1 through 20-n), wherein each enabled tri-state inverter of the one or more tri-state inverters is configured to provide a respective delay adjustment of a signal waveform (slope controller 10; delay time controller 20; see also Figures 2, 5 and 6).
Regarding Claim 2, Lee et al. further teaches the circuit, wherein:
the respective delay adjustment corresponds to a duration less than a gate delay, and the gate delay corresponds to a propagation delay of a logic gate (see adjustable rising and falling slopes of Figures 5 and 6).
Regarding Claim 3, Lee et al. further teaches the circuit, wherein the respective delay adjustment corresponds to a change in a slope of the signal waveform plotted on a graph of voltage as a function of time (see adjustable rising and falling slopes of Figures 5 and 6).
Regarding Claim 4, Lee et al. further teaches the circuit, wherein enabled tri-state inverters of the one or more tri-state inverters are configured to provide a plurality of delay adjustments of the signal waveform (based in part on MS2 through MSn and FS2 through FSm).
Regarding Claim 5, Lee et al. further teaches the circuit, wherein:
the plurality of delay adjustments includes one or more incremental portions of durations less than a gate delay (see adjustable rising and falling slopes of Figures 5 and 6); and
each delay adjustment of the plurality of delay adjustments corresponds to a different slope of the signal waveform plotted on a graph of voltage as a function of time (Col. 5, lines 9-49).
Regarding Claim 6, Lee et al. further teaches the circuit, wherein:
a first enabled tri-state inverter of the one or more tri-state inverters is configured to provide a first respective delay adjustment of the signal waveform (at least one of 10-1 through 10-n is selected); and
a difference between the first delay adjustment and the signal waveform corresponds to a difference between a slope of the first enabled tri-state inverter and the slope of the signal waveform plotted on a graph of voltage as a function of time (see waveforms of Figures 5 and 6; see also Col. 5, lines 9-49).
Regarding Claim 7, Lee et al. further teaches the circuit, wherein:
first and second enabled tri-state inverters of the enabled tri-state inverters are configured to provide respective first and second respective delay adjustments of the signal waveform (at least one of 10-1 through 10-n is selected and at least one of 20-1 through 20-n is selected); and
a difference between the first and second delay adjustments corresponds to a difference between respective first and second slopes of the signal waveform plotted on a graph of voltage as a function of time (see waveforms of Figures 5 and 6; see also Col. 5, lines 9-49).
Regarding Claim 8, Lee et al. further teaches the circuit, wherein each of the one or more tri-state inverters is coupled in parallel (wherein 10-1 through 10-n are in parallel; wherein 20-1 through 20-n are in parallel).
Regarding Claim 9, Lee et al. further teaches in Figure 4 the circuit, wherein each tri-state inverter of the one or more tri-state inverters comprises:
a pair of NMOS transistors (one of LN1, LN2; MN1, MN2; SN1, SN2; N1, N2; N3, N4; and/or N5, N6);
a pair of PMOS transistors (one of P1, P2; P3, P4; P5, P6; LP1, LP2; MP1, MP2; and/or SP1, SP2); and
an inverter (1).
Regarding Claim 10, Lee et al. further teaches the circuit, wherein a tri-state inverter is enabled upon enabling at least one PMOS transistor and enabling at least one NMOS transistor (using MS1, MS2, and/or MS3; using FS1, FS2, and/or FS3).
Regarding Claim 11, Lee et al. further teaches the circuit, further comprising:
first and second digital gates (10-1 and 20-1), wherein:
a node is coupled between the first and second digital gates (A, as coupled between 10-1 and 20-1);
the node is coupled to the one or more tri-state inverters (A is between 10-2, 10-3 in 10 and 20-2, 20-3 in 20); and
at least the first digital gate includes a same voltage-threshold type as the one or more tri-sate inverters (wherein 10-1 is the same voltage-threshold type as 10-2, 10-3).
Regarding Claim 12, Lee et al. further teaches the circuit, wherein a capacitance at the node corresponds to the respective delay adjustment (Figure 7, C).
Regarding Claim 13, Lee et al. further teaches the circuit, wherein each additional enabled tri-state inverter of the one or more tri-state inverters is configured to generate a respective incremental delay adjustment to the signal waveform (Col. 5, lines 9-49).
Regarding Claim 14, Lee et al. teaches in Figure 7 a method comprising:
determining a first gate capacitance at a node between first and second digital gates coupled to one or more tri-state inverters (using C, as connected to node A between 10 and 20; wherein 10 and 20 are further detailed in Figures 3 and 4);
activating at least one of the one or more tri-state inverters (using MS1 through MSn and FS1 through FSm); and
determining a second gate capacitance at the node (using 20), wherein a difference between first and second gate capacitances corresponds to a delay adjustment of a signal waveform (see Figures 5 and 6).
Regarding Claim 15, Lee et al. further teaches the method, wherein:
a quantity of enabled tri-state inverters is configured to control a delay offset of the signal waveform (Col. 5, lines 9-49); and
the delay adjustment corresponds to a change in a slope of the signal waveform plotted on a graph of voltage as a function of time (see waveforms of Figures 5 and 6).
Regarding Claim 16, Lee et al. teaches in Figure 7 a circuit comprising:
a first digital gate (10-1); and
a timing offset circuit portion coupled to the first digital gate, including:
one or more tri-state inverters (10-2 through 10-n),
wherein a capacitance at an output of the first digital gate is based on a quantity of enabled tri-state inverters of the one or more tri-state inverters (using C).
Regarding Claim 17, Lee et al. further teaches the circuit, wherein:
the capacitance at the output of the first digital gate corresponds to a slope of a waveform plotted on a graph of voltage as a function of time (see waveforms of Figures 5 and 6); and
the slope corresponds to a duration less than a gate delay (see variation of slopes in Figures 5 and 6).
Regarding Claim 18, Lee et al. further teaches the circuit, further comprising:
a second digital gate (20-1),
wherein the timing offset circuit portion is coupled at a node between the first and second digital gates (20-2 through 20-n is coupled at node A), and
wherein the capacitance at the node corresponds to the quantity of the enabled tri-state inverters (using C; see also Col. 5, lines 9-49).
Regarding Claim 19, Lee et al. further teaches the circuit, wherein the quantity of the enabled tri-state inverters of the one or more tri-state inverters correspond to a delay adjustment of a signal waveform (see Col. 5, lines 9-49).
Regarding Claim 20, Lee et al. further teaches the circuit, wherein one or more enabled tri-state inverters of the one or more tri-state inverters are configured to control a timing delay of a signal waveform (see Col. 5, lines 9-49).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Uhlmann (US 6,211,713 B1) teaches an “adjustable feedback for CMOS latches” (title), as illustrated in Figure 1A, in combination with Figure 3A.
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Diana J Cheng whose telephone number is (571)270-1197. The examiner can normally be reached Monday - Friday 9 am - 5:30 pm ET.
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/DIANA J. CHENG/Primary Examiner, Art Unit 2849