DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 20 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter as follows. The claim is a “at least one memory comprising programing instructions executable by the one or more processors.” wherein the claim is explicitly directed to a computer program perse with no embodying non-transitory computer readable medium. Since a computer program does not fall within the statutory categories of 35 U.S.C. 101 (i.e., process, machine, manufacture, or composition of matter), the claim is ineligible under 35 U.S.C. 101.
Claim(s) 20 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. Claim 20 recites a "at least one memory" and the broadest reasonable interpretation of the claimed " at least one memory consistent with the specification, the state- of-the-art, and a conclusion reached by one skilled in the art, is that the full scope covers non-statutory "transitory signals and carrier waves" embodiments. The specification does not specifically define a " at least one memory " to exclude transitory media. The state-of-the- art at the time the invention was made included signals, carrier waves and other wireless communication modalities (e.g., RF, infrared, etc.) as media on which executable code was recorded and from which computers acquired such code. Thus, the full scope of the claim covers "signals" and their equivalents, which are non- statutory per se. The examiner suggests clarify the claim to exclude such non-statutory signal embodiments, such as (but not limited to) by reciting a "non-transitory memory ".
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-7, 9, 10, 11, 17, andd 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hamdan et al (Pub 2021/0399722, further referred to as Hamdan) in view of Sperling et al (Pub 2021/0089104, further referred to as Sperling).
As to claim 1, Hamdan teaches a circuit comprising (fig 4):
a droop detection element (120) comprising voltage sensitive gates (paragraphs 28 and 29;
and at least two delay elements (421 and 422)), wherein:
each delay element of the at least two delay elements is a non-inverting gate or a non-
inverting gate combination (paragraphs 2-30 and 55, provides non-inverting delays), and wherein:
at least a first delay element comprises a first voltage-threshold (VT)-type;
at least a second delay element comprises a second VT-type; and
the first and the second VT-types are different (paragraphs 66 and 67, the delays have different thresholds based on process variations);.
Hamdan does not teach using the delay with a droop detection circuit.
Sperling teaches droop detection circuit (fig 1, 120) with voltage sensitive gates (paragraph 28) which receives input from power sensitive delay circuitry (104 and 106). As such it would have been obvious to a person of ordinary skill in the art before the filing date of the invention to combine the delay circuit taught in Hamdan with the droop detection taught in Sperling in order to improve accuracy and control during voltage variations.
As to claim 3, Hamdan teaches the unit can be implemented with a buffer (fig 6, 630, paragraph 69).
As to claim 4, As would have been recognized by a person of ordinary skill in the art implementing a delay with a AND gate or an OR gate is done merely as a design choice to choosing a user desired delay configuration.
As to claim 5, Hamdan teaches a multiplexer( (fig 4, 420) configured to transmit one of:
a clock signal (output a) to a delay line circuit;
a delayed clock signal transmitted from the first delay element of the first VT-type to the
delay line circuit (output b); or
a delayed clock signal transmitted from the second delay element of the second VT-type to
the delay line circuit (output c), wherein an input of the second delay element of the second VT-type is coupled to the output of the first delay element of the first VT-type (421 is output to 422).
As to claim 6, Hamdan teaches the clock signal at a first input (a) of the multiplexer (420);
the output of the first delay element at a second input of the multiplexer (b); and
the output of the second delay element at a third input of the multiplexer (c).
As to claim 7, Hamdan teaches the at least two delay elements (421 and 422) are a plurality of the delay elements (there are at least two delay elements 421 and 422, making it a plurality of delays); and the plurality of the delay elements comprises an arrangement of first delay elements (421) and an
arrangement of second delay elements (422), wherein the arrangement of the first delay elements and the arrangement of the second delay elements comprise at least one of: one or more single first delay elements (421) and one or more single second delay elements (422); one or more pairs of first delay elements and one or more pairs of second delay elements; or one or more triads of first delay elements and one or more triads of second delay elements.
As to claim 9, Hamdan teaches a multiplexer (420)configured to transmit a selected clock signal to a delay line circuit from a plurality of different versions of the clock signal (output a-d), wherein the different versions comprise at least a clock signal (a) and one or more delayed versions of the clock signal (b-d).
As to claim 10, Hamdan teaches the one or more delayed versions of the clock signal are transmitted from respective delay elements of the first or the second VT-types (b output is based om 421 and c output is based on 422).
As to claim 11, Hamdan teaches the clock signal at a first input (a) of the multiplexer;
an output of a first arrangement of the arrangement of first delay elements at a second input (b) of the multiplexer; or an output of a first arrangement of the arrangement of second delay elements at a third input (C) of the multiplexer.
As to claim 17, Hamdan teaches a method comprising (fig 4):
Providing a droop detection element (120) comprising voltage sensitive gates (paragraphs 28 and 29;
Providing by at least two delay elements (421 and 422)), a clock signal (input a at 420) or delay versions of the clock signal (inputs b and c at 420) wherein each delay element of the at least two delay elements have a first and the second VT-types that are different (paragraphs 66 and 67, the delays have different thresholds based on process variations);
Selecting the clock signal (by 420 at input a) or one of the delayed versions of the clock signal (b or c).
Hamdan does not teach using the delay with a droop detection circuit.
Sperling teaches droop detection circuit (fig 1, 120) with voltage sensitive gates (paragraph 28) which receives input from power sensitive delay circuitry (104 and 106). As such it would have been obvious to a person of ordinary skill in the art before the filing date of the invention to combine the delay circuit taught in Hamdan with the droop detection taught in Sperling in order to improve accuracy and control during voltage variations.
As to claim 20, Hamdan teaches a method comprising (fig 4):
Providing a droop detection element (120) comprising voltage sensitive gates (paragraphs 28 and 29;
Providing by at least two delay elements (421 and 422)), a clock signal (input a at 420) or delay versions of the clock signal (inputs b and c at 420) wherein each delay element of the at least two delay elements have a first and the second VT-types that are different (paragraphs 66 and 67, the delays have different thresholds based on process variations);
Selecting the clock signal (by 420 at input a) or one of the delayed versions of the clock signal (b or c); where it can be stored in memory and executed by a processor (paragraphs 97 and 98).
Hamdan does not teach using the delay with a droop detection circuit.
Sperling teaches droop detection circuit (fig 1, 120) with voltage sensitive gates (paragraph 28) which receives input from power sensitive delay circuitry (104 and 106). As such it would have been obvious to a person of ordinary skill in the art before the filing date of the invention to combine the delay circuit taught in Hamdan with the droop detection taught in Sperling in order to improve accuracy and control during voltage variations.
Allowable Subject Matter
Claims 2, 8, 12-16, 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
None of the cited prior art teach or suggest the specific transistors threshold type as is recited in claims 2, 8, 18, 19; the arrangement output taught in claims 12; and telescopic delay taught in claims 13-16.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Sathe et al (Pub 2012/0187991) teaches a delay adjustment and droop detection.
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/JEFFREY M SHIN/Primary Examiner, Art Unit 2836
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