DETAILED ACTION
This office action is in response to applicant’s remarks filed on April 1, 2026 in application 18/985,323.
Claims 1, 4-15 are presented for examination. Claims 1, 4-7, 9-12 are amended. Claims 2-3 are cancelled. Claims 13-15 are newly added.
IDS submitted on December 18, 2024 was acknowledged.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 4-15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant have amend overwriting the recovery program to writing to a second memory the recovery information. Refer to the rejection below of newly added reference Rahardio et al. for further details.
Claim Objections
Claims 1 and 11 are objected to because of the following informalities: Claim 1 recited “Arrah” on lines 7. Claim 11 recited “writing but the CPU” on line 8-9. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4-5, 10-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Borikar et al. (US 2021/0182212) in further view of Rahardjo et al. (US 2020/0134183).
In regard to claim 1, Borikar et al. teach an information processing apparatus including one or more units, wherein
the one or more units (chassis, fig. 1, 110) include a unit controller (server 112A or Server 112B, fig. 1),
the unit controller includes a first sub-system including a Central Processing Unit (CPU) (CPU 120A or CPU 120B, fig. 1) and a first memory (boot memory, fig. 1);
a second sub-system including a Field Programmable Gate array (FPGA) (baseboard management controller (BMC), 118A or 118B, fig. 1); and
Borikar et al. does not explicitly teach but Rahardjo et al. teach a second memory different from the first memory (firmware maintained by the remote access controller, fig. 2, 255), wherein a case where the CPU cannot communicate with the FPGA, the CPU writes the recovery configuration data into the second memory (the remote access controller may be configured to detect corruption of the active firmware and to replace the corrupted firmware without reliance on the recovery firmware, para. 38), and wherein, by the information processing apparatus being rebooted, the FPGA is booted by executing the recovery configuration data store in the second memory (management controller 220a may transmit a copy of the firmware 220d-e to the remote access controller 255, para. 40, where the remote access controller may provide BIOS functions implemented in full or in part, para. 41).
It would have been obvious to modify the apparatus of Borikar et al. by adding Rahardjo et al. recover FPGA firmware. A person of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make the modification because it would provide a recovery partition to reinitialized the FPGA and also further provide a remote access controller with a master copy of the FPGA card firmware (para. 38-39).
In regard to claim 4, Borikar et al. teach the information processing apparatus according to claim 1, wherein when the CPU and the FPGA establish communication, the FPGA collects configuration information of the second sub-system and transfers the configuration information to the CPU, the CPU acquires operational configuration data based on the configuration information from a server, (the ICH can connect computing system to peripheral devices, the BMC 212 and the boot subsystem 214 … the BMC 212 can provide management access to the computing system 200 prior to the loading of an operating system, and can operate as an aggregation point for server hardware … the boot subsystem 214 can include software or firmware for initializing hardware upon powering on or booting up the computing system 200, para. 56).
Borikar et al. does not explicitly teach but Rahardjo et al. teach writes the operational configuration data into the second memory (firmware maintained by the remote access controller, fig. 2, 255), and by the information processing apparatus being rebooted, the FPGA is booted by executing the operation configuration data stored in the second memory (management controller 220a may transmit a copy of the firmware 220d-e to the remote access controller 255, para. 40, where the remote access controller may provide BIOS functions implemented in full or in part, para. 41).
Refer to claim 1 for motivational statement.
In regard to claim 5, Borikar et al. teach the information processing apparatus according to claim 4, wherein the operational configuration data varies depending on a configuration of the second sub-system (BMC can monitor and manage the state of the server, can include specialized service processor and firmware to provide management and monitoring capabilities, para. 29).
In regard to claim 10, Borikar et al. teach an information processing apparatus including one or more units (chassis, fig. 1, 110), wherein
the one or more units (chassis, fig. 1, 110) include a unit controller (server 112A or Server 112B, fig. 1),
the unit controller includes a first sub-system including a Central Processing Unit (CPU) (CPU 120A or CPU 120B, fig. 1);
a second sub-system including a Field Programmable Gate Array (FPGA) (baseboard management controller (BMC), 118A or 118B, fig. 1); and a memory (boot memory, fig. 1),
wherein, when the information processing apparatus is booted, the FPGA collects configuration information of the second sub-system and transfers the configuration information to the CPU (the ICH can connect computing system to peripheral devices, the BMC 212 and the boot subsystem 214 … the BMC 212 can provide management access to the computing system 200 prior to the loading of an operating system, and can operate as an aggregation point for server hardware … the boot subsystem 214 can include software or firmware for initializing hardware upon powering on or booting up the computing system 200, para. 56).
Borikar et al. does not explicitly teach but Rahardjo et al. teach wherein the CPU acquires operational configuration data based on the configuration information from a server, and writes the operational configuration data into the memory (firmware maintained by the remote access controller, fig. 2, 255), and wherein, by the information processing apparatus being rebooted, the FPGA is booted by executing the operation configuration data stored in the memory (management controller 220a may transmit a copy of the firmware 220d-e to the remote access controller 255, para. 40, where the remote access controller may provide BIOS functions implemented in full or in part, para. 41).
Refer to claim 1 for motivational statement.
In regard to claim 11, Borikar et al. teach a method for controlling an information processing apparatus including one or more units (chassis, fig. 1, 110) each including a unit controller (server 112A or Server 112B, fig. 1), the unit controller including:
the unit controller includes a first sub-system including a Central Processing Unit (CPU) (CPU 120A or CPU 120B, fig. 1) and a first memory configured to store recovery configuration data (memory, fig. 1);
a second sub-system including a Field Programmable Gate array (FPGA) (baseboard management controller (BMC), 118A or 118B, fig. 1); and
Borikar et al. does not explicitly teach but Rahardjo et al. teach a second memory different from the first memory (firmware maintained by the remote access controller, fig. 2, 255), the method comprising: in a case where the CPU cannot communicate with the FPGA, writing but the CPU, the recovery configuration data into the second memory (the remote access controller may be configured to detect corruption of the active firmware and to replace the corrupted firmware without reliance on the recovery firmware, para. 38), and rebooting the information processing apparatus, wherein the FPGA is booted by executing the recovery configuration data store in the second memory (management controller 220a may transmit a copy of the firmware 220d-e to the remote access controller 255, para. 40, where the remote access controller may provide BIOS functions implemented in full or in part, para. 41).
Refer to claim 1 for motivational statement.
In regard to claim 12, Borikar et al. teach a non-transitory computer-readable storage medium, the storage medium storing a program for causing a computer to execute each step of a method for controlling an information processing apparatus including one or more units (chassis, fig. 1, 110) each including a unit controller (server 112A or Server 112B, fig. 1), the unit controller including:
a first sub-system including a Central Processing Unit (CPU) (CPU 120A or CPU 120B, fig. 1) and a first memory configured to store recovery configuration data (memory, fig. 1);
a second sub-system including a Field Programmable Gate array (FPGA) (baseboard management controller (BMC), 118A or 118B, fig. 1); and
Borikar et al. does not explicitly teach but Rahardjo et al. teach a second memory different from the first memory (firmware maintained by the remote access controller, fig. 2, 255), the method comprising: in a case where the CPU cannot communicate with the FPGA, writing by the CPU, the recovery configuration data into the second memory (the remote access controller may be configured to detect corruption of the active firmware and to replace the corrupted firmware without reliance on the recovery firmware, para. 38), and rebooting the information processing apparatus, wherein the FPGA is booted by executing the recovery configuration data store in the second memory (management controller 220a may transmit a copy of the firmware 220d-e to the remote access controller 255, para. 40, where the remote access controller may provide BIOS functions implemented in full or in part, para. 41).
Refer to claim 1 for motivational statement.
In regard to claim 13, Borikar et al. does not explicitly teach but Rahardjo et al. teach the information processing apparatus according to claim 1, wherein the recovery configuration is minimum configuration data (many instance, the recovery partition may store prior versions of the firmware instructions, para. 37).
Refer to claim 1 for motivational statement.
In regard to claim 14, Borikar et al. teach the information processing apparatus according to claim 1, wherein the second sub-system includes one or more function boards (baseboard management controller (BMC), 118A or 118B, fig. 1).
In regard to claim 15, Borikar et al. teach the information processing apparatus according to claim 4, wherein the CPU receives the configuration information via the established communication (boot subsystem can discover and setup one or more peripheral devices for access by the CPU, para. 40).
*****************
Claims 6-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Borikar et al. (US 2021/0182212) in further view of Rahardjo et al. (US 2020/0134183) in further view of Jayakumar et al. (US 2020/0257521).
In regard to claim 6, Borikar et al. and Rahardjo et al. does not explicitly teach but Jayakumar et al. teach the information processing apparatus according to claim 4, wherein when the recovery configuration data fails in recovery or the operation configuration data fails in recovery, the CPU calls a call center regarding failure in on-site recovery (if the boot firmware code is rejected, an administrator can be notified as the attempt to load another boot firmware code … the boot firmware code that was not authenticated can be deleted or overwritten, para. 42, it is noted that the administrator is notified is equated to the call to a call center).
It would have been obvious to modify the apparatus of Borikar et al. and Rahardjo et al. by adding Jayakumar et al. update of boot code handler. A person of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make the modification because it would aid in an update to an SMI handler (para. 13).
In regard to claim 7, Borikar et al. and Rahardjo et al. does not explicitly teach but Jayakumar et al. teach the information processing apparatus according to claim 4, wherein the recovery configuration data is configuration data in which some functions are removed from the operational configuration data (update can be for a variety of reasons such as bug fixes, security patches, feature enhancement and so forth, para. 7. It is noted that the update to remover the old code is equated to a removed of some functions).
Refer to claim 6 for motivational statement.
In regard to claim 8, Borikar et al. and Rahardjo et al. does not explicitly teach but Jayakumar et al. teach the information processing apparatus according to claim 7, wherein the some functions that are removed are control functions of a device (update can be for a variety of reasons such as bug fixes, security patches, feature enhancement and so forth, para. 7. It is noted that the update to remover the old code is equated to a removed of some functions).
Refer to claim 6 for motivational statement.
In regard to claim 9, Borikar et al. and Rahardjo et al. does not explicitly teach but Jayakumar et al. teach the information processing apparatus according to claim 4, wherein the recovery configuration data has a function of performing boot control of the second sub-system, a function of acquiring configuration information of the second sub-system, and a function of performing communication with the CPU (update an SMI handler can perform 1. store the new handler as part of a boot firmware code update, 2. Authenticated the stage image, 3. Decline or accept the new SMI handler code, 4. Install accepted SMI handler code by the current SMI handler, para. 11).
Refer to claim 6 for motivational statement.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO 892.
Zhu et al. (US 12,579,352) fig. 5, use secondary or backup CD for reboot
Johnson (US 2013/0232328) using two FPGA memories for upgrading boot program
************
Okamura et al. (US 2025/0337565) secure booting and recovery
Gao et al. (US 12,423,186) fault recovery for BMC firmware
Bhatia et al. (US 12,393,486) recovering a firmware image in BMC
Li (US 2025/0165422) BMC and CPU power on or de-reset
Shpilyuek et al. (US 2021/0406052) recovery site for boot OS disk
Bower, III et al. (US 11,863,414) bootable image hosted by BMC and visible to host CPU
Chou (US 11,775,314) CPU, BMC and boot memory
Hung et al. (US 2023/0297390) shared memory between hosts (CPU) and BMC
Hung et al. (US 2017/0109235) BMC controller recovery
Shadbolt et al. (US 2022/0299966) technician to repair data-corruption error in control logic
Jayaraman et al. (US 10,831,688) BMC gather/receive data about connectivity to CPU
Rangel-Martinez et al. (Us 2020/0218811) secure boot and update firmware
Ahmed et al. (US 2017/0131753) provisioning of a data center
Inada et al. (US 2006/0184781) printer with double boot function and overwrite
Broyles, III et al. (Us 2006/0020845) unattended bios recovery with update tool
King et al. (US 2004/0162977) service controller for rack-mounted computer
Little et al. (US 2002/0052718) recover boot by maintenance personnel
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LOAN TRUONG whose telephone number is 408-918-7552. The examiner can normally be reached on 10AM-6PM PST M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ashish Thomas can be reached on 571-272-0631. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Loan L.T. Truong/Primary Examiner, Art Unit 2114 Loan.truong@uspto.gov
Prosecution Insights