DETAILED ACTION
The instant application having Application No. 18/985,562 has claims 1-20 pending in the application, all of which are ready for examination by the examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgement is made of applicant’s claim for foreign priority based on an application filed in REPUBLIC OF KOREA on 1/5/2024. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/18/2024 is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 20 recites the term ‘the target generation parameter set’, but there is insufficient antecedent basis for this term. If the applicant intended to recite ‘target operation parameter set’, the examiner suggests amending ‘target generation parameter set’ as ‘target operation parameter set’.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-7, 10-11, 13, 15-16, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hu et al. (US 9251891 B1) in view of Madraswala et al. (US 20190102097 A1).
As per claim 1,
1. A memory system comprising: a memory device comprising a memory cell array and an offset table; and a memory controller configured to [Hu teaches a system comprising a controller and a memory device with a memory (col. 2, lines 21-35); Hu further teaches the memory device comprising a table comprising index values, or trim tags (col. 3, lines 33-58; fig. 1 and associated paragraphs)] generate a target operation parameter set corresponding to a current situation of the memory device and, in response to a target index being assigned to the target operation parameter set, transmit the target index to the memory device, wherein the offset table comprises mapping information between sample operation parameter sets respectively corresponding to sample situations of the memory device and indices respectively assigned to the sample operation parameter sets, and [Hu teaches the index values, or trim tags, used to identify a parameter set (e.g. read voltages) for memory operations, where the trim tags may be stored as a table in the memory device in association with corresponding data units (col. 3, lines 33-65; see col. 3, lines 57-58 on the memory also storing parameter values), where a parameter set in the memory may correspond to a sample operation parameter set; Hu teaches the controller retrieving a trim tag (target index) and comparing parameter values of a scheduled memory operation in the controller which matches the trim tag (target operation parameter set) against parameter values corresponding to parameter values stored in the memory (col. 4, line 53 – col. 5, line 20; col. 10, line 58 – col. 11, line 7; col. 11, lines 44 – col. 12, line 44; claim 1; figs. 1-2, 5 and associated paragraphs); responsive to the parameter values matching (a target index being assigned to the target operation parameter set), Hu teaches abstaining from sending updated parameter values to the memory and performing the scheduled (e.g. read) operation (col. 10, lines 11-26; col. 12, lines 17-22; see col. 4, lines 7-19, col. 6, lines 11-45 indicating the parameter values associated with trim tags in the memory device and the updated parameter values sent by the controller may correspond to different circumstances (e.g. SLC/MLC mode, time since storage))]
Hu does not explicitly disclose, but Madraswala teaches:
transmit the target index to the memory device,; wherein the memory device is configured to obtain target operation parameters mapped to the target index based on the offset table, adjust read voltages based on the target operation parameters, and read data stored in the memory cell array by using the adjusted read voltages. [Hu as shown above teaches the memory device comprising a table of trim tags corresponding to parameter sets to be used for memory operations, and, when the parameter values for a scheduled operation in the controller corresponding a retrieved trim tag matches the parameter values in the memory (i.e. the target operation parameter set already being in the memory), performing a memory operation without updating the parameters in the memory (please see the rejection above; col. 3, lines 33-65; col. 12, lines 15-23); where Hu does not explicitly disclose transmitting the trim tag to the memory for performing the operation, Madraswala teaches a controller sending a read voltage offset profile identifier with a read command, where the read voltage offset profile associated with the identifier is determined by the memory array for adjusting read voltages applied during the read operation as specified by the offsets in the profile (para. 16-17, 64-65, 87-89; figs. 1, 4, 8 and associated paragraphs; see para. 85 providing the profile identifiers and the profiles also being stored in a table)]
Hu and Madraswala are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Hu and Madraswala, to modify the disclosures by Hu to include disclosures by Madraswala since they both teach data storage and access, wherein Madraswala is directed towards improvements in memory reading procedures (para. 2). Therefore, it would be applying a known technique (transmission of a read command with a read voltage offset profile identifier used by memory device to apply a corresponding profile specifying read voltage offsets) to a known device (system comprising a memory device having trim tags indicating corresponding parameter sets used in memory operations) ready for improvement to yield predictable results (system comprising a memory device having trim tags indicating corresponding parameter sets used in memory operations, where a trim tag corresponding to a parameter set to be used by the memory device for a memory operation may be received with a memory operation command in order to provide for improved reliability in selection of the appropriate memory operation parameters). MPEP 2143
As per claim 2, Hu in view of Madraswala teaches claim 1 as shown above and further teaches:
2. The memory system of claim 1, wherein the memory controller is further configured to transmit the target operation parameter set to the memory device in response to no index being assigned to the target operation parameter set. [Hu in view of Madraswala teaches, if the parameter values of a scheduled operation corresponding to a retrieved trim tag and a copy of the parameter values of the memory do not match (no index being assigned to the target operation parameter set), transmitting updated parameter values to the memory device to overwrite the parameter values in the memory (see claim 1 above; Hu: col. 3, line 57 – col. 4, line 19; col. 4, line 53 – col. 5, line 31; col. 10, lines 26-34)]
As per claim 3, Hu in view of Madraswala teaches claim 2 as shown above and further teaches:
3. The memory system of claim 2, wherein a data amount of the target index transmitted by the memory controller to the memory device is less than a data amount of the target operation parameter set transmitted by the memory controller to the memory device. [Hu in view of Madraswala provides for an example of a trim tag comprising an integer value (e.g. 1) (Hu: col. 3, lines 33-45) and an example of a parameter set comprising a plurality of read voltages (Hu: col. 3, lines 33-45; also see Madraswala: fig. 4 giving an example of a plurality of voltage offset values in a profile), where data comprising an integer may necessarily comprise less data amount than data comprising a plurality of read voltages or offsets.]
As per claim 4, Hu in view of Madraswala teaches claim 2 as shown above and further teaches:
4. The memory system of claim 1, wherein in an initialization period the memory controller is configured to generate operation parameter sets respectively corresponding to a plurality of situations of the memory device, and respectively assign indices to the sample operation parameter sets corresponding to the sample situations that are some of the plurality of situations, transmit the sample operation parameter sets and the indices respectively assigned to the sample operation parameter sets to the memory device, and store the sample operation parameter sets and the indices as the offset table. [Hu as shown above teaches trim tags associated with parameter sets and further teaches performing initialization including setting values of memory device and storing an initial set of parameter values in the memory device (see claim 1 above; Hu: col. 3, lines 33-65; col. 13, lines 30-37); Madraswala teaches a memory controller generating read voltage offset profiles to be stored in a memory device, where the memory controller performs tests for optimal read voltage offsets for particular situations and thereby determines read voltage offset profiles to be used during operation of the memory, where the profiles can be stored in a in a lookup table of a memory device in association with profile identifiers (para. 82-86; fig. 8 and associated paragraphs), where the read voltage sets tested may correspond to operation parameter sets, and the read voltage sets stored in association with voltage offset profile identifiers may correspond to sample operation parameter sets; where it would have been obvious for one of ordinary skill in the arts, provided with Hu’s disclosure of setting the parameter values during initialization and Madraswala’s disclosure of a memory controller performing tests to determine and store read voltage profiles and identifiers, to provide for a combination where the a controller may, during initialization, perform tests to determine and store the parameter values for the parameter sets and trim tags; doing so would provide for improved read efficiency by requiring fewer adjustments to be made during the runtime of the system]
Hu and Madraswala are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Hu and Madraswala, to modify the disclosures by Hu to include disclosures by Madraswala since they both teach data storage and access, wherein Madraswala is directed towards improvements in memory reading procedures (para. 2). Therefore, it would be applying a known technique (transmission of a read command with a read voltage offset profile identifier used by memory device to apply a corresponding profile specifying read voltage offsets, a controller performing tests for determining and storing read voltage offset profiles and associated identifiers to the memory) to a known device (system comprising a memory device having trim tags indicating corresponding parameter sets used in memory operations, the trim tags and the parameters sets being stored to the memory device during initialization) ready for improvement to yield predictable results (system comprising a memory device having trim tags indicating corresponding parameter sets used in memory operations, the trim tags and the parameters sets stored in the memory device by a controller during initialization after testing to provide for reduced error rate during runtime, where a trim tag corresponding to a parameter set to be used by the memory device for a memory operation may be received with a memory operation command in order to provide for improved reliability in selection of the appropriate memory operation parameters). MPEP 2143
As per claim 6, Hu in view of Madraswala teaches claim 1 as shown above and further teaches:
6. The memory system of claim 1, wherein the memory device is further configured to obtain target operation parameters mapped to the target index based on the offset table in response to receiving the target index and a first read command, to adjust read voltages based on the target operation parameters, and to read data stored in the memory cell array by using the adjusted read voltages. [Hu as shown above teaches the memory device comprising a table of trim tags corresponding to parameter sets to be used for memory operations, and, when the parameter values for a scheduled operation in the controller corresponding a retrieved trim tag matches the parameter values in the memory (i.e. the target operation parameter set already being in the memory), performing a memory operation without updating the parameters in the memory (see claim 1; col. 3, lines 33-65; col. 12, lines 15-23); where Hu does not explicitly disclose transmitting the trim tag to the memory for performing the operation, Madraswala teaches a controller sending a read voltage offset profile identifier with a read command, where the read voltage offset profile associated with the identifier is determined by the memory array for adjusting read voltages applied during the read operation as specified by the offsets in the profile (para. 16-17, 64-65, 87-89; figs. 1, 4, 8 and associated paragraphs; see para. 85 providing the profile identifiers and the profiles also being stored in a table)]
Hu and Madraswala are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Hu and Madraswala, to modify the disclosures by Hu to include disclosures by Madraswala since they both teach data storage and access, wherein Madraswala is directed towards improvements in memory reading procedures (para. 2). Therefore, it would be applying a known technique (transmission of a read command with a read voltage offset profile identifier used by memory device to apply a corresponding profile specifying read voltage offsets) to a known device (system comprising a memory device having trim tags indicating corresponding parameter sets used in memory operations) ready for improvement to yield predictable results (system comprising a memory device having trim tags indicating corresponding parameter sets used in memory operations, where a trim tag corresponding to a parameter set to be used by the memory device for a memory operation may be received with a memory operation command in order to provide for improved reliability in selection of the appropriate memory operation parameters). MPEP 2143
As per claim 7, Hu in view of Madraswala teaches claim 2 as shown above and further teaches:
7. The memory system of claim 2, wherein the memory device is further configured to, when receiving the target operation parameter set and a second read command, read data stored in the memory cell array by using read voltages adjusted based on the target operation parameters. [Hu in view of Madraswala as shown above teaches, if the parameter values of a scheduled operation corresponding to a retrieved trim tag and a copy of the parameter values of the memory do not match (no index being assigned to the target operation parameter set), transmitting updated parameter values to the memory device to overwrite the parameter values in the memory (see claim 2 above; Hu: col. 3, line 57 – col. 4, line 19; col. 4, line 53 – col. 5, line 31; col. 10, lines 26-34); Hu in view of Madraswala further teaches performing a read operation according to a read command (Hu: col. 3, lines 33-65; col. 12, lines 15-23; Madraswala: para. 16-17, 64-65, 87-89)]
Hu and Madraswala are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Hu and Madraswala, to modify the disclosures by Hu to include disclosures by Madraswala since they both teach data storage and access, wherein Madraswala is directed towards improvements in memory reading procedures (para. 2). Therefore, it would be applying a known technique (transmission of a read command with a read voltage offset profile identifier used by memory device to apply a corresponding profile specifying read voltage offsets) to a known device (system comprising a memory device having trim tags indicating corresponding parameter sets used in memory operations) ready for improvement to yield predictable results (system comprising a memory device having trim tags indicating corresponding parameter sets used in memory operations, where a trim tag corresponding to a parameter set to be used by the memory device for a memory operation may be received with a memory operation command in order to provide for improved reliability in selection of the appropriate memory operation parameters). MPEP 2143
As per claim 10,
10. A memory controller comprising: the index processor [Hu teaches a system comprising a controller comprising a processor and a memory device with a memory (col. 2, lines 21-35); Hu further teaches the memory device comprising a table comprising index values, or trim tags (col. 3, lines 33-58; fig. 1 and associated paragraphs)] configured to generate a target operation parameter set corresponding to a current situation of the memory device and associated with compensating for operational characteristics of the memory device in the current situation, and the index processor configured to determine whether the target operation parameter set is matched to one of the sample operation parameter sets and a target index is assigned to the target operation parameter set, and transmit operation data that is different based on whether there is the target index; and [Hu teaches the index values, or trim tags, used to identify a parameter set (e.g. read voltages) for memory operations, where the trim tags may be stored as a table in the memory device in association with corresponding data units (col. 3, lines 33-65; see col. 3, lines 57-58 on the memory also storing parameter values), where a parameter set in the memory may correspond to a sample operation parameter set; Hu teaches the controller retrieving a trim tag (target index) and comparing parameter values of a scheduled memory operation in the controller which matches the trim tag (target operation parameter set) against parameter values corresponding to parameter values stored in the memory (col. 4, line 53 – col. 5, line 20; col. 10, line 58 – col. 11, line 7; col. 11, lines 44 – col. 12, line 44; claim 1; figs. 1-2, 5 and associated paragraphs); responsive to the parameter values matching (the target operation parameter set is matched and assigned the index), Hu teaches abstaining from sending updated parameter values to the memory and performing the scheduled (e.g. read) operation (col. 10, lines 11-26; col. 12, lines 17-22; see col. 4, lines 7-19, col. 6, lines 11-45 indicating the parameter values associated with trim tags in the memory device and the updated parameter values sent by the controller may correspond to different circumstances (e.g. SLC/MLC mode, time since storage)) and, responsive to the parameter values not matching, transmitting updated parameter values to the memory device to overwrite the parameter values in the memory (Hu: col. 3, line 57 – col. 4, line 19; col. 4, line 53 – col. 5, line 31; col. 10, lines 26-34)] a memory interface configured to transmit the operation data, which is one of the target index and the target operation parameter set, to the memory device. [Hu teaches a memory interface for communications between the host and the memory device (col. 4, lines 20-23; col. 5, lines 26-31; col. 10, lines 20-34)]
[With respect to the of limitation comprising, “transmit operation data that is different based on whether there is the target index”, while the recitation of the basis as ‘whether there is the target index’ appears to have been intended to indicate a condition of the target index being assigned to the target operation parameter set or not, the examiner respectfully notes that said limitation as presently recited could be interpreted as a much broader condition, such as whether the target index is present in a system]
Hu does not explicitly disclose, but Madraswala discloses:
target index; [Hu as shown above teaches the memory device comprising a table of trim tags corresponding to parameter sets to be used for memory operations, and, when the parameter values for a scheduled operation in the controller corresponding a retrieved trim tag matches the parameter values in the memory (i.e. the target operation parameter set already being in the memory), performing a memory operation without updating the parameters in the memory (please see the rejection above; col. 3, lines 33-65; col. 12, lines 15-23); where Hu does not explicitly disclose transmitting the trim tag to the memory for performing the operation, Madraswala teaches a controller sending a read voltage offset profile identifier with a read command, where the read voltage offset profile associated with the identifier is determined by the memory array for adjusting read voltages applied during the read operation as specified by the offsets in the profile (para. 16-17, 64-65, 87-89; figs. 1, 4, 8 and associated paragraphs; see para. 85 providing the profile identifiers and the profiles also being stored in a table; see para. 62 on interfacing between a memory controller and memory chip)] an index processor configured to generate sample operation parameter sets corresponding to sample situations of a memory device and indices respectively assigned to the sample operation parameter sets, [Hu does not explicitly disclose the processor generating and storing trim tags and parameter sets in the memory, but it does provide for the memory device performing initialization including setting values of memory device and storing an initial set of parameter values in the memory device (Hu: col. 3, lines 33-65; col. 13, lines 30-37); Madraswala teaches a memory controller generating read voltage offset profiles to be stored in a memory device, where the memory controller performs tests for optimal read voltage offsets for particular situations and thereby determines read voltage offset profiles to be used during operation of the memory, where the profiles can be stored in a in a lookup table of a memory device in association with profile identifiers (para. 82-86; fig. 8 and associated paragraphs), where the read voltage sets stored in association with voltage offset profile identifiers may correspond to sample operation parameter sets; where it would have been obvious for one of ordinary skill in the arts, provided with Hu’s disclosure of setting the parameter values during initialization and Madraswala’s disclosure of a memory controller performing tests to determine and store read voltage profiles and identifiers, to provide for a combination where the a controller may, during initialization, perform tests to determine and store the parameter values for the parameter sets and trim tags; doing so would provide for improved read efficiency by requiring fewer adjustments to be made during the runtime of the system]
Hu and Madraswala are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Hu and Madraswala, to modify the disclosures by Hu to include disclosures by Madraswala since they both teach data storage and access, wherein Madraswala is directed towards improvements in memory reading procedures (para. 2). Therefore, it would be applying a known technique (transmission of a read command with a read voltage offset profile identifier used by memory device to apply a corresponding profile specifying read voltage offsets, a controller performing tests for determining and storing read voltage offset profiles and associated identifiers to the memory) to a known device (system comprising a memory device having trim tags indicating corresponding parameter sets used in memory operations, the trim tags and the parameters sets being stored to the memory device during initialization) ready for improvement to yield predictable results (system comprising a memory device having trim tags indicating corresponding parameter sets used in memory operations, the trim tags and the parameters sets stored in the memory device by a controller during initialization after testing to provide for reduced error rate during runtime, where a trim tag corresponding to a parameter set to be used by the memory device for a memory operation may be received with a memory operation command in order to provide for improved reliability in selection of the appropriate memory operation parameters). MPEP 2143
As per claim 11, Hu in view of Madraswala teaches claim 10 as shown above and further teaches:
11. The memory controller of claim 10, wherein the index processor is further configured to transmit the target index as the operation data to the memory device through the memory interface in response to the target operation parameter set being matched to one of the sample operation parameter sets and the target index being assigned to the target operation parameter set. [Hu in view of Madraswala as shown above teaches transmitting a read command comprising a trim tag, without sending updated parameter values, responsive to the parameter values for a scheduled operation for the trim tag matching the copy of the parameter values of the memory (see claim 10; Hu: col. 3, lines 33-65; col. 12, lines 15-23; Madraswala: para. 16-17, 64-65, 87-89; figs. 1, 4, 8)]
Hu and Madraswala are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Hu and Madraswala, to modify the disclosures by Hu to include disclosures by Madraswala since they both teach data storage and access, wherein Madraswala is directed towards improvements in memory reading procedures (para. 2). Therefore, it would be applying a known technique (transmission of a read command with a read voltage offset profile identifier used by memory device to apply a corresponding profile specifying read voltage offsets, a controller performing tests for determining and storing read voltage offset profiles and associated identifiers to the memory) to a known device (system comprising a memory device having trim tags indicating corresponding parameter sets used in memory operations, the trim tags and the parameters sets being stored to the memory device during initialization) ready for improvement to yield predictable results (system comprising a memory device having trim tags indicating corresponding parameter sets used in memory operations, the trim tags and the parameters sets stored in the memory device by a controller during initialization after testing to provide for reduced error rate during runtime, where a trim tag corresponding to a parameter set to be used by the memory device for a memory operation may be received with a memory operation command in order to provide for improved reliability in selection of the appropriate memory operation parameters). MPEP 2143
As per claim 13, Hu in view of Madraswala teaches claim 10 as shown above and further teaches:
13. The memory controller of claim 10, wherein the index processor is further configured to transmit the target operation parameter set as the operation data to the memory device through the memory interface in response to the target operation parameter set not being matched to one of the sample operation parameter sets and there is no target index assigned to the target operation parameter set. [Hu in view of Madraswala teaches, if the parameter values of a scheduled operation corresponding to a retrieved trim tag and a copy of the parameter values of the memory do not match, transmitting updated parameter values to the memory device to overwrite the parameter values in the memory (see claim 10 above; Hu: col. 3, line 57 – col. 4, line 19; col. 4, line 53 – col. 5, line 31; col. 10, lines 26-34)]
As per claim 15, Hu in view of Madraswala teaches claim 10 as shown above and further teaches:
15. The memory controller of claim 10, wherein the index processor is further configured to, generate a first operation command in response to the target index being assigned to the target operation parameter set, and [Hu in view of Madraswala as shown above teaches the controller transmitting a read command comprising a trim tag, without sending updated parameter values, responsive to the parameter values for a scheduled operation for the trim tag matching the parameter values of memory (see claim 10; Hu: col. 3, lines 33-65; col. 12, lines 15-23; Madraswala: para. 16-17, 64-65, 87-89; figs. 1, 4, 8)] generate a second operation command in response to no target index being assigned to the target operation parameter set, wherein the first operation command is different from the second operation command. [Hu in view of Madraswala teaches, if the parameter values of a scheduled operation corresponding to a retrieved trim tag and a copy of the parameter values of the memory do not match, transmitting updated parameter values to the memory device to overwrite the parameter values in the memory (see claim 10 above; Hu: col. 3, line 57 – col. 4, line 19; col. 4, line 53 – col. 5, line 31; col. 10, lines 26-34; see col. 3, line 667 on an instruction being sent for updating the parameter values), where a read command for reading stored data and an instruction for updating the parameter values are necessarily different]
Hu and Madraswala are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Hu and Madraswala, to modify the disclosures by Hu to include disclosures by Madraswala since they both teach data storage and access, wherein Madraswala is directed towards improvements in memory reading procedures (para. 2). Therefore, it would be applying a known technique (transmission of a read command with a read voltage offset profile identifier used by memory device to apply a corresponding profile specifying read voltage offsets, a controller performing tests for determining and storing read voltage offset profiles and associated identifiers to the memory) to a known device (system comprising a memory device having trim tags indicating corresponding parameter sets used in memory operations, the trim tags and the parameters sets being stored to the memory device during initialization) ready for improvement to yield predictable results (system comprising a memory device having trim tags indicating corresponding parameter sets used in memory operations, the trim tags and the parameters sets stored in the memory device by a controller during initialization after testing to provide for reduced error rate during runtime, where a trim tag corresponding to a parameter set to be used by the memory device for a memory operation may be received with a memory operation command in order to provide for improved reliability in selection of the appropriate memory operation parameters). MPEP 2143
As per claim 16, Hu in view of Madraswala teaches claim 15 as shown above and further teaches:
16. The memory controller of claim 15, wherein the memory interface is further configured to transmit the first operation command, an address, and the target index to the memory device through a data signal in response to the target index being assigned to the target operation parameter set. [Hu in view of Madraswala as shown above teaches the controller transmitting a read command comprising a trim tag, without sending updated parameter values, responsive to the parameter values for a scheduled operation for the trim tag matching the parameter values of the memory (see claim 10; Hu: col. 3, lines 33-65; col. 12, lines 15-23; Madraswala: para. 16-17, 64-65, 87-89; figs. 1, 4, 8) and further teaches a read command specifying an address (Hu: col. 3, lines 30-32; Madraswala: para. 76)]
Hu and Madraswala are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Hu and Madraswala, to modify the disclosures by Hu to include disclosures by Madraswala since they both teach data storage and access, wherein Madraswala is directed towards improvements in memory reading procedures (para. 2). Therefore, it would be applying a known technique (transmission of a read command with a read voltage offset profile identifier used by memory device to apply a corresponding profile specifying read voltage offsets, a controller performing tests for determining and storing read voltage offset profiles and associated identifiers to the memory) to a known device (system comprising a memory device having trim tags indicating corresponding parameter sets used in memory operations, the trim tags and the parameters sets being stored to the memory device during initialization) ready for improvement to yield predictable results (system comprising a memory device having trim tags indicating corresponding parameter sets used in memory operations, the trim tags and the parameters sets stored in the memory device by a controller during initialization after testing to provide for reduced error rate during runtime, where a trim tag corresponding to a parameter set to be used by the memory device for a memory operation may be received with a memory operation command in order to provide for improved reliability in selection of the appropriate memory operation parameters). MPEP 2143
As per claim 19,
19. An operating method of a memory controller, the operating method comprising: [Hu teaches a system comprising a controller comprising a processor and a memory device with a memory (col. 2, lines 21-35); Hu further teaches the memory device comprising a table comprising index values, or trim tags (col. 3, lines 33-58; fig. 1 and associated paragraphs)] generating a target operation parameter set corresponding to a current situation of the memory device; determining whether the target operation parameter is matched to one of the sample operation parameter sets and there is a target index assigned to the target operation parameter set; and transmitting one of the target index and the target operation parameter set to the memory device based on the determining. [Hu teaches the index values, or trim tags, used to identify a parameter set (e.g. read voltages) for memory operations, where the trim tags may be stored as a table in the memory device in association with corresponding data units (col. 3, lines 33-65; see col. 3, lines 57-58 on the memory also storing parameter values), where a parameter set in the memory may correspond to a sample operation parameter set; Hu teaches the controller retrieving a trim tag (target index) and comparing parameter values of a scheduled memory operation in the controller which matches the trim tag (target operation parameter set) against parameter values corresponding to parameter values stored in the memory (col. 4, line 53 – col. 5, line 20; col. 10, line 58 – col. 11, line 7; col. 11, lines 44 – col. 12, line 44; claim 1; figs. 1-2, 5 and associated paragraphs); responsive to the parameter values matching (the target operation parameter set is matched and assigned an index), Hu teaches abstaining from sending updated parameter values to the memory and performing the scheduled (e.g. read) operation (col. 10, lines 11-26; col. 12, lines 17-22; see col. 4, lines 7-19, col. 6, lines 11-45 indicating the parameter values associated with trim tags in the memory device and the updated parameter values sent by the controller may correspond to different circumstances (e.g. SLC/MLC mode, time since storage)) and, responsive to the parameter values not matching, transmitting updated parameter values to the memory device to overwrite the parameter values in the memory (Hu: col. 3, line 57 – col. 4, line 19; col. 4, line 53 – col. 5, line 31; col. 10, lines 26-34)]
Hu does not explicitly disclose, but Madraswala discloses:
the target index [Hu as shown above teaches the memory device comprising a table of trim tags corresponding to parameter sets to be used for memory operations, and, when the parameter values for a scheduled operation in the controller corresponding a retrieved trim tag matches the parameter values in the memory (i.e. the target operation parameter set already being in the memory), performing a memory operation without updating the parameters in the memory (please see the rejection above; col. 3, lines 33-65; col. 12, lines 15-23); where Hu does not explicitly disclose transmitting the trim tag to the memory for performing the operation, Madraswala teaches a controller sending a read voltage offset profile identifier with a read command, where the read voltage offset profile associated with the identifier is determined by the memory array for adjusting read voltages applied during the read operation as specified by the offsets in the profile (para. 16-17, 64-65, 87-89; figs. 1, 4, 8 and associated paragraphs; see para. 85 providing the profile identifiers and the profiles also being stored in a table; see para. 62 on interfacing between a memory controller and memory chip)] generating sample operation parameter sets and indices respectively assigned to the sample operation parameter sets to be stored as an offset table included in a memory device; [Hu does not explicitly disclose the controller generating and storing trim tags and parameter sets in the memory, but it does provide for the memory device performing initialization including setting values of memory device and storing an initial set of parameter values in the memory device (Hu: col. 3, lines 33-65; col. 13, lines 30-37); Madraswala teaches a memory controller generating read voltage offset profiles to be stored in a memory device, where the memory controller performs tests for optimal read voltage offsets for particular situations and thereby determines read voltage offset profiles to be used during operation of the memory, where the profiles can be stored in a in a lookup table of a memory device in association with profile identifiers (para. 82-86; fig. 8 and associated paragraphs), where the read voltage sets stored in association with voltage offset profile identifiers may correspond to sample operation parameter sets; where it would have been obvious for one of ordinary skill in the arts, provided with Hu’s disclosure of setting the parameter values during initialization and Madraswala’s disclosure of a memory controller performing tests to determine and store read voltage profiles and identifiers, to provide for a combination where the a controller may, during initialization, perform tests to determine and store the parameter values for the parameter sets and trim tags; doing so would provide for improved read efficiency by requiring fewer adjustments to be made during the runtime of the system]
Hu and Madraswala are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Hu and Madraswala, to modify the disclosures by Hu to include disclosures by Madraswala since they both teach data storage and access, wherein Madraswala is directed towards improvements in memory reading procedures (para. 2). Therefore, it would be applying a known technique (transmission of a read command with a read voltage offset profile identifier used by memory device to apply a corresponding profile specifying read voltage offsets, a controller performing tests for determining and storing read voltage offset profiles and associated identifiers to the memory) to a known device (system comprising a memory device having trim tags indicating corresponding parameter sets used in memory operations, the trim tags and the parameters sets being stored to the memory device during initialization) ready for improvement to yield predictable results (system comprising a memory device having trim tags indicating corresponding parameter sets used in memory operations, the trim tags and the parameters sets stored in the memory device by a controller during initialization after testing to provide for reduced error rate during runtime, where a trim tag corresponding to a parameter set to be used by the memory device for a memory operation may be received with a memory operation command in order to provide for improved reliability in selection of the appropriate memory operation parameters). MPEP 2143
As per claim 20, Hu in view of Madraswala teaches claim 19 as shown above and further teaches:
20. The operating method of claim 19, wherein the transmitting of one of the target index and the target generation parameter set to the memory device comprises: transmitting the target index to the memory device in response to the target index being assigned to the target operation parameter set; and [Hu in view of Madraswala as shown above teaches the controller transmitting a read command comprising a trim tag, without sending updated parameters, responsive to the parameter values for a scheduled operation for the trim tag matching the parameter values in memory (see claim 19; Hu: col. 3, lines 33-65; col. 12, lines 15-23; Madraswala: para. 16-17, 64-65, 87-89; figs. 1, 4, 8)] transmitting the target operation parameter set to the memory device in response to no target index being assigned to the target operation parameter set. [Hu in view of Madraswala teaches, if the parameter values of a scheduled operation corresponding to a retrieved trim tag and a copy of the parameter values in the memory do not match, transmitting updated parameter values to the memory device to overwrite the parameter values in the memory (see claim 10 above; Hu: col. 3, line 57 – col. 4, line 19; col. 4, line 53 – col. 5, line 31; col. 10, lines 26-34; see col. 3, line 667 on an instruction being sent for updating the parameter values)]
Hu and Madraswala are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Hu and Madraswala, to modify the disclosures by Hu to include disclosures by Madraswala since they both teach data storage and access, wherein Madraswala is directed towards improvements in memory reading procedures (para. 2). Therefore, it would be applying a known technique (transmission of a read command with a read voltage offset profile identifier used by memory device to apply a corresponding profile specifying read voltage offsets, a controller performing tests for determining and storing read voltage offset profiles and associated identifiers to the memory) to a known device (system comprising a memory device having trim tags indicating corresponding parameter sets used in memory operations, the trim tags and the parameters sets being stored to the memory device during initialization) ready for improvement to yield predictable results (system comprising a memory device having trim tags indicating corresponding parameter sets used in memory operations, the trim tags and the parameters sets stored in the memory device by a controller during initialization after testing to provide for reduced error rate during runtime, where a trim tag corresponding to a parameter set to be used by the memory device for a memory operation may be received with a memory operation command in order to provide for improved reliability in selection of the appropriate memory operation parameters). MPEP 2143
Claims 5, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Hu et al. (US 9251891 B1) in view of Madraswala et al. (US 20190102097 A1) in view of Shukla et al. (US 20180181462 A1).
As per claim 5, Hu in view of Madraswala teaches all the limitations of claim 4 as shown above. it does not explicitly disclose, but Shukla discloses:
5. The memory system of claim 4, wherein the memory controller is further configured to extract the sample operation parameter sets based on a use frequency of each operation parameter set from among the operation parameter sets respectively corresponding to the plurality of situations. [Hu in view of Madraswala as shown above teaches a controller performing tests to determine the voltage sets to store in the memory device (see claim 4; Madraswala: para. 82-86; fig. 8 and associated paragraph); Hu in view of Madraswala does not explicitly provide for the voltage sets being determined based on a use frequency, but Shukla provides for selection of voltage adjustments involving the most frequently successful adjustments for decoding data in memory cells (para. 22-23, 76, 88; fig. 3A, 5A and associated paragraphs)]
Hu, Madraswala, and Shukla and are analogous to the claimed invention because they are in the same field of endeavor involving data storage and memory access.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the disclosures provided by Hu in view of Madraswala with Shukla’s disclosures directed towards selection of read voltage adjustments involving the most frequently successful adjustments. Doing so would allow for a greater time and power efficiency in association with read operations (Shukla: para. 22)
As per claim 17, Hu in view of Madraswala teaches claim 10 as shown above and further teaches:
17. The memory controller of claim 10, wherein in an initialization period the index processor is further configured to, generate a plurality of operation parameter sets respectively corresponding to a plurality of situations of the memory device, and extract the sample operation parameter sets based on a use frequency of each operation parameter set from among the plurality of operation parameter sets respectively corresponding to the plurality of situations. [Hu does not explicitly disclose the processor generating and storing trim tags and parameter sets in the memory, but it does provide for the memory device performing initialization including setting values of memory device and storing an initial set of parameter values in the memory device (Hu: col. 3, lines 33-65; col. 13, lines 30-37); Madraswala teaches a memory controller generating read voltage offset profiles to be stored in a memory device, where the memory controller performs tests for optimal read voltage offsets for particular situations and thereby determines read voltage offset profiles to be used during operation of the memory, where the profiles can be stored in a in a lookup table of a memory device in association with profile identifiers (para. 82-86; fig. 8 and associated paragraphs), where the read voltage sets tested may correspond to operation parameter sets, and the read voltage sets stored in association with voltage offset profile identifiers may correspond to sample operation parameter sets; where it would have been obvious for one of ordinary skill in the arts, provided with Hu’s disclosure of setting the parameter values during initialization and Madraswala’s disclosure of a memory controller performing tests to determine and store read voltage profiles and identifiers, to provide for a combination where the a controller may, during initialization, perform tests to determine and store the parameter values for the parameter sets and trim tags; doing so would provide for improved read efficiency by requiring fewer adjustments to be made during the runtime of the system]
Hu and Madraswala are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Hu and Madraswala, to modify the disclosures by Hu to include disclosures by Madraswala since they both teach data storage and access, wherein Madraswala is directed towards improvements in memory reading procedures (para. 2). Therefore, it would be applying a known technique (transmission of a read command with a read voltage offset profile identifier used by memory device to apply a corresponding profile specifying read voltage offsets, a controller performing tests for determining and storing read voltage offset profiles and associated identifiers to the memory) to a known device (system comprising a memory device having trim tags indicating corresponding parameter sets used in memory operations, the trim tags and the parameters sets being stored to the memory device during initialization) ready for improvement to yield predictable results (system comprising a memory device having trim tags indicating corresponding parameter sets used in memory operations, the trim tags and the parameters sets stored in the memory device by a controller during initialization after testing to provide for reduced error rate during runtime, where a trim tag corresponding to a parameter set to be used by the memory device for a memory operation may be received with a memory operation command in order to provide for improved reliability in selection of the appropriate memory operation parameters). MPEP 2143
Hu in view of Madraswala does not explicitly disclose, but Shukla discloses:
based on a use frequency [Hu in view of Madraswala as shown above teaches a controller performing tests to determine the voltage sets to store in the memory device; it does not explicitly provide for the voltage sets being determined based on a use frequency, but Shukla provides for selection of voltage adjustments involving the most frequently successful adjustments for decoding data in memory cells (para. 22-23, 76, 88; fig. 3A, 5A and associated paragraphs)]
Hu, Madraswala, and Shukla and are analogous to the claimed invention because they are in the same field of endeavor involving data storage and memory access.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the disclosures provided by Hu in view of Madraswala with Shukla’s disclosures directed towards selection of read voltage adjustments involving the most frequently successful adjustments. Doing so would allow for a greater time and power efficiency in association with read operations (Shukla: para. 22)
As per claim 18, Hu in view of Madraswala in view of Shukla teaches claim 17 as shown above and further teaches:
18. The memory controller of claim 17, wherein a use frequency of the sample operation parameter sets extracted from among the operation parameter sets respectively corresponding to the plurality of situations is higher than a use frequency of remaining operation parameter sets from among the operation parameter sets respectively corresponding to the plurality of situations. [Hu in view of Madraswala in view of Shukla as shown above teaches a controller performing tests to select voltage sets to be stored in the memory device, where the most frequently successful voltage sets are selected (see claim 17 above; Madraswala: para. 82-86; Shukla: para. 22-23, 76, 88)]
Hu and Madraswala are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Hu and Madraswala, to modify the disclosures by Hu to include disclosures by Madraswala since they both teach data storage and access, wherein Madraswala is directed towards improvements in memory reading procedures (para. 2). Therefore, it would be applying a known technique (transmission of a read command with a read voltage offset profile identifier used by memory device to apply a corresponding profile specifying read voltage offsets, a controller performing tests for determining and storing read voltage offset profiles and associated identifiers to the memory) to a known device (system comprising a memory device having trim tags indicating corresponding parameter sets used in memory operations, the trim tags and the parameters sets being stored to the memory device during initialization) ready for improvement to yield predictable results (system comprising a memory device having trim tags indicating corresponding parameter sets used in memory operations, the trim tags and the parameters sets stored in the memory device by a controller during initialization after testing to provide for reduced error rate during runtime, where a trim tag corresponding to a parameter set to be used by the memory device for a memory operation may be received with a memory operation command in order to provide for improved reliability in selection of the appropriate memory operation parameters). MPEP 2143
Hu, Madraswala, and Shukla and are analogous to the claimed invention because they are in the same field of endeavor involving data storage and memory access.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the disclosures provided by Hu in view of Madraswala with Shukla’s disclosures directed towards selection of read voltage adjustments involving the most frequently successful adjustments. Doing so would allow for a greater time and power efficiency in association with read operations (Shukla: para. 22)
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Hu et al. (US 9251891 B1) in view of Madraswala et al. (US 20190102097 A1) in view of Ni et al. (CN 113064843 A).
As per claim 8, Hu in view of Madraswala teaches claim 1 as shown above and further teaches:
8. The memory system of claim 1, wherein the memory device is further configured to receive a read command, an address, and operation data from the memory controller and [Hu in view of Madraswala teaches, if the parameter values of a scheduled operation corresponding to a retrieved trim tag and a copy of the parameter values in the memory do not match (no index being assigned to the target operation parameter set), transmitting updated parameter values to the memory device to overwrite the parameter values in the memory (see claim 1 above; Hu: col. 3, line 57 – col. 4, line 19; col. 4, line 53 – col. 5, line 31; col. 10, lines 26-34); Hu in view of Madraswala teaches a read command comprising the trim tag (see claim 1 above; Hu: col. 3, lines 33-65; col. 12, lines 15-23; Madraswala: para. 16-17, 64-65, 87-89) and specifying an address (Hu: col. 3, lines 30-32; Madraswala: para. 76)]
Hu and Madraswala are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Hu and Madraswala, to modify the disclosures by Hu to include disclosures by Madraswala since they both teach data storage and access, wherein Madraswala is directed towards improvements in memory reading procedures (para. 2). Therefore, it would be applying a known technique (transmission of a read command with a read voltage offset profile identifier used by memory device to apply a corresponding profile specifying read voltage offsets) to a known device (system comprising a memory device having trim tags indicating corresponding parameter sets used in memory operations) ready for improvement to yield predictable results (system comprising a memory device having trim tags indicating corresponding parameter sets used in memory operations, where a trim tag corresponding to a parameter set to be used by the memory device for a memory operation may be received with a memory operation command in order to provide for improved reliability in selection of the appropriate memory operation parameters). MPEP 2143
Hu in view of Madraswala does not explicitly disclose, but Ni discloses:
to identify the operation data received by the memory device as one of the target index and the target operation parameter set based on a number of pieces of operation data received by the memory device. [Hu in view of Madraswala provides for an example of a trim tag comprising an integer value (e.g. 1) (Hu: col. 3, lines 33-45) and an example of a parameter set comprising a plurality of read voltages (Hu: col. 3, lines 33-45; also see Madraswala: fig. 4 giving an example of a plurality of voltage offset values in a profile); where data comprising an integer may necessarily comprise less data amount, such as number of representative bits/bytes or other units of data (pieces), than data comprising a plurality of read voltages or offsets, Hu in view of Madraswala does not explicitly disclose differentiating data types based on data amount; however, Ni discloses a memory chip that determines size of data received and classifying data as a first type or a second type of data based the data size being smaller or greater than a size threshold (please see the attached translation of Ni (CN 113064843 A): para. 8, 16-18), where the size threshold may be selected as needed (para. 73); it would have been obvious for one of ordinary skill in the arts, provided with the disclosures by Hu in view of Madraswala, directed to transferring data to memory device comprising, among others, an integer or a set of read voltages, and disclosures by Ni, directed towards a memory chip classifying data type of received data based on a selectable size threshold, to provide for a combination where the memory device may configured classify data received, including said integer or set of read voltages, based on the data being smaller or greater than a configurable size threshold, wherein units of measuring the data size (e.g. bits, bytes) may correspond to pieces]
Hu, Madraswala, and Ni are analogous to the claimed invention because they are in the same field of endeavor involving data storage and memory access.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Hu in view of Madrasawla and Ni, to modify the disclosures by Hu in view of Madraswala to include disclosures by Ni since they both teach data storage and memory access, wherein Ni is directed towards (improved storage capacity and access speed). Therefore, it would be applying a known technique (selecting a data size threshold used for classifying types of data received) to a known device (memory device configured to receive data including a trim tag comprising an integer and a set of read voltages) ready for improvement to yield predictable results (a memory device configurable for selecting a data size threshold used for classifying types of data received, where the memory device may be configured to select a size threshold for distinguishing between a data having a size corresponding an integer for identifying a trim tag and a greater size corresponding to a read voltage set in order to provide for a faster, preliminary method of classifying data received). MPEP 2143
As per claim 9, Hu in view of Madraswala in view of Ni teaches claim 8 as shown above and further teaches:
9. The memory system of claim 8, wherein the memory device is further configured to, identify the operation data as the target index in response to the number of pieces of operation data received by the memory device being a first number, and identify the operation data as the target operation parameter set in response to the number of pieces of operation data received by the memory device being a second number, wherein the second number is greater than the first number. [Hu in view of Madraswala in view of Ni as shown above teaches a memory device using a configurable size threshold to determine a data type, such as an integer for a trim tag or a read voltage set based on the data being smaller or greater than the configurable size threshold (see claim 8 above; Ni: para. 8, 16-18, 73), where the units of measuring size may correspond to pieces; where the first number may comprise a number in a range below said size threshold and the second number may comprise a number in a range greater than said size threshold.]
Hu, Madraswala, and Ni are analogous to the claimed invention because they are in the same field of endeavor involving data storage and memory access.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Hu in view of Madrasawla and Ni, to modify the disclosures by Hu in view of Madraswala to include disclosures by Ni since they both teach data storage and memory access, wherein Ni is directed towards (improved storage capacity and access speed). Therefore, it would be applying a known technique (selecting a data size threshold used for classifying types of data received) to a known device (memory device configured to receive data including a trim tag comprising an integer and a set of read voltages) ready for improvement to yield predictable results (a memory device configurable for selecting a data size threshold used for classifying types of data received, where the memory device may be configured to select a size threshold for distinguishing between a data having a size corresponding an integer for identifying a trim tag and a greater size corresponding to a read voltage set in order to provide for a faster, preliminary method of classifying data received). MPEP 2143
Claims 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Hu et al. (US 9251891 B1) in view of Madraswala et al. (US 20190102097 A1) in view of Hyun et al. (US 20140092683 A1).
As per claim 12, Hu in view of Madraswala teaches claim 11 as shown above. It does not explicitly disclose, but Hyun discloses:
12. The memory controller of claim 11, wherein the memory interface is further configured to transmit the target index to the memory device for a first clock cycle number. [Hu in view of Madraswala as shown above teaches a controller transmitting a command comprising a trim tag corresponding to parameter values, such as read voltages, for performing a memory operation as shown above (see claim 10-11; Hu: col. 3, lines 33-65; col. 12, lines 15-23; Madraswala: para. 16-17, 64-65, 87-89; figs. 1, 4, 8); Hu provides that its parameters may correspond to parameters other than read voltages and provides additional examples such as programming pulse length (col. 1, lines 19-21; col. 3, lines 37-40); Hyun provides for a memory device comprising adjustable read time parameters for performing read operations (para. 29, 82), where, according to a read command, a read operation may be carried out according to clock cycles specified by the read time parameter (para. 77); where it would have been obvious for one of ordinary skill in the arts, provided with the disclosures of Hu in view of Madraswala providing for transmission of a command comprising a trim tag corresponding to a parameter set, stored in the memory device, for performing read operations, and disclosures of Hyun, directed towards a memory device comprising read time parameters comprising clock cycles for performing read operations, to provide for a combination where trim tags may also indicate the desired read time parameter comprising clock cycles to be applied to the read operation to provide for a greater range of control over read operations by the memory controller.]
The disclosures by Hu, Madraswala, and Hyun are analogous because they are in the same field of endeavor of data storage and memory access.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hu in view of Madraswala and Hyun, to modify the teachings of Hu in view of Madraswala to include the teaching of Hyun since they both teach data storage and memory access, wherein Hyun is directed towards improved read time (para. 4). Therefore, it would be applying a known technique (controlling read operations according to an adjustable read time parameter specifying a clock cycle) to a known device (memory controller providing a trim tag indicating a parameter such as read voltages to be used for read operations) ready for improvement to yield predictable results (memory controller providing a trim tag indicating a parameter such as read voltages or clock cycles to be used for read operations in order to provide for a greater range of control by the controller for read operations). MPEP 2143
As per claim 14, Hu in view of Madraswala teaches claim 13 as shown above. It does not explicitly disclose, but Hyun discloses:
14. The memory controller of claim 13, wherein the memory interface is further configured to transmit the target operation parameter set to the memory device for a second clock cycle number, wherein the second clock cycle number is greater than a first clock cycle number. [Hu in view of Madraswala teaches, if the parameter values of a scheduled operation corresponding to a retrieved trim tag and a copy of the parameter values of the memory do not match, transmitting updated parameter values to the memory device to overwrite the parameter values in the memory (see claim 10, 13 above; Hu: col. 3, line 57 – col. 4, line 19; col. 4, line 53 – col. 5, line 31; col. 10, lines 26-34); Hu provides that its parameters may correspond to parameters other than read voltages and provides additional examples such as programming pulse length (col. 1, lines 19-21; col. 3, lines 37-40); Hyun provides for a memory device comprising adjustable read time parameters for performing read operations (para. 29, 82), where, according to a read command, a read operation may be carried out according to clock cycles specified by the read time parameter (para. 77); where it would have been obvious for one of ordinary skill in the arts, provided with the disclosures of Hu in view of Madraswala providing for transmission of parameter values for updating parameter values stored in a memory device, and disclosures of Hyun, directed towards a memory device comprising an adjustable read time parameters comprising clock cycles for performing read operations, to provide for a combination where a controller may also adjust parameters in the memory device for performing read operations by sending updated parameters which may comprise read voltages as well as clock cycles; doing so would provide for a greater range of control over read operations by the memory controller; where the clock cycles in the memory device are adjusted by an updated (second) clock cycle number, the updated clock cycle number may necessarily be different, for example, by being larger, than the clock cycle number (first) originally stored in the memory device (see Hyun: para. 67, fig. 3E providing an example of a new read time that is longer than a default read time)]
The disclosures by Hu, Madraswala, and Hyun are analogous because they are in the same field of endeavor of data storage and memory access.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hu in view of Madraswala and Hyun, to modify the teachings of Hu in view of Madraswala to include the teaching of Hyun since they both teach data storage and memory access, wherein Hyun is directed towards improved read time (para. 4). Therefore, it would be applying a known technique (controlling read operations according to an adjustable read time parameter specifying a clock cycle) to a known device (memory controller providing updated parameter values such as read voltages to be used for read operations) ready for improvement to yield predictable results (memory controller providing updated parameter values such as read voltages or clock cycles to be used for read operations in order to provide for a greater range of control by the controller for read operations). MPEP 2143
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Lee (US 20220093194 A1) teaches a command generator outputting a read command with an index to a buffer, the buffer locating the relevant read voltages from a voltage table and outputting the voltages.
Conclusion
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/E.Y.K./Examiner, Art Unit 2135 /JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135