DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities: on lines 1 and 5 of paragraph [0012] and on line 2 of Clause 6 in paragraph [0114], the recitation “an control switch” should be changed to “a control switch”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7-9,14-15 and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al. (US 2019/0214973).
For claims 1, 17 and 20, Figure 1A of Choi et al. teaches a solid state switch device, comprising: a controllable switch (114) comprising a control terminal (gate), a first channel terminal (drain), and a second channel terminal (source), and arranged to be switched between an off-state and an on-state, wherein in the on-state the controllable switch (114) allows a current to flow between the first channel terminal (drain) and the second channel terminal (source); and a first compensation circuit (all elements in Figure 1A except for 114 and 116) configured to: generate a first boost current (output current of 112 to gate of 114) based on a voltage difference between the first channel terminal and the second channel terminal (see [0047]-[0048], which discloses the generation of a boost current based on the voltage Vout being lower than Vin-offset voltage, thereby based on the drain-source voltage); and apply the first boost current to the control terminal (gate of 114, see [0047]) to charge a switch capacitance (the parasitic capacitance of 114) of the controllable switch (114, see [0047]-[0048], the current generated by the charge pump is increased, so it is inherent that as the driver current is higher, the gate capacitance inherently charges faster). Note that the apparatus as discussed also meets all the limitations of method claim 17, and a compensation circuit of claim 20.
For claims 2 and 18, it is seen that Figure 1A of Choi et al. teaches wherein the first compensation circuit (all elements in Figure 1A except for 114 and 116) is configured to apply the first boost current (output current of 112 to gate of 114) to the control terminal (gate) of the controllable switch (112) during a transition of the controllable switch from the off-state to the on-state (also see [0047]-0048]).
For claim 3, it is seen that Figure 1A of Choi et al. teaches wherein the first compensation circuit (all elements in Figure 1A except for 114 and 116) is configured to apply the first boost current (output current of 112 to gate of 114) until the voltage difference between the first channel terminal (drain) and the second channel terminal (source) is less than or equal to a difference threshold voltage (see [0047]-0048]).
For claim 4, it is seen that Figure 1A of Choi et al. teaches wherein the first compensation circuit (all elements in Figure 1A except for 114 and 116) is configured to, during the application of the first boost current (output current of 112 to gate of 114), adjust the first boost current proportionally (output current of 112 to gate of 114) with any changes to the voltage difference between the first channel terminal and the second channel terminal (the change in the drain voltage and/or source voltage of 114 would cause the comparison of 120 changes, and thus it would change the boost current, also see [0047]-[0048]).
For claim 5, it is seen that Figure 1A of Choi et al. teaches wherein during application of the first boost current (output current of 112 to gate of 114), the first boost current (output current of 112 to gate of 114) is of fixed amplitude, and wherein the first compensation circuit (all elements in Figure 1A except for 114 and 116) is configured to: apply the first boost current (output current of 112 to gate of 114) for a time period; and determine the fixed amplitude and the time period based on the voltage difference between the first channel terminal (drain of 114) and the second channel terminal (source of 114) at a time prior to application of the first boost current (the current output of 112 depends on the drain voltage and source voltage of 114, also see [0047]-[0048]).
For claim 7, Figure 1A of Choi et al. teaches a second compensation circuit (116), wherein the second compensation circuit (116) is configured to: generate a second boost current (output current of 116 to gate of 114) of a predetermined fixed amplitude; and apply the second boost current (output current of 116 to gate of 114) to the control terminal (gate of 114) to charge the switch capacitance (the parasitic capacitance of 114) of the controllable switch (114) during a transition of the controllable switch from the off-state to the on-state (also see [0047]-[0048]).
For claims 8 and 19, Figure 1A of Choi et al. teaches wherein the second boost current (output current of 116 to gate of 114) is applied to charge the switch capacitance (the parasitic capacitance of 114) of the controllable switch (114) during a period of time after the voltage difference between the first channel terminal (drain of 114) and the second channel terminal (source of 114) is less than or equal to a difference threshold voltage (also see [0047]-[0048]).
For claim 9, it is also seen that Figure 1A of Choi et al. teaches wherein the predetermined fixed amplitude of the second boost current (output current of 116) is less than a peak amplitude of the first boost current (output current of 112. Note that 116 provides current for a soft-start while driver 112 provides fast main switch turn-on and charge-pump 110 support a large driver current, also see [0047]-[0048]).
For claim 14, Figure 1A of Choi et al. teaches wherein the controllable switch (114) comprises a first Field Effect Transistor (FET) (114), wherein the control terminal (gate) comprises a gate terminal of the first FET (gate of 114).
For claim 15, Figure 1A of Choi et al. teaches wherein the switch capacitance (the parasitic capacitance of 114) of the controllable switch (114) is a parasitic gate-source capacitor (Cgs) of the first FET (inherently because every FET has the parasitic gate-source capacitance).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 2019/0214973) in view of Li et al. (US 2016/0020760).
For claim 16, Figure 1A of Choi et al. teaches all the limitations of this claim as discussed in claim 1 above except for wherein the controllable switch (114) further comprises a second FET, and wherein a source terminal of the first FET is coupled to a source terminal of the second FET, wherein the control terminal of the controllable switch further comprises a gate terminal of the second FET, and wherein the second channel terminal comprises a drain terminal of the second FET. However, Figure 2 of Li et al. teaches a controllable switch (1) includes a first FET (M1) and a second FET (M2), and wherein a source terminal of the first FET (M1) is coupled to a source terminal of the second FET (M2), wherein the control terminal (gate VG connected to gates of M1 and M2) of the controllable switch further comprises a gate terminal of the second FET (M2), and wherein the second channel terminal comprises a drain terminal of the second FET (M2). Therefore, it would have been obvious to one having ordinary skilled in the art at the time before the invention was effectively filed to modify the circuit in Figure 1A of Choi et al. by replacing the broad controllable switch (114, Figure 1A of Choi et al.) with the specific controllable switch (1) with first and second FETs (M1 and M2) as taught in Figure 2 of Li et al. the purpose of reducing the parasitic capacitance of the switch so that signal deterioration is suppressed (Li et al., see [0057]-[0058] and [0061]). Thus, this combination and modification now teaches the controllable switch with the first FET (M1) and the second FET (M2) with the connections as recited in the claim.
Allowable Subject Matter
Claim 6 and 10-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Maier et al. (USP 11,031,929) in Figure 2C teaches a solid state switch device comprising a controllable switch (10), and a compensation circuit (19, 14, and 16a-16c.
Any inquiry concerning this communication or earlier communications from the examiner should be directly to Examiner Long Nguyen whose telephone number is (571) 272-1753. The Examiner can normally be reached on Monday to Friday from 8:30am to 5:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch, can be reached at (571) 270-7101. The fax number for this group is (571) 273-8300.
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/Long Nguyen/
Primary Examiner
Art Unit 2836
Prosecution Insights