Prosecution Insights
Last updated: April 19, 2026
Application No. 18/985,636

ENHANCEMENTS FOR MULTIPLE DATA PLANE READ COMMANDS

Non-Final OA §103
Filed
Dec 18, 2024
Examiner
RUIZ, ARACELIS
Art Unit
2139
Tech Center
2100 — Computer Architecture & Software
Assignee
Micron Technology, Inc.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
2y 7m
To Grant
99%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allow Rate
709 granted / 814 resolved
+32.1% vs TC avg
Moderate +12% lift
Without
With
+12.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
22 currently pending
Career history
836
Total Applications
across all art units

Statute-Specific Performance

§101
5.9%
-34.1% vs TC avg
§103
55.1%
+15.1% vs TC avg
§102
16.5%
-23.5% vs TC avg
§112
9.6%
-30.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 814 resolved cases

Office Action

§103
DETAILED ACTION Claims 1-7 and 15-28 are present for examination. Claims 8-14 and 29-35 have been cancelled. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Election/Restrictions Applicant’s election without traverse of Species I (claims 1-7 and 15-28) in the reply filed on 01/30/2026 is acknowledged. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-4, 6, 5-18, 20, 22-25 and 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Guo et al. (US2016/0283111) in view of Fu et al. (US 2024/0086317). With respect claim 1, Guo et al. teaches receiving a plurality of read commands each associated with accessing a respective plane of a memory device (see paragraph 17; read operations may arrive from the host device accessing a target die and target plane); determining whether a quantity of planes associated with the plurality of read commands satisfies a threshold based at least in part on receiving the plurality of read commands (see Figs. 3-4 and paragraphs 18-19; it is determined if there are 2 or more matching read requests that are directed to the same target die but to different planes on the target die (i.e., threshold satisfied)); and outputting a multi-plane read command to the memory device based at least in part on the quantity of planes satisfying the threshold (see paragraphs 18-20; if at operation 430 there are matches, then control passes to operation 435 and the controller 142 combines matching read requests to form a combined read request (i.e., multi-plane read request)), wherein the multi-plane read command comprises a logical command that comprises the plurality of read commands (see paragraph 19; at operation 430 the controller 142 will combine the three read requests directed to die 15 and execute the read requests concurrently (operation 440)). Guo et al. does not teach wherein the multi-plane read command comprises a logical command that comprises the plurality of read commands and a plurality of data transfer commands corresponding to a plurality of planes. However, Fu et al. teaches wherein because there may be multiple pages in a block, a read operation may include multiple batches of multi-plane cache read commands and data transfer commands (see paragraph 25)… Cache Read Data Transfer Phase 304 may comprise many rounds of data reading from storage array and data transferring. Each round may comprise one subsequent batch of multi-plane cache read commands followed by a set of data transfer commands (see paragraph 38). It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Guo et al. to include the above mentioned to efficiently retrieve valid data units from these identified blocks (see Fu, paragraph 17). With respect claim 2, Guo et al. teaches receiving a second plurality of read commands (see paragraph 17; read operations may arrive from the host device accessing a target die and target plane); determining that a second quantity of planes associated with the second plurality of read commands fails to satisfy the threshold (see Figs. 3-4 and paragraphs 18-19; it is determined if there are no matching read requests that are directed to the same target die but to different planes on the target die (i.e., threshold not satisfied)); generating a plurality of single-plane read commands based at least in part on the second quantity of planes failing to satisfy the threshold (see paragraph 18; if, at operation 430 there are no matches then control passes to operation 440 and the controller 142 executes read operations in accordance with normal operations, e.g., the read operations may be executed in a first-in, first-out (FIFO) manner (i.e., single-plane read request)); and outputting the plurality of single-plane read commands (see paragraph 18; if, at operation 430 there are no matches then control passes to operation 440 and the controller 142 executes read operations in accordance with normal operations, e.g., the read operations may be executed in a first-in, first-out (FIFO) manner). With respect claim 3, Guo et al. teaches wherein each single-plane read command of the plurality of single-plane read commands comprises a respective read command of the plurality of read commands (see paragraph 18; if, at operation 430 there are no matches then control passes to operation 440 and the controller 142 executes read operations in accordance with normal operations, e.g., the read operations may be executed in a first-in, first-out (FIFO) manner (i.e., single-plane read request)). Guo et al. does not teach wherein single-plane read commands comprises a respective read command of the plurality of read commands and a data transfer command for the respective plane. However, Fu et al. teaches Cache Read Data Transfer Phase 304 may comprise many rounds of data reading from storage array and data transferring (see paragraph 38). It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Guo et al. to include the above mentioned to efficiently retrieve valid data units from these identified blocks (see Fu, paragraph 17). With respect claim 4, Guo et al. teaches wherein the threshold is based at least in part on a quantity of memory dies of the memory system (see paragraph 14; the memory 150 comprises a number M dies, each of which is divided into four planes. Also, in paragraphs 18-20; it is determined if there are 2 or more matching read requests that are directed to a same one target die but to different planes (i.e., request must be directed to 2 or more planes of a same die)). With respect claim 6, Guo et al. teaches wherein storing the plurality of read commands comprises: storing a respective read command of the plurality of read commands in a respective logical unit queue of the one or more logical unit queues based at least in part on a memory die index of the respective read command, a plane index of the respective read command, a command type of the respective read command, or any combination thereof (see paragraph 16-17; controller 142 places the read operation in read queue…the respective read requests in the read queue may each have a die and a plane on the die associated with them) . With respect claim 15, Guo et al. teaches receive a plurality of read commands each associated with accessing a respective plane of a memory device (see paragraph 17; read operations may arrive from the host device accessing a target die and target plane); determine whether a quantity of planes associated with the plurality of read commands satisfies a threshold based at least in part on receiving the plurality of read commands (see Figs. 3-4 and paragraphs 18-19; it is determined if there are 2 or more matching read requests that are directed to the same target die but to different planes on the target die (i.e., threshold satisfied)); and output a multi-plane read command to the memory device based at least in part on the quantity of planes satisfying the threshold (see paragraphs 18-20; if at operation 430 there are matches, then control passes to operation 435 and the controller 142 combines matching read requests to form a combined read request (i.e., multi-plane read request)), wherein the multi-plane read command comprises a logical command that comprises the plurality of read commands (see paragraph 19; at operation 430 the controller 142 will combine the three read requests directed to die 15 and execute the read requests concurrently (operation 440)). Guo et al. does not teach wherein the multi-plane read command comprises a logical command that comprises the plurality of read commands and a plurality of data transfer commands corresponding to a plurality of planes. However, Fu et al. teaches wherein because there may be multiple pages in a block, a read operation may include multiple batches of multi-plane cache read commands and data transfer commands (see paragraph 25)… Cache Read Data Transfer Phase 304 may comprise many rounds of data reading from storage array and data transferring. Each round may comprise one subsequent batch of multi-plane cache read commands followed by a set of data transfer commands (see paragraph 38). It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Guo et al. to include the above mentioned to efficiently retrieve valid data units from these identified blocks (see Fu, paragraph 17). With respect claim 16, Guo et al. teaches wherein the instructions are further executable by the one or more processors to: receive a second plurality of read commands (see paragraph 17; read operations may arrive from the host device accessing a target die and target plane); determine that a second quantity of planes associated with the second plurality of read commands fails to satisfy the threshold (see Figs. 3-4 and paragraphs 18-19; it is determined if there are no matching read requests that are directed to the same target die but to different planes on the target die (i.e., threshold not satisfied)); generate a plurality of single-plane read commands based at least in part on the second quantity of planes failing to satisfy the threshold (see paragraph 18; if, at operation 430 there are no matches then control passes to operation 440 and the controller 142 executes read operations in accordance with normal operations, e.g., the read operations may be executed in a first-in, first-out (FIFO) manner (i.e., single-plane read request)); and output the plurality of single-plane read commands (see paragraph 18; if, at operation 430 there are no matches then control passes to operation 440 and the controller 142 executes read operations in accordance with normal operations, e.g., the read operations may be executed in a first-in, first-out (FIFO) manner). With respect claim 17, Guo et al. teaches wherein each single-plane read command of the plurality of single-plane read commands comprises a respective read command of the plurality of read commands (see paragraph 18; if, at operation 430 there are no matches then control passes to operation 440 and the controller 142 executes read operations in accordance with normal operations, e.g., the read operations may be executed in a first-in, first-out (FIFO) manner (i.e., single-plane read request)) . Guo et al. does not teach wherein single-plane read commands comprises a respective read command of the plurality of read commands and a data transfer command for the respective plane. However, Fu et al. teaches Cache Read Data Transfer Phase 304 may comprise many rounds of data reading from storage array and data transferring (see paragraph 38). It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Guo et al. to include the above mentioned to efficiently retrieve valid data units from these identified blocks (see Fu, paragraph 17). With respect claim 18, Guo et al. teaches wherein the threshold is based at least in part on a quantity of memory dies of a memory system (see paragraph 14; the memory 150 comprises a number M dies, each of which is divided into four planes. Also, in paragraphs 18-20; it is determined if there are 2 or more matching read requests that are directed to a same one target die but to different planes (i.e., request must be directed to 2 or more planes of a same die)). With respect claim 20, Guo et al. teaches store a respective read command of the plurality of read commands in a respective logical unit queue of the one or more logical unit queues based at least in part on a memory die index of the respective read command, a plane index of the respective read command, a command type of the respective read command, or any combination thereof (see paragraph 16-17; controller 142 places the read operation in read queue…the respective read requests in the read queue may each have a die and a plane on the die associated with them). With respect claim 22, Guo et al. teaches one or more memory devices (see Fig. 1 and paragraph 12; one or more memory devices 140); and processing circuitry coupled with the one or more memory devices (see Fig. 1 and paragraph 11; CPU package and processor 110 coupled to memory devices) and configured to cause the memory system to: receive a plurality of read commands each associated with accessing a respective plane of a memory device (see paragraph 17; read operations may arrive from the host device accessing a target die and target plane); determine whether a quantity of planes associated with the plurality of read commands satisfies a threshold based at least in part on receiving the plurality of read commands (see Figs. 3-4 and paragraphs 18-19; it is determined if there are 2 or more matching read requests that are directed to the same target die but to different planes on the target die (i.e., threshold satisfied)); and output a multi-plane read command to the memory device based at least in part on the quantity of planes satisfying the threshold (see paragraphs 18-20; if at operation 430 there are matches, then control passes to operation 435 and the controller 142 combines matching read requests to form a combined read request (i.e., multi-plane read request)), wherein the multi-plane read command comprises a logical command that comprises the plurality of read commands (see paragraph 19; at operation 430 the controller 142 will combine the three read requests directed to die 15 and execute the read requests concurrently (operation 440)). Guo et al. does not teach wherein the multi-plane read command comprises a logical command that comprises the plurality of read commands and a plurality of data transfer commands corresponding to a plurality of planes. However, Fu et al. teaches wherein because there may be multiple pages in a block, a read operation may include multiple batches of multi-plane cache read commands and data transfer commands (see paragraph 25)… Cache Read Data Transfer Phase 304 may comprise many rounds of data reading from storage array and data transferring. Each round may comprise one subsequent batch of multi-plane cache read commands followed by a set of data transfer commands (see paragraph 38). It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Guo et al. to include the above mentioned to efficiently retrieve valid data units from these identified blocks (see Fu, paragraph 17). With respect claim 23, Guo et al. teaches receive a second plurality of read commands (see paragraph 17; read operations may arrive from the host device accessing a target die and target plane); determine that a second quantity of planes associated with the second plurality of read commands fails to satisfy the threshold (see Figs. 3-4 and paragraphs 18-19; it is determined if there are no matching read requests that are directed to the same target die but to different planes on the target die (i.e., threshold not satisfied)); generate a plurality of single-plane read commands based at least in part on the second quantity of planes failing to satisfy the threshold (see paragraph 18; if, at operation 430 there are no matches then control passes to operation 440 and the controller 142 executes read operations in accordance with normal operations, e.g., the read operations may be executed in a first-in, first-out (FIFO) manner (i.e., single-plane read request)); and output the plurality of single-plane read commands (see paragraph 18; if, at operation 430 there are no matches then control passes to operation 440 and the controller 142 executes read operations in accordance with normal operations, e.g., the read operations may be executed in a first-in, first-out (FIFO) manner). With respect claim 24, Guo et al. teaches wherein each single-plane read command of the plurality of single-plane read commands comprises a respective read command of the plurality of read commands (see paragraph 18; if, at operation 430 there are no matches then control passes to operation 440 and the controller 142 executes read operations in accordance with normal operations, e.g., the read operations may be executed in a first-in, first-out (FIFO) manner (i.e., single-plane read request)). Guo et al. does not teach wherein single-plane read commands comprises a respective read command of the plurality of read commands and a data transfer command for the respective plane. However, Fu et al. teaches Cache Read Data Transfer Phase 304 may comprise many rounds of data reading from storage array and data transferring (see paragraph 38). It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Guo et al. to include the above mentioned to efficiently retrieve valid data units from these identified blocks (see Fu, paragraph 17). With respect claim 25, Guo et al. teaches wherein the threshold is based at least in part on a quantity of memory dies of the memory system (see paragraph 14; the memory 150 comprises a number M dies, each of which is divided into four planes. Also, in paragraphs 18-20; it is determined if there are 2 or more matching read requests that are directed to a same one target die but to different planes (i.e., request must be directed to 2 or more planes of a same die)). With respect claim 27, Guo et al. teaches wherein storing the plurality of read commands comprises the processing circuitry configured to cause the memory system to: store a respective read command of the plurality of read commands in a respective logical unit queue of the one or more logical unit queues based at least in part on a memory die index of the respective read command, a plane index of the respective read command, a command type of the respective read command, or any combination thereof (see paragraph 16-17; controller 142 places the read operation in read queue…the respective read requests in the read queue may each have a die and a plane on the die associated with them). Claim(s) 7, 21 and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Guo et al. (US2016/0283111) and Fu et al. (US 2024/0086317) as applied to claims 1, 15 and 22 above, and further in view of Cariello (US2024/0054971). With respect claim 7, Guo et al. and Fu et al. do not teach wherein one or more read commands of the plurality of read commands are associated with accessing a sub-portion of a page of a plane. However, Cariello et al. teaches wherein if a first portion of data was stored with the multi-plane write operation, then the first portion of data may be read via a multi-plane read operation (see paragraphs 13 and 38). It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Guo et al. and Fu et al. to include the above mentioned to benefit the memory system may from an increase in reading efficiency while using a multi-plane read operation (see Cariello, paragraph 69). With respect claim 21, Guo et al and Fu et al. do not teach wherein one or more read commands of the plurality of read commands are associated with accessing a sub-portion of a page of a plane. However, Cariello et al. teaches wherein if a first portion of data was stored with the multi-plane write operation, then the first portion of data may be read via a multi-plane read operation (see paragraphs 13 and 38). It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Guo et al. and Fu et al. to include the above mentioned to benefit the memory medium may from an increase in reading efficiency while using a multi-plane read operation (see Cariello, paragraph 69). With respect claim 28, Guo et al. and Fu et al. do not teach wherein one or more read commands of the plurality of read commands are associated with accessing a sub-portion of a page of a plane. However, Cariello et al. teaches wherein if a first portion of data was stored with the multi-plane write operation, then the first portion of data may be read via a multi-plane read operation (see paragraphs 13 and 38). It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Guo et al. and Fu et al. to include the above mentioned to benefit the memory system may from an increase in reading efficiency while using a multi-plane read operation (see Cariello, paragraph 69). Allowable Subject Matter Claim 5, 19 and 26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Guo et al. (US2016/0283111) teaches wherein read operations received in controller 142 may be placed in a read queue 310 (see paragraph 15); and wherein the controller 142 scans the read queue 310 for read requests that are directed to the same target die but to different planes on the target die (see paragraph 18). However, Guo et al. does not teach wherein determining whether the quantity of planes satisfies the threshold is based at least in part on determining the quantity of logical unit queues as recited in claims 5, 19 and 26. Sankaranarayanan (US11,868,655) teaches processing logic can insert the memory access command into a queue associated with the plane (see column 12, lines 26-29). However, Sankaranarayanan does not teach wherein determining whether the quantity of planes satisfies the threshold is based at least in part on determining the quantity of logical unit queues as recited in claims 5, 19 and 26. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Fisher et al. (US2023/0063564) teaches multi-plane switching of non-volatile memory). Rho (US11,645,008) teaches memory system and operating method for controlling multi-plane read operation. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARACELIS RUIZ whose telephone number is (571)270-1038. The examiner can normally be reached Monday-Friday 11:00am-7:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald G. Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ARACELIS RUIZ/ Primary Examiner, Art Unit 2139
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Prosecution Timeline

Dec 18, 2024
Application Filed
Feb 21, 2026
Non-Final Rejection — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
99%
With Interview (+12.5%)
2y 7m
Median Time to Grant
Low
PTA Risk
Based on 814 resolved cases by this examiner. Grant probability derived from career allow rate.

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